drivers/gpu/drm/rcar-du/rcar_du_group.c

   1 /*
   2  * rcar_du_group.c  --  R-Car Display Unit Channels Pair
   3  *
   4  * Copyright (C) 2013 Renesas Corporation
   5  *
   6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 /*
  15  * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
  16  * unit, timings generator, ...) and device-global resources (start/stop
  17  * control, planes, ...) shared between the two CRTCs.
  18  *
  19  * The R8A7790 introduced a third CRTC with its own set of global resources.
  20  * This would be modeled as two separate DU device instances if it wasn't for
  21  * a handful or resources that are shared between the three CRTCs (mostly
  22  * related to input and output routing). For this reason the R8A7790 DU must be
  23  * modeled as a single device with three CRTCs, two sets of "semi-global"
  24  * resources, and a few device-global resources.
  25  *
  26  * The rcar_du_group object is a driver specific object, without any real
  27  * counterpart in the DU documentation, that models those semi-global resources.
  28  */
  29
  30 #include <linux/io.h>
  31
  32 #include "rcar_du_drv.h"
  33 #include "rcar_du_group.h"
  34 #include "rcar_du_regs.h"
  35
  36 static u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg)
  37 {
  38         return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg);
  39 }
  40
  41 static void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data)
  42 {
  43         rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data);
  44 }
  45
  46 static void rcar_du_group_setup(struct rcar_du_group *rgrp)
  47 {
  48         /* Enable extended features */
  49         rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE);
  50         rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G);
  51         rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3);
  52         rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE);
  53         rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5);
  54
  55         /* Use DS1PR and DS2PR to configure planes priorities and connects the
  56          * superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
  57          */
  58         rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
  59 }
  60
  61 /*
  62  * rcar_du_group_get - Acquire a reference to the DU channels group
  63  *
  64  * Acquiring the first reference setups core registers. A reference must be held
  65  * before accessing any hardware registers.
  66  *
  67  * This function must be called with the DRM mode_config lock held.
  68  *
  69  * Return 0 in case of success or a negative error code otherwise.
  70  */
  71 int rcar_du_group_get(struct rcar_du_group *rgrp)
  72 {
  73         if (rgrp->use_count)
  74                 goto done;
  75
  76         rcar_du_group_setup(rgrp);
  77
  78 done:
  79         rgrp->use_count++;
  80         return 0;
  81 }
  82
  83 /*
  84  * rcar_du_group_put - Release a reference to the DU
  85  *
  86  * This function must be called with the DRM mode_config lock held.
  87  */
  88 void rcar_du_group_put(struct rcar_du_group *rgrp)
  89 {
  90         --rgrp->use_count;
  91 }
  92
  93 static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
  94 {
  95         rcar_du_group_write(rgrp, DSYSR,
  96                 (rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES | DSYSR_DEN)) |
  97                 (start ? DSYSR_DEN : DSYSR_DRES));
  98 }
  99
 100 void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
 101 {
 102         /* Many of the configuration bits are only updated when the display
 103          * reset (DRES) bit in DSYSR is set to 1, disabling *both* CRTCs. Some
 104          * of those bits could be pre-configured, but others (especially the
 105          * bits related to plane assignment to display timing controllers) need
 106          * to be modified at runtime.
 107          *
 108          * Restart the display controller if a start is requested. Sorry for the
 109          * flicker. It should be possible to move most of the "DRES-update" bits
 110          * setup to driver initialization time and minimize the number of cases
 111          * when the display controller will have to be restarted.
 112          */
 113         if (start) {
 114                 if (rgrp->used_crtcs++ != 0)
 115                         __rcar_du_group_start_stop(rgrp, false);
 116                 __rcar_du_group_start_stop(rgrp, true);
 117         } else {
 118                 if (--rgrp->used_crtcs == 0)
 119                         __rcar_du_group_start_stop(rgrp, false);
 120         }
 121 }
 122
 123 void rcar_du_group_restart(struct rcar_du_group *rgrp)
 124 {
 125         __rcar_du_group_start_stop(rgrp, false);
 126         __rcar_du_group_start_stop(rgrp, true);
 127 }