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drm/rockchip: vop: Add yuv plane support
[deliverable/linux.git] / drivers / gpu / drm / rockchip / rockchip_drm_vop.c
1 /*
2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <drm/drm.h>
16 #include <drm/drmP.h>
17 #include <drm/drm_crtc.h>
18 #include <drm/drm_crtc_helper.h>
19 #include <drm/drm_plane_helper.h>
20
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/clk.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/component.h>
29
30 #include <linux/reset.h>
31 #include <linux/delay.h>
32
33 #include "rockchip_drm_drv.h"
34 #include "rockchip_drm_gem.h"
35 #include "rockchip_drm_fb.h"
36 #include "rockchip_drm_vop.h"
37
38 #define VOP_REG(off, _mask, s) \
39 {.offset = off, \
40 .mask = _mask, \
41 .shift = s,}
42
43 #define __REG_SET_RELAXED(x, off, mask, shift, v) \
44 vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift)
45 #define __REG_SET_NORMAL(x, off, mask, shift, v) \
46 vop_mask_write(x, off, (mask) << shift, (v) << shift)
47
48 #define REG_SET(x, base, reg, v, mode) \
49 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
50
51 #define VOP_WIN_SET(x, win, name, v) \
52 REG_SET(x, win->base, win->phy->name, v, RELAXED)
53 #define VOP_CTRL_SET(x, name, v) \
54 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
55
56 #define VOP_WIN_GET(x, win, name) \
57 vop_read_reg(x, win->base, &win->phy->name)
58
59 #define VOP_WIN_GET_YRGBADDR(vop, win) \
60 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
61
62 #define to_vop(x) container_of(x, struct vop, crtc)
63 #define to_vop_win(x) container_of(x, struct vop_win, base)
64
65 struct vop_win_state {
66 struct list_head head;
67 struct drm_framebuffer *fb;
68 dma_addr_t yrgb_mst;
69 struct drm_pending_vblank_event *event;
70 };
71
72 struct vop_win {
73 struct drm_plane base;
74 const struct vop_win_data *data;
75 struct vop *vop;
76
77 struct list_head pending;
78 struct vop_win_state *active;
79 };
80
81 struct vop {
82 struct drm_crtc crtc;
83 struct device *dev;
84 struct drm_device *drm_dev;
85 bool is_enabled;
86
87 int connector_type;
88 int connector_out_mode;
89
90 /* mutex vsync_ work */
91 struct mutex vsync_mutex;
92 bool vsync_work_pending;
93 struct completion dsp_hold_completion;
94
95 const struct vop_data *data;
96
97 uint32_t *regsbak;
98 void __iomem *regs;
99
100 /* physical map length of vop register */
101 uint32_t len;
102
103 /* one time only one process allowed to config the register */
104 spinlock_t reg_lock;
105 /* lock vop irq reg */
106 spinlock_t irq_lock;
107
108 unsigned int irq;
109
110 /* vop AHP clk */
111 struct clk *hclk;
112 /* vop dclk */
113 struct clk *dclk;
114 /* vop share memory frequency */
115 struct clk *aclk;
116
117 /* vop dclk reset */
118 struct reset_control *dclk_rst;
119
120 int pipe;
121
122 struct vop_win win[];
123 };
124
125 enum vop_data_format {
126 VOP_FMT_ARGB8888 = 0,
127 VOP_FMT_RGB888,
128 VOP_FMT_RGB565,
129 VOP_FMT_YUV420SP = 4,
130 VOP_FMT_YUV422SP,
131 VOP_FMT_YUV444SP,
132 };
133
134 struct vop_reg_data {
135 uint32_t offset;
136 uint32_t value;
137 };
138
139 struct vop_reg {
140 uint32_t offset;
141 uint32_t shift;
142 uint32_t mask;
143 };
144
145 struct vop_ctrl {
146 struct vop_reg standby;
147 struct vop_reg data_blank;
148 struct vop_reg gate_en;
149 struct vop_reg mmu_en;
150 struct vop_reg rgb_en;
151 struct vop_reg edp_en;
152 struct vop_reg hdmi_en;
153 struct vop_reg mipi_en;
154 struct vop_reg out_mode;
155 struct vop_reg dither_down;
156 struct vop_reg dither_up;
157 struct vop_reg pin_pol;
158
159 struct vop_reg htotal_pw;
160 struct vop_reg hact_st_end;
161 struct vop_reg vtotal_pw;
162 struct vop_reg vact_st_end;
163 struct vop_reg hpost_st_end;
164 struct vop_reg vpost_st_end;
165 };
166
167 struct vop_win_phy {
168 const uint32_t *data_formats;
169 uint32_t nformats;
170
171 struct vop_reg enable;
172 struct vop_reg format;
173 struct vop_reg rb_swap;
174 struct vop_reg act_info;
175 struct vop_reg dsp_info;
176 struct vop_reg dsp_st;
177 struct vop_reg yrgb_mst;
178 struct vop_reg uv_mst;
179 struct vop_reg yrgb_vir;
180 struct vop_reg uv_vir;
181
182 struct vop_reg dst_alpha_ctl;
183 struct vop_reg src_alpha_ctl;
184 };
185
186 struct vop_win_data {
187 uint32_t base;
188 const struct vop_win_phy *phy;
189 enum drm_plane_type type;
190 };
191
192 struct vop_data {
193 const struct vop_reg_data *init_table;
194 unsigned int table_size;
195 const struct vop_ctrl *ctrl;
196 const struct vop_win_data *win;
197 unsigned int win_size;
198 };
199
200 static const uint32_t formats_01[] = {
201 DRM_FORMAT_XRGB8888,
202 DRM_FORMAT_ARGB8888,
203 DRM_FORMAT_XBGR8888,
204 DRM_FORMAT_ABGR8888,
205 DRM_FORMAT_RGB888,
206 DRM_FORMAT_BGR888,
207 DRM_FORMAT_RGB565,
208 DRM_FORMAT_BGR565,
209 DRM_FORMAT_NV12,
210 DRM_FORMAT_NV16,
211 DRM_FORMAT_NV24,
212 };
213
214 static const uint32_t formats_234[] = {
215 DRM_FORMAT_XRGB8888,
216 DRM_FORMAT_ARGB8888,
217 DRM_FORMAT_XBGR8888,
218 DRM_FORMAT_ABGR8888,
219 DRM_FORMAT_RGB888,
220 DRM_FORMAT_BGR888,
221 DRM_FORMAT_RGB565,
222 DRM_FORMAT_BGR565,
223 };
224
225 static const struct vop_win_phy win01_data = {
226 .data_formats = formats_01,
227 .nformats = ARRAY_SIZE(formats_01),
228 .enable = VOP_REG(WIN0_CTRL0, 0x1, 0),
229 .format = VOP_REG(WIN0_CTRL0, 0x7, 1),
230 .rb_swap = VOP_REG(WIN0_CTRL0, 0x1, 12),
231 .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0),
232 .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0),
233 .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0),
234 .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0),
235 .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0),
236 .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0),
237 .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16),
238 .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0),
239 .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0),
240 };
241
242 static const struct vop_win_phy win23_data = {
243 .data_formats = formats_234,
244 .nformats = ARRAY_SIZE(formats_234),
245 .enable = VOP_REG(WIN2_CTRL0, 0x1, 0),
246 .format = VOP_REG(WIN2_CTRL0, 0x7, 1),
247 .rb_swap = VOP_REG(WIN2_CTRL0, 0x1, 12),
248 .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0),
249 .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0),
250 .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0),
251 .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0),
252 .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0),
253 .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0),
254 };
255
256 static const struct vop_ctrl ctrl_data = {
257 .standby = VOP_REG(SYS_CTRL, 0x1, 22),
258 .gate_en = VOP_REG(SYS_CTRL, 0x1, 23),
259 .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20),
260 .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12),
261 .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13),
262 .edp_en = VOP_REG(SYS_CTRL, 0x1, 14),
263 .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15),
264 .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1),
265 .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6),
266 .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19),
267 .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0),
268 .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4),
269 .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
270 .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0),
271 .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
272 .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0),
273 .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0),
274 .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0),
275 };
276
277 static const struct vop_reg_data vop_init_reg_table[] = {
278 {SYS_CTRL, 0x00c00000},
279 {DSP_CTRL0, 0x00000000},
280 {WIN0_CTRL0, 0x00000080},
281 {WIN1_CTRL0, 0x00000080},
282 };
283
284 /*
285 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
286 * special support to get alpha blending working. For now, just use overlay
287 * window 3 for the drm cursor.
288 *
289 */
290 static const struct vop_win_data rk3288_vop_win_data[] = {
291 { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY },
292 { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_OVERLAY },
293 { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY },
294 { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_CURSOR },
295 };
296
297 static const struct vop_data rk3288_vop = {
298 .init_table = vop_init_reg_table,
299 .table_size = ARRAY_SIZE(vop_init_reg_table),
300 .ctrl = &ctrl_data,
301 .win = rk3288_vop_win_data,
302 .win_size = ARRAY_SIZE(rk3288_vop_win_data),
303 };
304
305 static const struct of_device_id vop_driver_dt_match[] = {
306 { .compatible = "rockchip,rk3288-vop",
307 .data = &rk3288_vop },
308 {},
309 };
310
311 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
312 {
313 writel(v, vop->regs + offset);
314 vop->regsbak[offset >> 2] = v;
315 }
316
317 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
318 {
319 return readl(vop->regs + offset);
320 }
321
322 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
323 const struct vop_reg *reg)
324 {
325 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
326 }
327
328 static inline void vop_cfg_done(struct vop *vop)
329 {
330 writel(0x01, vop->regs + REG_CFG_DONE);
331 }
332
333 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
334 uint32_t mask, uint32_t v)
335 {
336 if (mask) {
337 uint32_t cached_val = vop->regsbak[offset >> 2];
338
339 cached_val = (cached_val & ~mask) | v;
340 writel(cached_val, vop->regs + offset);
341 vop->regsbak[offset >> 2] = cached_val;
342 }
343 }
344
345 static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset,
346 uint32_t mask, uint32_t v)
347 {
348 if (mask) {
349 uint32_t cached_val = vop->regsbak[offset >> 2];
350
351 cached_val = (cached_val & ~mask) | v;
352 writel_relaxed(cached_val, vop->regs + offset);
353 vop->regsbak[offset >> 2] = cached_val;
354 }
355 }
356
357 static bool has_rb_swapped(uint32_t format)
358 {
359 switch (format) {
360 case DRM_FORMAT_XBGR8888:
361 case DRM_FORMAT_ABGR8888:
362 case DRM_FORMAT_BGR888:
363 case DRM_FORMAT_BGR565:
364 return true;
365 default:
366 return false;
367 }
368 }
369
370 static enum vop_data_format vop_convert_format(uint32_t format)
371 {
372 switch (format) {
373 case DRM_FORMAT_XRGB8888:
374 case DRM_FORMAT_ARGB8888:
375 case DRM_FORMAT_XBGR8888:
376 case DRM_FORMAT_ABGR8888:
377 return VOP_FMT_ARGB8888;
378 case DRM_FORMAT_RGB888:
379 case DRM_FORMAT_BGR888:
380 return VOP_FMT_RGB888;
381 case DRM_FORMAT_RGB565:
382 case DRM_FORMAT_BGR565:
383 return VOP_FMT_RGB565;
384 case DRM_FORMAT_NV12:
385 return VOP_FMT_YUV420SP;
386 case DRM_FORMAT_NV16:
387 return VOP_FMT_YUV422SP;
388 case DRM_FORMAT_NV24:
389 return VOP_FMT_YUV444SP;
390 default:
391 DRM_ERROR("unsupport format[%08x]\n", format);
392 return -EINVAL;
393 }
394 }
395
396 static bool is_yuv_support(uint32_t format)
397 {
398 switch (format) {
399 case DRM_FORMAT_NV12:
400 case DRM_FORMAT_NV16:
401 case DRM_FORMAT_NV24:
402 return true;
403 default:
404 return false;
405 }
406 }
407
408 static bool is_alpha_support(uint32_t format)
409 {
410 switch (format) {
411 case DRM_FORMAT_ARGB8888:
412 case DRM_FORMAT_ABGR8888:
413 return true;
414 default:
415 return false;
416 }
417 }
418
419 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
420 {
421 unsigned long flags;
422
423 if (WARN_ON(!vop->is_enabled))
424 return;
425
426 spin_lock_irqsave(&vop->irq_lock, flags);
427
428 vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
429 DSP_HOLD_VALID_INTR_EN(1));
430
431 spin_unlock_irqrestore(&vop->irq_lock, flags);
432 }
433
434 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
435 {
436 unsigned long flags;
437
438 if (WARN_ON(!vop->is_enabled))
439 return;
440
441 spin_lock_irqsave(&vop->irq_lock, flags);
442
443 vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
444 DSP_HOLD_VALID_INTR_EN(0));
445
446 spin_unlock_irqrestore(&vop->irq_lock, flags);
447 }
448
449 static void vop_enable(struct drm_crtc *crtc)
450 {
451 struct vop *vop = to_vop(crtc);
452 int ret;
453
454 if (vop->is_enabled)
455 return;
456
457 ret = pm_runtime_get_sync(vop->dev);
458 if (ret < 0) {
459 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
460 return;
461 }
462
463 ret = clk_enable(vop->hclk);
464 if (ret < 0) {
465 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
466 return;
467 }
468
469 ret = clk_enable(vop->dclk);
470 if (ret < 0) {
471 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
472 goto err_disable_hclk;
473 }
474
475 ret = clk_enable(vop->aclk);
476 if (ret < 0) {
477 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
478 goto err_disable_dclk;
479 }
480
481 /*
482 * Slave iommu shares power, irq and clock with vop. It was associated
483 * automatically with this master device via common driver code.
484 * Now that we have enabled the clock we attach it to the shared drm
485 * mapping.
486 */
487 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
488 if (ret) {
489 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
490 goto err_disable_aclk;
491 }
492
493 /*
494 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
495 */
496 vop->is_enabled = true;
497
498 spin_lock(&vop->reg_lock);
499
500 VOP_CTRL_SET(vop, standby, 0);
501
502 spin_unlock(&vop->reg_lock);
503
504 enable_irq(vop->irq);
505
506 drm_vblank_on(vop->drm_dev, vop->pipe);
507
508 return;
509
510 err_disable_aclk:
511 clk_disable(vop->aclk);
512 err_disable_dclk:
513 clk_disable(vop->dclk);
514 err_disable_hclk:
515 clk_disable(vop->hclk);
516 }
517
518 static void vop_disable(struct drm_crtc *crtc)
519 {
520 struct vop *vop = to_vop(crtc);
521
522 if (!vop->is_enabled)
523 return;
524
525 drm_vblank_off(crtc->dev, vop->pipe);
526
527 /*
528 * Vop standby will take effect at end of current frame,
529 * if dsp hold valid irq happen, it means standby complete.
530 *
531 * we must wait standby complete when we want to disable aclk,
532 * if not, memory bus maybe dead.
533 */
534 reinit_completion(&vop->dsp_hold_completion);
535 vop_dsp_hold_valid_irq_enable(vop);
536
537 spin_lock(&vop->reg_lock);
538
539 VOP_CTRL_SET(vop, standby, 1);
540
541 spin_unlock(&vop->reg_lock);
542
543 wait_for_completion(&vop->dsp_hold_completion);
544
545 vop_dsp_hold_valid_irq_disable(vop);
546
547 disable_irq(vop->irq);
548
549 vop->is_enabled = false;
550
551 /*
552 * vop standby complete, so iommu detach is safe.
553 */
554 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
555
556 clk_disable(vop->dclk);
557 clk_disable(vop->aclk);
558 clk_disable(vop->hclk);
559 pm_runtime_put(vop->dev);
560 }
561
562 /*
563 * Caller must hold vsync_mutex.
564 */
565 static struct drm_framebuffer *vop_win_last_pending_fb(struct vop_win *vop_win)
566 {
567 struct vop_win_state *last;
568 struct vop_win_state *active = vop_win->active;
569
570 if (list_empty(&vop_win->pending))
571 return active ? active->fb : NULL;
572
573 last = list_last_entry(&vop_win->pending, struct vop_win_state, head);
574 return last ? last->fb : NULL;
575 }
576
577 /*
578 * Caller must hold vsync_mutex.
579 */
580 static int vop_win_queue_fb(struct vop_win *vop_win,
581 struct drm_framebuffer *fb, dma_addr_t yrgb_mst,
582 struct drm_pending_vblank_event *event)
583 {
584 struct vop_win_state *state;
585
586 state = kzalloc(sizeof(*state), GFP_KERNEL);
587 if (!state)
588 return -ENOMEM;
589
590 state->fb = fb;
591 state->yrgb_mst = yrgb_mst;
592 state->event = event;
593
594 list_add_tail(&state->head, &vop_win->pending);
595
596 return 0;
597 }
598
599 static int vop_update_plane_event(struct drm_plane *plane,
600 struct drm_crtc *crtc,
601 struct drm_framebuffer *fb, int crtc_x,
602 int crtc_y, unsigned int crtc_w,
603 unsigned int crtc_h, uint32_t src_x,
604 uint32_t src_y, uint32_t src_w,
605 uint32_t src_h,
606 struct drm_pending_vblank_event *event)
607 {
608 struct vop_win *vop_win = to_vop_win(plane);
609 const struct vop_win_data *win = vop_win->data;
610 struct vop *vop = to_vop(crtc);
611 struct drm_gem_object *obj;
612 struct rockchip_gem_object *rk_obj;
613 struct drm_gem_object *uv_obj;
614 struct rockchip_gem_object *rk_uv_obj;
615 unsigned long offset;
616 unsigned int actual_w;
617 unsigned int actual_h;
618 unsigned int dsp_stx;
619 unsigned int dsp_sty;
620 unsigned int y_vir_stride;
621 unsigned int uv_vir_stride = 0;
622 dma_addr_t yrgb_mst;
623 dma_addr_t uv_mst = 0;
624 enum vop_data_format format;
625 uint32_t val;
626 bool is_alpha;
627 bool rb_swap;
628 bool is_yuv;
629 bool visible;
630 int ret;
631 struct drm_rect dest = {
632 .x1 = crtc_x,
633 .y1 = crtc_y,
634 .x2 = crtc_x + crtc_w,
635 .y2 = crtc_y + crtc_h,
636 };
637 struct drm_rect src = {
638 /* 16.16 fixed point */
639 .x1 = src_x,
640 .y1 = src_y,
641 .x2 = src_x + src_w,
642 .y2 = src_y + src_h,
643 };
644 const struct drm_rect clip = {
645 .x2 = crtc->mode.hdisplay,
646 .y2 = crtc->mode.vdisplay,
647 };
648 bool can_position = plane->type != DRM_PLANE_TYPE_PRIMARY;
649
650 ret = drm_plane_helper_check_update(plane, crtc, fb,
651 &src, &dest, &clip,
652 DRM_PLANE_HELPER_NO_SCALING,
653 DRM_PLANE_HELPER_NO_SCALING,
654 can_position, false, &visible);
655 if (ret)
656 return ret;
657
658 if (!visible)
659 return 0;
660
661 is_alpha = is_alpha_support(fb->pixel_format);
662 rb_swap = has_rb_swapped(fb->pixel_format);
663 is_yuv = is_yuv_support(fb->pixel_format);
664
665 format = vop_convert_format(fb->pixel_format);
666 if (format < 0)
667 return format;
668
669 obj = rockchip_fb_get_gem_obj(fb, 0);
670 if (!obj) {
671 DRM_ERROR("fail to get rockchip gem object from framebuffer\n");
672 return -EINVAL;
673 }
674
675 rk_obj = to_rockchip_obj(obj);
676
677 if (is_yuv) {
678 /*
679 * Src.x1 can be odd when do clip, but yuv plane start point
680 * need align with 2 pixel.
681 */
682 val = (src.x1 >> 16) % 2;
683 src.x1 += val << 16;
684 src.x2 += val << 16;
685 }
686
687 actual_w = (src.x2 - src.x1) >> 16;
688 actual_h = (src.y2 - src.y1) >> 16;
689
690 dsp_stx = dest.x1 + crtc->mode.htotal - crtc->mode.hsync_start;
691 dsp_sty = dest.y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
692
693 offset = (src.x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
694 offset += (src.y1 >> 16) * fb->pitches[0];
695
696 yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
697 y_vir_stride = fb->pitches[0] >> 2;
698
699 if (is_yuv) {
700 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
701 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
702 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
703
704 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
705 if (!uv_obj) {
706 DRM_ERROR("fail to get uv object from framebuffer\n");
707 return -EINVAL;
708 }
709 rk_uv_obj = to_rockchip_obj(uv_obj);
710 uv_vir_stride = fb->pitches[1] >> 2;
711
712 offset = (src.x1 >> 16) * bpp / hsub;
713 offset += (src.y1 >> 16) * fb->pitches[1] / vsub;
714
715 uv_mst = rk_uv_obj->dma_addr + offset + fb->offsets[1];
716 }
717
718 /*
719 * If this plane update changes the plane's framebuffer, (or more
720 * precisely, if this update has a different framebuffer than the last
721 * update), enqueue it so we can track when it completes.
722 *
723 * Only when we discover that this update has completed, can we
724 * unreference any previous framebuffers.
725 */
726 mutex_lock(&vop->vsync_mutex);
727 if (fb != vop_win_last_pending_fb(vop_win)) {
728 ret = drm_vblank_get(plane->dev, vop->pipe);
729 if (ret) {
730 DRM_ERROR("failed to get vblank, %d\n", ret);
731 mutex_unlock(&vop->vsync_mutex);
732 return ret;
733 }
734
735 drm_framebuffer_reference(fb);
736
737 ret = vop_win_queue_fb(vop_win, fb, yrgb_mst, event);
738 if (ret) {
739 drm_vblank_put(plane->dev, vop->pipe);
740 mutex_unlock(&vop->vsync_mutex);
741 return ret;
742 }
743
744 vop->vsync_work_pending = true;
745 }
746 mutex_unlock(&vop->vsync_mutex);
747
748 spin_lock(&vop->reg_lock);
749
750 VOP_WIN_SET(vop, win, format, format);
751 VOP_WIN_SET(vop, win, yrgb_vir, y_vir_stride);
752 VOP_WIN_SET(vop, win, yrgb_mst, yrgb_mst);
753 if (is_yuv) {
754 VOP_WIN_SET(vop, win, uv_vir, uv_vir_stride);
755 VOP_WIN_SET(vop, win, uv_mst, uv_mst);
756 }
757 val = (actual_h - 1) << 16;
758 val |= (actual_w - 1) & 0xffff;
759 VOP_WIN_SET(vop, win, act_info, val);
760 VOP_WIN_SET(vop, win, dsp_info, val);
761 val = (dsp_sty - 1) << 16;
762 val |= (dsp_stx - 1) & 0xffff;
763 VOP_WIN_SET(vop, win, dsp_st, val);
764 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
765
766 if (is_alpha) {
767 VOP_WIN_SET(vop, win, dst_alpha_ctl,
768 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
769 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
770 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
771 SRC_BLEND_M0(ALPHA_PER_PIX) |
772 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
773 SRC_FACTOR_M0(ALPHA_ONE);
774 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
775 } else {
776 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
777 }
778
779 VOP_WIN_SET(vop, win, enable, 1);
780
781 vop_cfg_done(vop);
782 spin_unlock(&vop->reg_lock);
783
784 return 0;
785 }
786
787 static int vop_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
788 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
789 unsigned int crtc_w, unsigned int crtc_h,
790 uint32_t src_x, uint32_t src_y, uint32_t src_w,
791 uint32_t src_h)
792 {
793 return vop_update_plane_event(plane, crtc, fb, crtc_x, crtc_y, crtc_w,
794 crtc_h, src_x, src_y, src_w, src_h,
795 NULL);
796 }
797
798 static int vop_update_primary_plane(struct drm_crtc *crtc,
799 struct drm_pending_vblank_event *event)
800 {
801 unsigned int crtc_w, crtc_h;
802
803 crtc_w = crtc->primary->fb->width - crtc->x;
804 crtc_h = crtc->primary->fb->height - crtc->y;
805
806 return vop_update_plane_event(crtc->primary, crtc, crtc->primary->fb,
807 0, 0, crtc_w, crtc_h, crtc->x << 16,
808 crtc->y << 16, crtc_w << 16,
809 crtc_h << 16, event);
810 }
811
812 static int vop_disable_plane(struct drm_plane *plane)
813 {
814 struct vop_win *vop_win = to_vop_win(plane);
815 const struct vop_win_data *win = vop_win->data;
816 struct vop *vop;
817 int ret;
818
819 if (!plane->crtc)
820 return 0;
821
822 vop = to_vop(plane->crtc);
823
824 ret = drm_vblank_get(plane->dev, vop->pipe);
825 if (ret) {
826 DRM_ERROR("failed to get vblank, %d\n", ret);
827 return ret;
828 }
829
830 mutex_lock(&vop->vsync_mutex);
831
832 ret = vop_win_queue_fb(vop_win, NULL, 0, NULL);
833 if (ret) {
834 drm_vblank_put(plane->dev, vop->pipe);
835 mutex_unlock(&vop->vsync_mutex);
836 return ret;
837 }
838
839 vop->vsync_work_pending = true;
840 mutex_unlock(&vop->vsync_mutex);
841
842 spin_lock(&vop->reg_lock);
843 VOP_WIN_SET(vop, win, enable, 0);
844 vop_cfg_done(vop);
845 spin_unlock(&vop->reg_lock);
846
847 return 0;
848 }
849
850 static void vop_plane_destroy(struct drm_plane *plane)
851 {
852 vop_disable_plane(plane);
853 drm_plane_cleanup(plane);
854 }
855
856 static const struct drm_plane_funcs vop_plane_funcs = {
857 .update_plane = vop_update_plane,
858 .disable_plane = vop_disable_plane,
859 .destroy = vop_plane_destroy,
860 };
861
862 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
863 int connector_type,
864 int out_mode)
865 {
866 struct vop *vop = to_vop(crtc);
867
868 vop->connector_type = connector_type;
869 vop->connector_out_mode = out_mode;
870
871 return 0;
872 }
873 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
874
875 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
876 {
877 struct vop *vop = to_vop(crtc);
878 unsigned long flags;
879
880 if (!vop->is_enabled)
881 return -EPERM;
882
883 spin_lock_irqsave(&vop->irq_lock, flags);
884
885 vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(1));
886
887 spin_unlock_irqrestore(&vop->irq_lock, flags);
888
889 return 0;
890 }
891
892 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
893 {
894 struct vop *vop = to_vop(crtc);
895 unsigned long flags;
896
897 if (!vop->is_enabled)
898 return;
899
900 spin_lock_irqsave(&vop->irq_lock, flags);
901 vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(0));
902 spin_unlock_irqrestore(&vop->irq_lock, flags);
903 }
904
905 static const struct rockchip_crtc_funcs private_crtc_funcs = {
906 .enable_vblank = vop_crtc_enable_vblank,
907 .disable_vblank = vop_crtc_disable_vblank,
908 };
909
910 static void vop_crtc_dpms(struct drm_crtc *crtc, int mode)
911 {
912 DRM_DEBUG_KMS("crtc[%d] mode[%d]\n", crtc->base.id, mode);
913
914 switch (mode) {
915 case DRM_MODE_DPMS_ON:
916 vop_enable(crtc);
917 break;
918 case DRM_MODE_DPMS_STANDBY:
919 case DRM_MODE_DPMS_SUSPEND:
920 case DRM_MODE_DPMS_OFF:
921 vop_disable(crtc);
922 break;
923 default:
924 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
925 break;
926 }
927 }
928
929 static void vop_crtc_prepare(struct drm_crtc *crtc)
930 {
931 vop_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
932 }
933
934 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
935 const struct drm_display_mode *mode,
936 struct drm_display_mode *adjusted_mode)
937 {
938 if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0)
939 return false;
940
941 return true;
942 }
943
944 static int vop_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
945 struct drm_framebuffer *old_fb)
946 {
947 int ret;
948
949 crtc->x = x;
950 crtc->y = y;
951
952 ret = vop_update_primary_plane(crtc, NULL);
953 if (ret < 0) {
954 DRM_ERROR("fail to update plane\n");
955 return ret;
956 }
957
958 return 0;
959 }
960
961 static int vop_crtc_mode_set(struct drm_crtc *crtc,
962 struct drm_display_mode *mode,
963 struct drm_display_mode *adjusted_mode,
964 int x, int y, struct drm_framebuffer *fb)
965 {
966 struct vop *vop = to_vop(crtc);
967 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
968 u16 hdisplay = adjusted_mode->hdisplay;
969 u16 htotal = adjusted_mode->htotal;
970 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
971 u16 hact_end = hact_st + hdisplay;
972 u16 vdisplay = adjusted_mode->vdisplay;
973 u16 vtotal = adjusted_mode->vtotal;
974 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
975 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
976 u16 vact_end = vact_st + vdisplay;
977 int ret, ret_clk;
978 uint32_t val;
979
980 /*
981 * disable dclk to stop frame scan, so that we can safe config mode and
982 * enable iommu.
983 */
984 clk_disable(vop->dclk);
985
986 switch (vop->connector_type) {
987 case DRM_MODE_CONNECTOR_LVDS:
988 VOP_CTRL_SET(vop, rgb_en, 1);
989 break;
990 case DRM_MODE_CONNECTOR_eDP:
991 VOP_CTRL_SET(vop, edp_en, 1);
992 break;
993 case DRM_MODE_CONNECTOR_HDMIA:
994 VOP_CTRL_SET(vop, hdmi_en, 1);
995 break;
996 default:
997 DRM_ERROR("unsupport connector_type[%d]\n",
998 vop->connector_type);
999 ret = -EINVAL;
1000 goto out;
1001 };
1002 VOP_CTRL_SET(vop, out_mode, vop->connector_out_mode);
1003
1004 val = 0x8;
1005 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1006 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1007 VOP_CTRL_SET(vop, pin_pol, val);
1008
1009 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1010 val = hact_st << 16;
1011 val |= hact_end;
1012 VOP_CTRL_SET(vop, hact_st_end, val);
1013 VOP_CTRL_SET(vop, hpost_st_end, val);
1014
1015 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1016 val = vact_st << 16;
1017 val |= vact_end;
1018 VOP_CTRL_SET(vop, vact_st_end, val);
1019 VOP_CTRL_SET(vop, vpost_st_end, val);
1020
1021 ret = vop_crtc_mode_set_base(crtc, x, y, fb);
1022 if (ret)
1023 goto out;
1024
1025 /*
1026 * reset dclk, take all mode config affect, so the clk would run in
1027 * correct frame.
1028 */
1029 reset_control_assert(vop->dclk_rst);
1030 usleep_range(10, 20);
1031 reset_control_deassert(vop->dclk_rst);
1032
1033 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1034 out:
1035 ret_clk = clk_enable(vop->dclk);
1036 if (ret_clk < 0) {
1037 dev_err(vop->dev, "failed to enable dclk - %d\n", ret_clk);
1038 return ret_clk;
1039 }
1040
1041 return ret;
1042 }
1043
1044 static void vop_crtc_commit(struct drm_crtc *crtc)
1045 {
1046 }
1047
1048 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1049 .dpms = vop_crtc_dpms,
1050 .prepare = vop_crtc_prepare,
1051 .mode_fixup = vop_crtc_mode_fixup,
1052 .mode_set = vop_crtc_mode_set,
1053 .mode_set_base = vop_crtc_mode_set_base,
1054 .commit = vop_crtc_commit,
1055 };
1056
1057 static int vop_crtc_page_flip(struct drm_crtc *crtc,
1058 struct drm_framebuffer *fb,
1059 struct drm_pending_vblank_event *event,
1060 uint32_t page_flip_flags)
1061 {
1062 struct vop *vop = to_vop(crtc);
1063 struct drm_framebuffer *old_fb = crtc->primary->fb;
1064 int ret;
1065
1066 /* when the page flip is requested, crtc should be on */
1067 if (!vop->is_enabled) {
1068 DRM_DEBUG("page flip request rejected because crtc is off.\n");
1069 return 0;
1070 }
1071
1072 crtc->primary->fb = fb;
1073
1074 ret = vop_update_primary_plane(crtc, event);
1075 if (ret)
1076 crtc->primary->fb = old_fb;
1077
1078 return ret;
1079 }
1080
1081 static void vop_win_state_complete(struct vop_win *vop_win,
1082 struct vop_win_state *state)
1083 {
1084 struct vop *vop = vop_win->vop;
1085 struct drm_crtc *crtc = &vop->crtc;
1086 struct drm_device *drm = crtc->dev;
1087 unsigned long flags;
1088
1089 if (state->event) {
1090 spin_lock_irqsave(&drm->event_lock, flags);
1091 drm_send_vblank_event(drm, -1, state->event);
1092 spin_unlock_irqrestore(&drm->event_lock, flags);
1093 }
1094
1095 list_del(&state->head);
1096 drm_vblank_put(crtc->dev, vop->pipe);
1097 }
1098
1099 static void vop_crtc_destroy(struct drm_crtc *crtc)
1100 {
1101 drm_crtc_cleanup(crtc);
1102 }
1103
1104 static const struct drm_crtc_funcs vop_crtc_funcs = {
1105 .set_config = drm_crtc_helper_set_config,
1106 .page_flip = vop_crtc_page_flip,
1107 .destroy = vop_crtc_destroy,
1108 };
1109
1110 static bool vop_win_state_is_active(struct vop_win *vop_win,
1111 struct vop_win_state *state)
1112 {
1113 bool active = false;
1114
1115 if (state->fb) {
1116 dma_addr_t yrgb_mst;
1117
1118 /* check yrgb_mst to tell if pending_fb is now front */
1119 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data);
1120
1121 active = (yrgb_mst == state->yrgb_mst);
1122 } else {
1123 bool enabled;
1124
1125 /* if enable bit is clear, plane is now disabled */
1126 enabled = VOP_WIN_GET(vop_win->vop, vop_win->data, enable);
1127
1128 active = (enabled == 0);
1129 }
1130
1131 return active;
1132 }
1133
1134 static void vop_win_state_destroy(struct vop_win_state *state)
1135 {
1136 struct drm_framebuffer *fb = state->fb;
1137
1138 if (fb)
1139 drm_framebuffer_unreference(fb);
1140
1141 kfree(state);
1142 }
1143
1144 static void vop_win_update_state(struct vop_win *vop_win)
1145 {
1146 struct vop_win_state *state, *n, *new_active = NULL;
1147
1148 /* Check if any pending states are now active */
1149 list_for_each_entry(state, &vop_win->pending, head)
1150 if (vop_win_state_is_active(vop_win, state)) {
1151 new_active = state;
1152 break;
1153 }
1154
1155 if (!new_active)
1156 return;
1157
1158 /*
1159 * Destroy any 'skipped' pending states - states that were queued
1160 * before the newly active state.
1161 */
1162 list_for_each_entry_safe(state, n, &vop_win->pending, head) {
1163 if (state == new_active)
1164 break;
1165 vop_win_state_complete(vop_win, state);
1166 vop_win_state_destroy(state);
1167 }
1168
1169 vop_win_state_complete(vop_win, new_active);
1170
1171 if (vop_win->active)
1172 vop_win_state_destroy(vop_win->active);
1173 vop_win->active = new_active;
1174 }
1175
1176 static bool vop_win_has_pending_state(struct vop_win *vop_win)
1177 {
1178 return !list_empty(&vop_win->pending);
1179 }
1180
1181 static irqreturn_t vop_isr_thread(int irq, void *data)
1182 {
1183 struct vop *vop = data;
1184 const struct vop_data *vop_data = vop->data;
1185 unsigned int i;
1186
1187 mutex_lock(&vop->vsync_mutex);
1188
1189 if (!vop->vsync_work_pending)
1190 goto done;
1191
1192 vop->vsync_work_pending = false;
1193
1194 for (i = 0; i < vop_data->win_size; i++) {
1195 struct vop_win *vop_win = &vop->win[i];
1196
1197 vop_win_update_state(vop_win);
1198 if (vop_win_has_pending_state(vop_win))
1199 vop->vsync_work_pending = true;
1200 }
1201
1202 done:
1203 mutex_unlock(&vop->vsync_mutex);
1204
1205 return IRQ_HANDLED;
1206 }
1207
1208 static irqreturn_t vop_isr(int irq, void *data)
1209 {
1210 struct vop *vop = data;
1211 uint32_t intr0_reg, active_irqs;
1212 unsigned long flags;
1213 int ret = IRQ_NONE;
1214
1215 /*
1216 * INTR_CTRL0 register has interrupt status, enable and clear bits, we
1217 * must hold irq_lock to avoid a race with enable/disable_vblank().
1218 */
1219 spin_lock_irqsave(&vop->irq_lock, flags);
1220 intr0_reg = vop_readl(vop, INTR_CTRL0);
1221 active_irqs = intr0_reg & INTR_MASK;
1222 /* Clear all active interrupt sources */
1223 if (active_irqs)
1224 vop_writel(vop, INTR_CTRL0,
1225 intr0_reg | (active_irqs << INTR_CLR_SHIFT));
1226 spin_unlock_irqrestore(&vop->irq_lock, flags);
1227
1228 /* This is expected for vop iommu irqs, since the irq is shared */
1229 if (!active_irqs)
1230 return IRQ_NONE;
1231
1232 if (active_irqs & DSP_HOLD_VALID_INTR) {
1233 complete(&vop->dsp_hold_completion);
1234 active_irqs &= ~DSP_HOLD_VALID_INTR;
1235 ret = IRQ_HANDLED;
1236 }
1237
1238 if (active_irqs & FS_INTR) {
1239 drm_handle_vblank(vop->drm_dev, vop->pipe);
1240 active_irqs &= ~FS_INTR;
1241 ret = (vop->vsync_work_pending) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
1242 }
1243
1244 /* Unhandled irqs are spurious. */
1245 if (active_irqs)
1246 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1247
1248 return ret;
1249 }
1250
1251 static int vop_create_crtc(struct vop *vop)
1252 {
1253 const struct vop_data *vop_data = vop->data;
1254 struct device *dev = vop->dev;
1255 struct drm_device *drm_dev = vop->drm_dev;
1256 struct drm_plane *primary = NULL, *cursor = NULL, *plane;
1257 struct drm_crtc *crtc = &vop->crtc;
1258 struct device_node *port;
1259 int ret;
1260 int i;
1261
1262 /*
1263 * Create drm_plane for primary and cursor planes first, since we need
1264 * to pass them to drm_crtc_init_with_planes, which sets the
1265 * "possible_crtcs" to the newly initialized crtc.
1266 */
1267 for (i = 0; i < vop_data->win_size; i++) {
1268 struct vop_win *vop_win = &vop->win[i];
1269 const struct vop_win_data *win_data = vop_win->data;
1270
1271 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1272 win_data->type != DRM_PLANE_TYPE_CURSOR)
1273 continue;
1274
1275 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1276 0, &vop_plane_funcs,
1277 win_data->phy->data_formats,
1278 win_data->phy->nformats,
1279 win_data->type);
1280 if (ret) {
1281 DRM_ERROR("failed to initialize plane\n");
1282 goto err_cleanup_planes;
1283 }
1284
1285 plane = &vop_win->base;
1286 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1287 primary = plane;
1288 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1289 cursor = plane;
1290 }
1291
1292 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1293 &vop_crtc_funcs);
1294 if (ret)
1295 return ret;
1296
1297 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1298
1299 /*
1300 * Create drm_planes for overlay windows with possible_crtcs restricted
1301 * to the newly created crtc.
1302 */
1303 for (i = 0; i < vop_data->win_size; i++) {
1304 struct vop_win *vop_win = &vop->win[i];
1305 const struct vop_win_data *win_data = vop_win->data;
1306 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1307
1308 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1309 continue;
1310
1311 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1312 possible_crtcs,
1313 &vop_plane_funcs,
1314 win_data->phy->data_formats,
1315 win_data->phy->nformats,
1316 win_data->type);
1317 if (ret) {
1318 DRM_ERROR("failed to initialize overlay plane\n");
1319 goto err_cleanup_crtc;
1320 }
1321 }
1322
1323 port = of_get_child_by_name(dev->of_node, "port");
1324 if (!port) {
1325 DRM_ERROR("no port node found in %s\n",
1326 dev->of_node->full_name);
1327 goto err_cleanup_crtc;
1328 }
1329
1330 init_completion(&vop->dsp_hold_completion);
1331 crtc->port = port;
1332 vop->pipe = drm_crtc_index(crtc);
1333 rockchip_register_crtc_funcs(drm_dev, &private_crtc_funcs, vop->pipe);
1334
1335 return 0;
1336
1337 err_cleanup_crtc:
1338 drm_crtc_cleanup(crtc);
1339 err_cleanup_planes:
1340 list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head)
1341 drm_plane_cleanup(plane);
1342 return ret;
1343 }
1344
1345 static void vop_destroy_crtc(struct vop *vop)
1346 {
1347 struct drm_crtc *crtc = &vop->crtc;
1348
1349 rockchip_unregister_crtc_funcs(vop->drm_dev, vop->pipe);
1350 of_node_put(crtc->port);
1351 drm_crtc_cleanup(crtc);
1352 }
1353
1354 static int vop_initial(struct vop *vop)
1355 {
1356 const struct vop_data *vop_data = vop->data;
1357 const struct vop_reg_data *init_table = vop_data->init_table;
1358 struct reset_control *ahb_rst;
1359 int i, ret;
1360
1361 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1362 if (IS_ERR(vop->hclk)) {
1363 dev_err(vop->dev, "failed to get hclk source\n");
1364 return PTR_ERR(vop->hclk);
1365 }
1366 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1367 if (IS_ERR(vop->aclk)) {
1368 dev_err(vop->dev, "failed to get aclk source\n");
1369 return PTR_ERR(vop->aclk);
1370 }
1371 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1372 if (IS_ERR(vop->dclk)) {
1373 dev_err(vop->dev, "failed to get dclk source\n");
1374 return PTR_ERR(vop->dclk);
1375 }
1376
1377 ret = clk_prepare(vop->hclk);
1378 if (ret < 0) {
1379 dev_err(vop->dev, "failed to prepare hclk\n");
1380 return ret;
1381 }
1382
1383 ret = clk_prepare(vop->dclk);
1384 if (ret < 0) {
1385 dev_err(vop->dev, "failed to prepare dclk\n");
1386 goto err_unprepare_hclk;
1387 }
1388
1389 ret = clk_prepare(vop->aclk);
1390 if (ret < 0) {
1391 dev_err(vop->dev, "failed to prepare aclk\n");
1392 goto err_unprepare_dclk;
1393 }
1394
1395 /*
1396 * enable hclk, so that we can config vop register.
1397 */
1398 ret = clk_enable(vop->hclk);
1399 if (ret < 0) {
1400 dev_err(vop->dev, "failed to prepare aclk\n");
1401 goto err_unprepare_aclk;
1402 }
1403 /*
1404 * do hclk_reset, reset all vop registers.
1405 */
1406 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1407 if (IS_ERR(ahb_rst)) {
1408 dev_err(vop->dev, "failed to get ahb reset\n");
1409 ret = PTR_ERR(ahb_rst);
1410 goto err_disable_hclk;
1411 }
1412 reset_control_assert(ahb_rst);
1413 usleep_range(10, 20);
1414 reset_control_deassert(ahb_rst);
1415
1416 memcpy(vop->regsbak, vop->regs, vop->len);
1417
1418 for (i = 0; i < vop_data->table_size; i++)
1419 vop_writel(vop, init_table[i].offset, init_table[i].value);
1420
1421 for (i = 0; i < vop_data->win_size; i++) {
1422 const struct vop_win_data *win = &vop_data->win[i];
1423
1424 VOP_WIN_SET(vop, win, enable, 0);
1425 }
1426
1427 vop_cfg_done(vop);
1428
1429 /*
1430 * do dclk_reset, let all config take affect.
1431 */
1432 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1433 if (IS_ERR(vop->dclk_rst)) {
1434 dev_err(vop->dev, "failed to get dclk reset\n");
1435 ret = PTR_ERR(vop->dclk_rst);
1436 goto err_unprepare_aclk;
1437 }
1438 reset_control_assert(vop->dclk_rst);
1439 usleep_range(10, 20);
1440 reset_control_deassert(vop->dclk_rst);
1441
1442 clk_disable(vop->hclk);
1443
1444 vop->is_enabled = false;
1445
1446 return 0;
1447
1448 err_disable_hclk:
1449 clk_disable(vop->hclk);
1450 err_unprepare_aclk:
1451 clk_unprepare(vop->aclk);
1452 err_unprepare_dclk:
1453 clk_unprepare(vop->dclk);
1454 err_unprepare_hclk:
1455 clk_unprepare(vop->hclk);
1456 return ret;
1457 }
1458
1459 /*
1460 * Initialize the vop->win array elements.
1461 */
1462 static void vop_win_init(struct vop *vop)
1463 {
1464 const struct vop_data *vop_data = vop->data;
1465 unsigned int i;
1466
1467 for (i = 0; i < vop_data->win_size; i++) {
1468 struct vop_win *vop_win = &vop->win[i];
1469 const struct vop_win_data *win_data = &vop_data->win[i];
1470
1471 vop_win->data = win_data;
1472 vop_win->vop = vop;
1473 INIT_LIST_HEAD(&vop_win->pending);
1474 }
1475 }
1476
1477 static int vop_bind(struct device *dev, struct device *master, void *data)
1478 {
1479 struct platform_device *pdev = to_platform_device(dev);
1480 const struct of_device_id *of_id;
1481 const struct vop_data *vop_data;
1482 struct drm_device *drm_dev = data;
1483 struct vop *vop;
1484 struct resource *res;
1485 size_t alloc_size;
1486 int ret, irq;
1487
1488 of_id = of_match_device(vop_driver_dt_match, dev);
1489 vop_data = of_id->data;
1490 if (!vop_data)
1491 return -ENODEV;
1492
1493 /* Allocate vop struct and its vop_win array */
1494 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1495 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1496 if (!vop)
1497 return -ENOMEM;
1498
1499 vop->dev = dev;
1500 vop->data = vop_data;
1501 vop->drm_dev = drm_dev;
1502 dev_set_drvdata(dev, vop);
1503
1504 vop_win_init(vop);
1505
1506 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1507 vop->len = resource_size(res);
1508 vop->regs = devm_ioremap_resource(dev, res);
1509 if (IS_ERR(vop->regs))
1510 return PTR_ERR(vop->regs);
1511
1512 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1513 if (!vop->regsbak)
1514 return -ENOMEM;
1515
1516 ret = vop_initial(vop);
1517 if (ret < 0) {
1518 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1519 return ret;
1520 }
1521
1522 irq = platform_get_irq(pdev, 0);
1523 if (irq < 0) {
1524 dev_err(dev, "cannot find irq for vop\n");
1525 return irq;
1526 }
1527 vop->irq = (unsigned int)irq;
1528
1529 spin_lock_init(&vop->reg_lock);
1530 spin_lock_init(&vop->irq_lock);
1531
1532 mutex_init(&vop->vsync_mutex);
1533
1534 ret = devm_request_threaded_irq(dev, vop->irq, vop_isr, vop_isr_thread,
1535 IRQF_SHARED, dev_name(dev), vop);
1536 if (ret)
1537 return ret;
1538
1539 /* IRQ is initially disabled; it gets enabled in power_on */
1540 disable_irq(vop->irq);
1541
1542 ret = vop_create_crtc(vop);
1543 if (ret)
1544 return ret;
1545
1546 pm_runtime_enable(&pdev->dev);
1547 return 0;
1548 }
1549
1550 static void vop_unbind(struct device *dev, struct device *master, void *data)
1551 {
1552 struct vop *vop = dev_get_drvdata(dev);
1553
1554 pm_runtime_disable(dev);
1555 vop_destroy_crtc(vop);
1556 }
1557
1558 static const struct component_ops vop_component_ops = {
1559 .bind = vop_bind,
1560 .unbind = vop_unbind,
1561 };
1562
1563 static int vop_probe(struct platform_device *pdev)
1564 {
1565 struct device *dev = &pdev->dev;
1566
1567 if (!dev->of_node) {
1568 dev_err(dev, "can't find vop devices\n");
1569 return -ENODEV;
1570 }
1571
1572 return component_add(dev, &vop_component_ops);
1573 }
1574
1575 static int vop_remove(struct platform_device *pdev)
1576 {
1577 component_del(&pdev->dev, &vop_component_ops);
1578
1579 return 0;
1580 }
1581
1582 struct platform_driver vop_platform_driver = {
1583 .probe = vop_probe,
1584 .remove = vop_remove,
1585 .driver = {
1586 .name = "rockchip-vop",
1587 .owner = THIS_MODULE,
1588 .of_match_table = of_match_ptr(vop_driver_dt_match),
1589 },
1590 };
1591
1592 module_platform_driver(vop_platform_driver);
1593
1594 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
1595 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
1596 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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