projects / deliverable / linux.git / blob
? search:


da72de9eb3d517f1c6d3806621b42a0c081dc63e
[deliverable/linux.git] / drivers / gpu / drm / rockchip / rockchip_drm_vop.c
1 /*
2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <drm/drm.h>
16 #include <drm/drmP.h>
17 #include <drm/drm_crtc.h>
18 #include <drm/drm_crtc_helper.h>
19 #include <drm/drm_plane_helper.h>
20
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/clk.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/component.h>
29
30 #include <linux/reset.h>
31 #include <linux/delay.h>
32
33 #include "rockchip_drm_drv.h"
34 #include "rockchip_drm_gem.h"
35 #include "rockchip_drm_fb.h"
36 #include "rockchip_drm_vop.h"
37
38 #define VOP_REG(off, _mask, s) \
39 {.offset = off, \
40 .mask = _mask, \
41 .shift = s,}
42
43 #define __REG_SET_RELAXED(x, off, mask, shift, v) \
44 vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift)
45 #define __REG_SET_NORMAL(x, off, mask, shift, v) \
46 vop_mask_write(x, off, (mask) << shift, (v) << shift)
47
48 #define REG_SET(x, base, reg, v, mode) \
49 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
50
51 #define VOP_WIN_SET(x, win, name, v) \
52 REG_SET(x, win->base, win->phy->name, v, RELAXED)
53 #define VOP_CTRL_SET(x, name, v) \
54 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
55
56 #define VOP_WIN_GET(x, win, name) \
57 vop_read_reg(x, win->base, &win->phy->name)
58
59 #define VOP_WIN_GET_YRGBADDR(vop, win) \
60 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
61
62 #define to_vop(x) container_of(x, struct vop, crtc)
63 #define to_vop_win(x) container_of(x, struct vop_win, base)
64
65 struct vop_win_state {
66 struct list_head head;
67 struct drm_framebuffer *fb;
68 dma_addr_t yrgb_mst;
69 struct drm_pending_vblank_event *event;
70 };
71
72 struct vop_win {
73 struct drm_plane base;
74 const struct vop_win_data *data;
75 struct vop *vop;
76
77 struct list_head pending;
78 struct vop_win_state *active;
79 };
80
81 struct vop {
82 struct drm_crtc crtc;
83 struct device *dev;
84 struct drm_device *drm_dev;
85 bool is_enabled;
86
87 int connector_type;
88 int connector_out_mode;
89
90 /* mutex vsync_ work */
91 struct mutex vsync_mutex;
92 bool vsync_work_pending;
93 struct completion dsp_hold_completion;
94
95 const struct vop_data *data;
96
97 uint32_t *regsbak;
98 void __iomem *regs;
99
100 /* physical map length of vop register */
101 uint32_t len;
102
103 /* one time only one process allowed to config the register */
104 spinlock_t reg_lock;
105 /* lock vop irq reg */
106 spinlock_t irq_lock;
107
108 unsigned int irq;
109
110 /* vop AHP clk */
111 struct clk *hclk;
112 /* vop dclk */
113 struct clk *dclk;
114 /* vop share memory frequency */
115 struct clk *aclk;
116
117 /* vop dclk reset */
118 struct reset_control *dclk_rst;
119
120 int pipe;
121
122 struct vop_win win[];
123 };
124
125 enum vop_data_format {
126 VOP_FMT_ARGB8888 = 0,
127 VOP_FMT_RGB888,
128 VOP_FMT_RGB565,
129 VOP_FMT_YUV420SP = 4,
130 VOP_FMT_YUV422SP,
131 VOP_FMT_YUV444SP,
132 };
133
134 struct vop_reg_data {
135 uint32_t offset;
136 uint32_t value;
137 };
138
139 struct vop_reg {
140 uint32_t offset;
141 uint32_t shift;
142 uint32_t mask;
143 };
144
145 struct vop_ctrl {
146 struct vop_reg standby;
147 struct vop_reg data_blank;
148 struct vop_reg gate_en;
149 struct vop_reg mmu_en;
150 struct vop_reg rgb_en;
151 struct vop_reg edp_en;
152 struct vop_reg hdmi_en;
153 struct vop_reg mipi_en;
154 struct vop_reg out_mode;
155 struct vop_reg dither_down;
156 struct vop_reg dither_up;
157 struct vop_reg pin_pol;
158
159 struct vop_reg htotal_pw;
160 struct vop_reg hact_st_end;
161 struct vop_reg vtotal_pw;
162 struct vop_reg vact_st_end;
163 struct vop_reg hpost_st_end;
164 struct vop_reg vpost_st_end;
165 };
166
167 struct vop_win_phy {
168 const uint32_t *data_formats;
169 uint32_t nformats;
170
171 struct vop_reg enable;
172 struct vop_reg format;
173 struct vop_reg rb_swap;
174 struct vop_reg act_info;
175 struct vop_reg dsp_info;
176 struct vop_reg dsp_st;
177 struct vop_reg yrgb_mst;
178 struct vop_reg uv_mst;
179 struct vop_reg yrgb_vir;
180 struct vop_reg uv_vir;
181
182 struct vop_reg dst_alpha_ctl;
183 struct vop_reg src_alpha_ctl;
184 };
185
186 struct vop_win_data {
187 uint32_t base;
188 const struct vop_win_phy *phy;
189 enum drm_plane_type type;
190 };
191
192 struct vop_data {
193 const struct vop_reg_data *init_table;
194 unsigned int table_size;
195 const struct vop_ctrl *ctrl;
196 const struct vop_win_data *win;
197 unsigned int win_size;
198 };
199
200 static const uint32_t formats_01[] = {
201 DRM_FORMAT_XRGB8888,
202 DRM_FORMAT_ARGB8888,
203 DRM_FORMAT_XBGR8888,
204 DRM_FORMAT_ABGR8888,
205 DRM_FORMAT_RGB888,
206 DRM_FORMAT_BGR888,
207 DRM_FORMAT_RGB565,
208 DRM_FORMAT_BGR565,
209 DRM_FORMAT_NV12,
210 DRM_FORMAT_NV16,
211 DRM_FORMAT_NV24,
212 };
213
214 static const uint32_t formats_234[] = {
215 DRM_FORMAT_XRGB8888,
216 DRM_FORMAT_ARGB8888,
217 DRM_FORMAT_XBGR8888,
218 DRM_FORMAT_ABGR8888,
219 DRM_FORMAT_RGB888,
220 DRM_FORMAT_BGR888,
221 DRM_FORMAT_RGB565,
222 DRM_FORMAT_BGR565,
223 };
224
225 static const struct vop_win_phy win01_data = {
226 .data_formats = formats_01,
227 .nformats = ARRAY_SIZE(formats_01),
228 .enable = VOP_REG(WIN0_CTRL0, 0x1, 0),
229 .format = VOP_REG(WIN0_CTRL0, 0x7, 1),
230 .rb_swap = VOP_REG(WIN0_CTRL0, 0x1, 12),
231 .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0),
232 .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0),
233 .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0),
234 .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0),
235 .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0),
236 .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0),
237 .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16),
238 .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0),
239 .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0),
240 };
241
242 static const struct vop_win_phy win23_data = {
243 .data_formats = formats_234,
244 .nformats = ARRAY_SIZE(formats_234),
245 .enable = VOP_REG(WIN2_CTRL0, 0x1, 0),
246 .format = VOP_REG(WIN2_CTRL0, 0x7, 1),
247 .rb_swap = VOP_REG(WIN2_CTRL0, 0x1, 12),
248 .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0),
249 .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0),
250 .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0),
251 .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0),
252 .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0),
253 .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0),
254 };
255
256 static const struct vop_ctrl ctrl_data = {
257 .standby = VOP_REG(SYS_CTRL, 0x1, 22),
258 .gate_en = VOP_REG(SYS_CTRL, 0x1, 23),
259 .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20),
260 .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12),
261 .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13),
262 .edp_en = VOP_REG(SYS_CTRL, 0x1, 14),
263 .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15),
264 .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1),
265 .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6),
266 .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19),
267 .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0),
268 .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4),
269 .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
270 .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0),
271 .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
272 .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0),
273 .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0),
274 .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0),
275 };
276
277 static const struct vop_reg_data vop_init_reg_table[] = {
278 {SYS_CTRL, 0x00c00000},
279 {DSP_CTRL0, 0x00000000},
280 {WIN0_CTRL0, 0x00000080},
281 {WIN1_CTRL0, 0x00000080},
282 };
283
284 /*
285 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
286 * special support to get alpha blending working. For now, just use overlay
287 * window 3 for the drm cursor.
288 *
289 */
290 static const struct vop_win_data rk3288_vop_win_data[] = {
291 { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY },
292 { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_OVERLAY },
293 { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY },
294 { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_CURSOR },
295 };
296
297 static const struct vop_data rk3288_vop = {
298 .init_table = vop_init_reg_table,
299 .table_size = ARRAY_SIZE(vop_init_reg_table),
300 .ctrl = &ctrl_data,
301 .win = rk3288_vop_win_data,
302 .win_size = ARRAY_SIZE(rk3288_vop_win_data),
303 };
304
305 static const struct of_device_id vop_driver_dt_match[] = {
306 { .compatible = "rockchip,rk3288-vop",
307 .data = &rk3288_vop },
308 {},
309 };
310
311 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
312 {
313 writel(v, vop->regs + offset);
314 vop->regsbak[offset >> 2] = v;
315 }
316
317 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
318 {
319 return readl(vop->regs + offset);
320 }
321
322 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
323 const struct vop_reg *reg)
324 {
325 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
326 }
327
328 static inline void vop_cfg_done(struct vop *vop)
329 {
330 writel(0x01, vop->regs + REG_CFG_DONE);
331 }
332
333 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
334 uint32_t mask, uint32_t v)
335 {
336 if (mask) {
337 uint32_t cached_val = vop->regsbak[offset >> 2];
338
339 cached_val = (cached_val & ~mask) | v;
340 writel(cached_val, vop->regs + offset);
341 vop->regsbak[offset >> 2] = cached_val;
342 }
343 }
344
345 static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset,
346 uint32_t mask, uint32_t v)
347 {
348 if (mask) {
349 uint32_t cached_val = vop->regsbak[offset >> 2];
350
351 cached_val = (cached_val & ~mask) | v;
352 writel_relaxed(cached_val, vop->regs + offset);
353 vop->regsbak[offset >> 2] = cached_val;
354 }
355 }
356
357 static bool has_rb_swapped(uint32_t format)
358 {
359 switch (format) {
360 case DRM_FORMAT_XBGR8888:
361 case DRM_FORMAT_ABGR8888:
362 case DRM_FORMAT_BGR888:
363 case DRM_FORMAT_BGR565:
364 return true;
365 default:
366 return false;
367 }
368 }
369
370 static enum vop_data_format vop_convert_format(uint32_t format)
371 {
372 switch (format) {
373 case DRM_FORMAT_XRGB8888:
374 case DRM_FORMAT_ARGB8888:
375 case DRM_FORMAT_XBGR8888:
376 case DRM_FORMAT_ABGR8888:
377 return VOP_FMT_ARGB8888;
378 case DRM_FORMAT_RGB888:
379 case DRM_FORMAT_BGR888:
380 return VOP_FMT_RGB888;
381 case DRM_FORMAT_RGB565:
382 case DRM_FORMAT_BGR565:
383 return VOP_FMT_RGB565;
384 case DRM_FORMAT_NV12:
385 return VOP_FMT_YUV420SP;
386 case DRM_FORMAT_NV16:
387 return VOP_FMT_YUV422SP;
388 case DRM_FORMAT_NV24:
389 return VOP_FMT_YUV444SP;
390 default:
391 DRM_ERROR("unsupport format[%08x]\n", format);
392 return -EINVAL;
393 }
394 }
395
396 static bool is_alpha_support(uint32_t format)
397 {
398 switch (format) {
399 case DRM_FORMAT_ARGB8888:
400 case DRM_FORMAT_ABGR8888:
401 return true;
402 default:
403 return false;
404 }
405 }
406
407 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
408 {
409 unsigned long flags;
410
411 if (WARN_ON(!vop->is_enabled))
412 return;
413
414 spin_lock_irqsave(&vop->irq_lock, flags);
415
416 vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
417 DSP_HOLD_VALID_INTR_EN(1));
418
419 spin_unlock_irqrestore(&vop->irq_lock, flags);
420 }
421
422 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
423 {
424 unsigned long flags;
425
426 if (WARN_ON(!vop->is_enabled))
427 return;
428
429 spin_lock_irqsave(&vop->irq_lock, flags);
430
431 vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
432 DSP_HOLD_VALID_INTR_EN(0));
433
434 spin_unlock_irqrestore(&vop->irq_lock, flags);
435 }
436
437 static void vop_enable(struct drm_crtc *crtc)
438 {
439 struct vop *vop = to_vop(crtc);
440 int ret;
441
442 if (vop->is_enabled)
443 return;
444
445 ret = pm_runtime_get_sync(vop->dev);
446 if (ret < 0) {
447 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
448 return;
449 }
450
451 ret = clk_enable(vop->hclk);
452 if (ret < 0) {
453 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
454 return;
455 }
456
457 ret = clk_enable(vop->dclk);
458 if (ret < 0) {
459 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
460 goto err_disable_hclk;
461 }
462
463 ret = clk_enable(vop->aclk);
464 if (ret < 0) {
465 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
466 goto err_disable_dclk;
467 }
468
469 /*
470 * Slave iommu shares power, irq and clock with vop. It was associated
471 * automatically with this master device via common driver code.
472 * Now that we have enabled the clock we attach it to the shared drm
473 * mapping.
474 */
475 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
476 if (ret) {
477 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
478 goto err_disable_aclk;
479 }
480
481 /*
482 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
483 */
484 vop->is_enabled = true;
485
486 spin_lock(&vop->reg_lock);
487
488 VOP_CTRL_SET(vop, standby, 0);
489
490 spin_unlock(&vop->reg_lock);
491
492 enable_irq(vop->irq);
493
494 drm_vblank_on(vop->drm_dev, vop->pipe);
495
496 return;
497
498 err_disable_aclk:
499 clk_disable(vop->aclk);
500 err_disable_dclk:
501 clk_disable(vop->dclk);
502 err_disable_hclk:
503 clk_disable(vop->hclk);
504 }
505
506 static void vop_disable(struct drm_crtc *crtc)
507 {
508 struct vop *vop = to_vop(crtc);
509
510 if (!vop->is_enabled)
511 return;
512
513 drm_vblank_off(crtc->dev, vop->pipe);
514
515 /*
516 * Vop standby will take effect at end of current frame,
517 * if dsp hold valid irq happen, it means standby complete.
518 *
519 * we must wait standby complete when we want to disable aclk,
520 * if not, memory bus maybe dead.
521 */
522 reinit_completion(&vop->dsp_hold_completion);
523 vop_dsp_hold_valid_irq_enable(vop);
524
525 spin_lock(&vop->reg_lock);
526
527 VOP_CTRL_SET(vop, standby, 1);
528
529 spin_unlock(&vop->reg_lock);
530
531 wait_for_completion(&vop->dsp_hold_completion);
532
533 vop_dsp_hold_valid_irq_disable(vop);
534
535 disable_irq(vop->irq);
536
537 vop->is_enabled = false;
538
539 /*
540 * vop standby complete, so iommu detach is safe.
541 */
542 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
543
544 clk_disable(vop->dclk);
545 clk_disable(vop->aclk);
546 clk_disable(vop->hclk);
547 pm_runtime_put(vop->dev);
548 }
549
550 /*
551 * Caller must hold vsync_mutex.
552 */
553 static struct drm_framebuffer *vop_win_last_pending_fb(struct vop_win *vop_win)
554 {
555 struct vop_win_state *last;
556 struct vop_win_state *active = vop_win->active;
557
558 if (list_empty(&vop_win->pending))
559 return active ? active->fb : NULL;
560
561 last = list_last_entry(&vop_win->pending, struct vop_win_state, head);
562 return last ? last->fb : NULL;
563 }
564
565 /*
566 * Caller must hold vsync_mutex.
567 */
568 static int vop_win_queue_fb(struct vop_win *vop_win,
569 struct drm_framebuffer *fb, dma_addr_t yrgb_mst,
570 struct drm_pending_vblank_event *event)
571 {
572 struct vop_win_state *state;
573
574 state = kzalloc(sizeof(*state), GFP_KERNEL);
575 if (!state)
576 return -ENOMEM;
577
578 state->fb = fb;
579 state->yrgb_mst = yrgb_mst;
580 state->event = event;
581
582 list_add_tail(&state->head, &vop_win->pending);
583
584 return 0;
585 }
586
587 static int vop_update_plane_event(struct drm_plane *plane,
588 struct drm_crtc *crtc,
589 struct drm_framebuffer *fb, int crtc_x,
590 int crtc_y, unsigned int crtc_w,
591 unsigned int crtc_h, uint32_t src_x,
592 uint32_t src_y, uint32_t src_w,
593 uint32_t src_h,
594 struct drm_pending_vblank_event *event)
595 {
596 struct vop_win *vop_win = to_vop_win(plane);
597 const struct vop_win_data *win = vop_win->data;
598 struct vop *vop = to_vop(crtc);
599 struct drm_gem_object *obj;
600 struct rockchip_gem_object *rk_obj;
601 unsigned long offset;
602 unsigned int actual_w;
603 unsigned int actual_h;
604 unsigned int dsp_stx;
605 unsigned int dsp_sty;
606 unsigned int y_vir_stride;
607 dma_addr_t yrgb_mst;
608 enum vop_data_format format;
609 uint32_t val;
610 bool is_alpha;
611 bool rb_swap;
612 bool visible;
613 int ret;
614 struct drm_rect dest = {
615 .x1 = crtc_x,
616 .y1 = crtc_y,
617 .x2 = crtc_x + crtc_w,
618 .y2 = crtc_y + crtc_h,
619 };
620 struct drm_rect src = {
621 /* 16.16 fixed point */
622 .x1 = src_x,
623 .y1 = src_y,
624 .x2 = src_x + src_w,
625 .y2 = src_y + src_h,
626 };
627 const struct drm_rect clip = {
628 .x2 = crtc->mode.hdisplay,
629 .y2 = crtc->mode.vdisplay,
630 };
631 bool can_position = plane->type != DRM_PLANE_TYPE_PRIMARY;
632
633 ret = drm_plane_helper_check_update(plane, crtc, fb,
634 &src, &dest, &clip,
635 DRM_PLANE_HELPER_NO_SCALING,
636 DRM_PLANE_HELPER_NO_SCALING,
637 can_position, false, &visible);
638 if (ret)
639 return ret;
640
641 if (!visible)
642 return 0;
643
644 is_alpha = is_alpha_support(fb->pixel_format);
645 rb_swap = has_rb_swapped(fb->pixel_format);
646 format = vop_convert_format(fb->pixel_format);
647 if (format < 0)
648 return format;
649
650 obj = rockchip_fb_get_gem_obj(fb, 0);
651 if (!obj) {
652 DRM_ERROR("fail to get rockchip gem object from framebuffer\n");
653 return -EINVAL;
654 }
655
656 rk_obj = to_rockchip_obj(obj);
657
658 actual_w = (src.x2 - src.x1) >> 16;
659 actual_h = (src.y2 - src.y1) >> 16;
660
661 dsp_stx = dest.x1 + crtc->mode.htotal - crtc->mode.hsync_start;
662 dsp_sty = dest.y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
663
664 offset = (src.x1 >> 16) * (fb->bits_per_pixel >> 3);
665 offset += (src.y1 >> 16) * fb->pitches[0];
666 yrgb_mst = rk_obj->dma_addr + offset;
667
668 y_vir_stride = fb->pitches[0] >> 2;
669
670 /*
671 * If this plane update changes the plane's framebuffer, (or more
672 * precisely, if this update has a different framebuffer than the last
673 * update), enqueue it so we can track when it completes.
674 *
675 * Only when we discover that this update has completed, can we
676 * unreference any previous framebuffers.
677 */
678 mutex_lock(&vop->vsync_mutex);
679 if (fb != vop_win_last_pending_fb(vop_win)) {
680 ret = drm_vblank_get(plane->dev, vop->pipe);
681 if (ret) {
682 DRM_ERROR("failed to get vblank, %d\n", ret);
683 mutex_unlock(&vop->vsync_mutex);
684 return ret;
685 }
686
687 drm_framebuffer_reference(fb);
688
689 ret = vop_win_queue_fb(vop_win, fb, yrgb_mst, event);
690 if (ret) {
691 drm_vblank_put(plane->dev, vop->pipe);
692 mutex_unlock(&vop->vsync_mutex);
693 return ret;
694 }
695
696 vop->vsync_work_pending = true;
697 }
698 mutex_unlock(&vop->vsync_mutex);
699
700 spin_lock(&vop->reg_lock);
701
702 VOP_WIN_SET(vop, win, format, format);
703 VOP_WIN_SET(vop, win, yrgb_vir, y_vir_stride);
704 VOP_WIN_SET(vop, win, yrgb_mst, yrgb_mst);
705 val = (actual_h - 1) << 16;
706 val |= (actual_w - 1) & 0xffff;
707 VOP_WIN_SET(vop, win, act_info, val);
708 VOP_WIN_SET(vop, win, dsp_info, val);
709 val = (dsp_sty - 1) << 16;
710 val |= (dsp_stx - 1) & 0xffff;
711 VOP_WIN_SET(vop, win, dsp_st, val);
712 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
713
714 if (is_alpha) {
715 VOP_WIN_SET(vop, win, dst_alpha_ctl,
716 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
717 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
718 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
719 SRC_BLEND_M0(ALPHA_PER_PIX) |
720 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
721 SRC_FACTOR_M0(ALPHA_ONE);
722 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
723 } else {
724 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
725 }
726
727 VOP_WIN_SET(vop, win, enable, 1);
728
729 vop_cfg_done(vop);
730 spin_unlock(&vop->reg_lock);
731
732 return 0;
733 }
734
735 static int vop_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
736 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
737 unsigned int crtc_w, unsigned int crtc_h,
738 uint32_t src_x, uint32_t src_y, uint32_t src_w,
739 uint32_t src_h)
740 {
741 return vop_update_plane_event(plane, crtc, fb, crtc_x, crtc_y, crtc_w,
742 crtc_h, src_x, src_y, src_w, src_h,
743 NULL);
744 }
745
746 static int vop_update_primary_plane(struct drm_crtc *crtc,
747 struct drm_pending_vblank_event *event)
748 {
749 unsigned int crtc_w, crtc_h;
750
751 crtc_w = crtc->primary->fb->width - crtc->x;
752 crtc_h = crtc->primary->fb->height - crtc->y;
753
754 return vop_update_plane_event(crtc->primary, crtc, crtc->primary->fb,
755 0, 0, crtc_w, crtc_h, crtc->x << 16,
756 crtc->y << 16, crtc_w << 16,
757 crtc_h << 16, event);
758 }
759
760 static int vop_disable_plane(struct drm_plane *plane)
761 {
762 struct vop_win *vop_win = to_vop_win(plane);
763 const struct vop_win_data *win = vop_win->data;
764 struct vop *vop;
765 int ret;
766
767 if (!plane->crtc)
768 return 0;
769
770 vop = to_vop(plane->crtc);
771
772 ret = drm_vblank_get(plane->dev, vop->pipe);
773 if (ret) {
774 DRM_ERROR("failed to get vblank, %d\n", ret);
775 return ret;
776 }
777
778 mutex_lock(&vop->vsync_mutex);
779
780 ret = vop_win_queue_fb(vop_win, NULL, 0, NULL);
781 if (ret) {
782 drm_vblank_put(plane->dev, vop->pipe);
783 mutex_unlock(&vop->vsync_mutex);
784 return ret;
785 }
786
787 vop->vsync_work_pending = true;
788 mutex_unlock(&vop->vsync_mutex);
789
790 spin_lock(&vop->reg_lock);
791 VOP_WIN_SET(vop, win, enable, 0);
792 vop_cfg_done(vop);
793 spin_unlock(&vop->reg_lock);
794
795 return 0;
796 }
797
798 static void vop_plane_destroy(struct drm_plane *plane)
799 {
800 vop_disable_plane(plane);
801 drm_plane_cleanup(plane);
802 }
803
804 static const struct drm_plane_funcs vop_plane_funcs = {
805 .update_plane = vop_update_plane,
806 .disable_plane = vop_disable_plane,
807 .destroy = vop_plane_destroy,
808 };
809
810 int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
811 int connector_type,
812 int out_mode)
813 {
814 struct vop *vop = to_vop(crtc);
815
816 vop->connector_type = connector_type;
817 vop->connector_out_mode = out_mode;
818
819 return 0;
820 }
821 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
822
823 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
824 {
825 struct vop *vop = to_vop(crtc);
826 unsigned long flags;
827
828 if (!vop->is_enabled)
829 return -EPERM;
830
831 spin_lock_irqsave(&vop->irq_lock, flags);
832
833 vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(1));
834
835 spin_unlock_irqrestore(&vop->irq_lock, flags);
836
837 return 0;
838 }
839
840 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
841 {
842 struct vop *vop = to_vop(crtc);
843 unsigned long flags;
844
845 if (!vop->is_enabled)
846 return;
847
848 spin_lock_irqsave(&vop->irq_lock, flags);
849 vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(0));
850 spin_unlock_irqrestore(&vop->irq_lock, flags);
851 }
852
853 static const struct rockchip_crtc_funcs private_crtc_funcs = {
854 .enable_vblank = vop_crtc_enable_vblank,
855 .disable_vblank = vop_crtc_disable_vblank,
856 };
857
858 static void vop_crtc_dpms(struct drm_crtc *crtc, int mode)
859 {
860 DRM_DEBUG_KMS("crtc[%d] mode[%d]\n", crtc->base.id, mode);
861
862 switch (mode) {
863 case DRM_MODE_DPMS_ON:
864 vop_enable(crtc);
865 break;
866 case DRM_MODE_DPMS_STANDBY:
867 case DRM_MODE_DPMS_SUSPEND:
868 case DRM_MODE_DPMS_OFF:
869 vop_disable(crtc);
870 break;
871 default:
872 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
873 break;
874 }
875 }
876
877 static void vop_crtc_prepare(struct drm_crtc *crtc)
878 {
879 vop_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
880 }
881
882 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
883 const struct drm_display_mode *mode,
884 struct drm_display_mode *adjusted_mode)
885 {
886 if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0)
887 return false;
888
889 return true;
890 }
891
892 static int vop_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
893 struct drm_framebuffer *old_fb)
894 {
895 int ret;
896
897 crtc->x = x;
898 crtc->y = y;
899
900 ret = vop_update_primary_plane(crtc, NULL);
901 if (ret < 0) {
902 DRM_ERROR("fail to update plane\n");
903 return ret;
904 }
905
906 return 0;
907 }
908
909 static int vop_crtc_mode_set(struct drm_crtc *crtc,
910 struct drm_display_mode *mode,
911 struct drm_display_mode *adjusted_mode,
912 int x, int y, struct drm_framebuffer *fb)
913 {
914 struct vop *vop = to_vop(crtc);
915 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
916 u16 hdisplay = adjusted_mode->hdisplay;
917 u16 htotal = adjusted_mode->htotal;
918 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
919 u16 hact_end = hact_st + hdisplay;
920 u16 vdisplay = adjusted_mode->vdisplay;
921 u16 vtotal = adjusted_mode->vtotal;
922 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
923 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
924 u16 vact_end = vact_st + vdisplay;
925 int ret, ret_clk;
926 uint32_t val;
927
928 /*
929 * disable dclk to stop frame scan, so that we can safe config mode and
930 * enable iommu.
931 */
932 clk_disable(vop->dclk);
933
934 switch (vop->connector_type) {
935 case DRM_MODE_CONNECTOR_LVDS:
936 VOP_CTRL_SET(vop, rgb_en, 1);
937 break;
938 case DRM_MODE_CONNECTOR_eDP:
939 VOP_CTRL_SET(vop, edp_en, 1);
940 break;
941 case DRM_MODE_CONNECTOR_HDMIA:
942 VOP_CTRL_SET(vop, hdmi_en, 1);
943 break;
944 default:
945 DRM_ERROR("unsupport connector_type[%d]\n",
946 vop->connector_type);
947 ret = -EINVAL;
948 goto out;
949 };
950 VOP_CTRL_SET(vop, out_mode, vop->connector_out_mode);
951
952 val = 0x8;
953 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
954 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
955 VOP_CTRL_SET(vop, pin_pol, val);
956
957 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
958 val = hact_st << 16;
959 val |= hact_end;
960 VOP_CTRL_SET(vop, hact_st_end, val);
961 VOP_CTRL_SET(vop, hpost_st_end, val);
962
963 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
964 val = vact_st << 16;
965 val |= vact_end;
966 VOP_CTRL_SET(vop, vact_st_end, val);
967 VOP_CTRL_SET(vop, vpost_st_end, val);
968
969 ret = vop_crtc_mode_set_base(crtc, x, y, fb);
970 if (ret)
971 goto out;
972
973 /*
974 * reset dclk, take all mode config affect, so the clk would run in
975 * correct frame.
976 */
977 reset_control_assert(vop->dclk_rst);
978 usleep_range(10, 20);
979 reset_control_deassert(vop->dclk_rst);
980
981 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
982 out:
983 ret_clk = clk_enable(vop->dclk);
984 if (ret_clk < 0) {
985 dev_err(vop->dev, "failed to enable dclk - %d\n", ret_clk);
986 return ret_clk;
987 }
988
989 return ret;
990 }
991
992 static void vop_crtc_commit(struct drm_crtc *crtc)
993 {
994 }
995
996 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
997 .dpms = vop_crtc_dpms,
998 .prepare = vop_crtc_prepare,
999 .mode_fixup = vop_crtc_mode_fixup,
1000 .mode_set = vop_crtc_mode_set,
1001 .mode_set_base = vop_crtc_mode_set_base,
1002 .commit = vop_crtc_commit,
1003 };
1004
1005 static int vop_crtc_page_flip(struct drm_crtc *crtc,
1006 struct drm_framebuffer *fb,
1007 struct drm_pending_vblank_event *event,
1008 uint32_t page_flip_flags)
1009 {
1010 struct vop *vop = to_vop(crtc);
1011 struct drm_framebuffer *old_fb = crtc->primary->fb;
1012 int ret;
1013
1014 /* when the page flip is requested, crtc should be on */
1015 if (!vop->is_enabled) {
1016 DRM_DEBUG("page flip request rejected because crtc is off.\n");
1017 return 0;
1018 }
1019
1020 crtc->primary->fb = fb;
1021
1022 ret = vop_update_primary_plane(crtc, event);
1023 if (ret)
1024 crtc->primary->fb = old_fb;
1025
1026 return ret;
1027 }
1028
1029 static void vop_win_state_complete(struct vop_win *vop_win,
1030 struct vop_win_state *state)
1031 {
1032 struct vop *vop = vop_win->vop;
1033 struct drm_crtc *crtc = &vop->crtc;
1034 struct drm_device *drm = crtc->dev;
1035 unsigned long flags;
1036
1037 if (state->event) {
1038 spin_lock_irqsave(&drm->event_lock, flags);
1039 drm_send_vblank_event(drm, -1, state->event);
1040 spin_unlock_irqrestore(&drm->event_lock, flags);
1041 }
1042
1043 list_del(&state->head);
1044 drm_vblank_put(crtc->dev, vop->pipe);
1045 }
1046
1047 static void vop_crtc_destroy(struct drm_crtc *crtc)
1048 {
1049 drm_crtc_cleanup(crtc);
1050 }
1051
1052 static const struct drm_crtc_funcs vop_crtc_funcs = {
1053 .set_config = drm_crtc_helper_set_config,
1054 .page_flip = vop_crtc_page_flip,
1055 .destroy = vop_crtc_destroy,
1056 };
1057
1058 static bool vop_win_state_is_active(struct vop_win *vop_win,
1059 struct vop_win_state *state)
1060 {
1061 bool active = false;
1062
1063 if (state->fb) {
1064 dma_addr_t yrgb_mst;
1065
1066 /* check yrgb_mst to tell if pending_fb is now front */
1067 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data);
1068
1069 active = (yrgb_mst == state->yrgb_mst);
1070 } else {
1071 bool enabled;
1072
1073 /* if enable bit is clear, plane is now disabled */
1074 enabled = VOP_WIN_GET(vop_win->vop, vop_win->data, enable);
1075
1076 active = (enabled == 0);
1077 }
1078
1079 return active;
1080 }
1081
1082 static void vop_win_state_destroy(struct vop_win_state *state)
1083 {
1084 struct drm_framebuffer *fb = state->fb;
1085
1086 if (fb)
1087 drm_framebuffer_unreference(fb);
1088
1089 kfree(state);
1090 }
1091
1092 static void vop_win_update_state(struct vop_win *vop_win)
1093 {
1094 struct vop_win_state *state, *n, *new_active = NULL;
1095
1096 /* Check if any pending states are now active */
1097 list_for_each_entry(state, &vop_win->pending, head)
1098 if (vop_win_state_is_active(vop_win, state)) {
1099 new_active = state;
1100 break;
1101 }
1102
1103 if (!new_active)
1104 return;
1105
1106 /*
1107 * Destroy any 'skipped' pending states - states that were queued
1108 * before the newly active state.
1109 */
1110 list_for_each_entry_safe(state, n, &vop_win->pending, head) {
1111 if (state == new_active)
1112 break;
1113 vop_win_state_complete(vop_win, state);
1114 vop_win_state_destroy(state);
1115 }
1116
1117 vop_win_state_complete(vop_win, new_active);
1118
1119 if (vop_win->active)
1120 vop_win_state_destroy(vop_win->active);
1121 vop_win->active = new_active;
1122 }
1123
1124 static bool vop_win_has_pending_state(struct vop_win *vop_win)
1125 {
1126 return !list_empty(&vop_win->pending);
1127 }
1128
1129 static irqreturn_t vop_isr_thread(int irq, void *data)
1130 {
1131 struct vop *vop = data;
1132 const struct vop_data *vop_data = vop->data;
1133 unsigned int i;
1134
1135 mutex_lock(&vop->vsync_mutex);
1136
1137 if (!vop->vsync_work_pending)
1138 goto done;
1139
1140 vop->vsync_work_pending = false;
1141
1142 for (i = 0; i < vop_data->win_size; i++) {
1143 struct vop_win *vop_win = &vop->win[i];
1144
1145 vop_win_update_state(vop_win);
1146 if (vop_win_has_pending_state(vop_win))
1147 vop->vsync_work_pending = true;
1148 }
1149
1150 done:
1151 mutex_unlock(&vop->vsync_mutex);
1152
1153 return IRQ_HANDLED;
1154 }
1155
1156 static irqreturn_t vop_isr(int irq, void *data)
1157 {
1158 struct vop *vop = data;
1159 uint32_t intr0_reg, active_irqs;
1160 unsigned long flags;
1161 int ret = IRQ_NONE;
1162
1163 /*
1164 * INTR_CTRL0 register has interrupt status, enable and clear bits, we
1165 * must hold irq_lock to avoid a race with enable/disable_vblank().
1166 */
1167 spin_lock_irqsave(&vop->irq_lock, flags);
1168 intr0_reg = vop_readl(vop, INTR_CTRL0);
1169 active_irqs = intr0_reg & INTR_MASK;
1170 /* Clear all active interrupt sources */
1171 if (active_irqs)
1172 vop_writel(vop, INTR_CTRL0,
1173 intr0_reg | (active_irqs << INTR_CLR_SHIFT));
1174 spin_unlock_irqrestore(&vop->irq_lock, flags);
1175
1176 /* This is expected for vop iommu irqs, since the irq is shared */
1177 if (!active_irqs)
1178 return IRQ_NONE;
1179
1180 if (active_irqs & DSP_HOLD_VALID_INTR) {
1181 complete(&vop->dsp_hold_completion);
1182 active_irqs &= ~DSP_HOLD_VALID_INTR;
1183 ret = IRQ_HANDLED;
1184 }
1185
1186 if (active_irqs & FS_INTR) {
1187 drm_handle_vblank(vop->drm_dev, vop->pipe);
1188 active_irqs &= ~FS_INTR;
1189 ret = (vop->vsync_work_pending) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
1190 }
1191
1192 /* Unhandled irqs are spurious. */
1193 if (active_irqs)
1194 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1195
1196 return ret;
1197 }
1198
1199 static int vop_create_crtc(struct vop *vop)
1200 {
1201 const struct vop_data *vop_data = vop->data;
1202 struct device *dev = vop->dev;
1203 struct drm_device *drm_dev = vop->drm_dev;
1204 struct drm_plane *primary = NULL, *cursor = NULL, *plane;
1205 struct drm_crtc *crtc = &vop->crtc;
1206 struct device_node *port;
1207 int ret;
1208 int i;
1209
1210 /*
1211 * Create drm_plane for primary and cursor planes first, since we need
1212 * to pass them to drm_crtc_init_with_planes, which sets the
1213 * "possible_crtcs" to the newly initialized crtc.
1214 */
1215 for (i = 0; i < vop_data->win_size; i++) {
1216 struct vop_win *vop_win = &vop->win[i];
1217 const struct vop_win_data *win_data = vop_win->data;
1218
1219 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1220 win_data->type != DRM_PLANE_TYPE_CURSOR)
1221 continue;
1222
1223 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1224 0, &vop_plane_funcs,
1225 win_data->phy->data_formats,
1226 win_data->phy->nformats,
1227 win_data->type);
1228 if (ret) {
1229 DRM_ERROR("failed to initialize plane\n");
1230 goto err_cleanup_planes;
1231 }
1232
1233 plane = &vop_win->base;
1234 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1235 primary = plane;
1236 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1237 cursor = plane;
1238 }
1239
1240 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1241 &vop_crtc_funcs);
1242 if (ret)
1243 return ret;
1244
1245 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1246
1247 /*
1248 * Create drm_planes for overlay windows with possible_crtcs restricted
1249 * to the newly created crtc.
1250 */
1251 for (i = 0; i < vop_data->win_size; i++) {
1252 struct vop_win *vop_win = &vop->win[i];
1253 const struct vop_win_data *win_data = vop_win->data;
1254 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1255
1256 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1257 continue;
1258
1259 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1260 possible_crtcs,
1261 &vop_plane_funcs,
1262 win_data->phy->data_formats,
1263 win_data->phy->nformats,
1264 win_data->type);
1265 if (ret) {
1266 DRM_ERROR("failed to initialize overlay plane\n");
1267 goto err_cleanup_crtc;
1268 }
1269 }
1270
1271 port = of_get_child_by_name(dev->of_node, "port");
1272 if (!port) {
1273 DRM_ERROR("no port node found in %s\n",
1274 dev->of_node->full_name);
1275 goto err_cleanup_crtc;
1276 }
1277
1278 init_completion(&vop->dsp_hold_completion);
1279 crtc->port = port;
1280 vop->pipe = drm_crtc_index(crtc);
1281 rockchip_register_crtc_funcs(drm_dev, &private_crtc_funcs, vop->pipe);
1282
1283 return 0;
1284
1285 err_cleanup_crtc:
1286 drm_crtc_cleanup(crtc);
1287 err_cleanup_planes:
1288 list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head)
1289 drm_plane_cleanup(plane);
1290 return ret;
1291 }
1292
1293 static void vop_destroy_crtc(struct vop *vop)
1294 {
1295 struct drm_crtc *crtc = &vop->crtc;
1296
1297 rockchip_unregister_crtc_funcs(vop->drm_dev, vop->pipe);
1298 of_node_put(crtc->port);
1299 drm_crtc_cleanup(crtc);
1300 }
1301
1302 static int vop_initial(struct vop *vop)
1303 {
1304 const struct vop_data *vop_data = vop->data;
1305 const struct vop_reg_data *init_table = vop_data->init_table;
1306 struct reset_control *ahb_rst;
1307 int i, ret;
1308
1309 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1310 if (IS_ERR(vop->hclk)) {
1311 dev_err(vop->dev, "failed to get hclk source\n");
1312 return PTR_ERR(vop->hclk);
1313 }
1314 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1315 if (IS_ERR(vop->aclk)) {
1316 dev_err(vop->dev, "failed to get aclk source\n");
1317 return PTR_ERR(vop->aclk);
1318 }
1319 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1320 if (IS_ERR(vop->dclk)) {
1321 dev_err(vop->dev, "failed to get dclk source\n");
1322 return PTR_ERR(vop->dclk);
1323 }
1324
1325 ret = clk_prepare(vop->hclk);
1326 if (ret < 0) {
1327 dev_err(vop->dev, "failed to prepare hclk\n");
1328 return ret;
1329 }
1330
1331 ret = clk_prepare(vop->dclk);
1332 if (ret < 0) {
1333 dev_err(vop->dev, "failed to prepare dclk\n");
1334 goto err_unprepare_hclk;
1335 }
1336
1337 ret = clk_prepare(vop->aclk);
1338 if (ret < 0) {
1339 dev_err(vop->dev, "failed to prepare aclk\n");
1340 goto err_unprepare_dclk;
1341 }
1342
1343 /*
1344 * enable hclk, so that we can config vop register.
1345 */
1346 ret = clk_enable(vop->hclk);
1347 if (ret < 0) {
1348 dev_err(vop->dev, "failed to prepare aclk\n");
1349 goto err_unprepare_aclk;
1350 }
1351 /*
1352 * do hclk_reset, reset all vop registers.
1353 */
1354 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1355 if (IS_ERR(ahb_rst)) {
1356 dev_err(vop->dev, "failed to get ahb reset\n");
1357 ret = PTR_ERR(ahb_rst);
1358 goto err_disable_hclk;
1359 }
1360 reset_control_assert(ahb_rst);
1361 usleep_range(10, 20);
1362 reset_control_deassert(ahb_rst);
1363
1364 memcpy(vop->regsbak, vop->regs, vop->len);
1365
1366 for (i = 0; i < vop_data->table_size; i++)
1367 vop_writel(vop, init_table[i].offset, init_table[i].value);
1368
1369 for (i = 0; i < vop_data->win_size; i++) {
1370 const struct vop_win_data *win = &vop_data->win[i];
1371
1372 VOP_WIN_SET(vop, win, enable, 0);
1373 }
1374
1375 vop_cfg_done(vop);
1376
1377 /*
1378 * do dclk_reset, let all config take affect.
1379 */
1380 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1381 if (IS_ERR(vop->dclk_rst)) {
1382 dev_err(vop->dev, "failed to get dclk reset\n");
1383 ret = PTR_ERR(vop->dclk_rst);
1384 goto err_unprepare_aclk;
1385 }
1386 reset_control_assert(vop->dclk_rst);
1387 usleep_range(10, 20);
1388 reset_control_deassert(vop->dclk_rst);
1389
1390 clk_disable(vop->hclk);
1391
1392 vop->is_enabled = false;
1393
1394 return 0;
1395
1396 err_disable_hclk:
1397 clk_disable(vop->hclk);
1398 err_unprepare_aclk:
1399 clk_unprepare(vop->aclk);
1400 err_unprepare_dclk:
1401 clk_unprepare(vop->dclk);
1402 err_unprepare_hclk:
1403 clk_unprepare(vop->hclk);
1404 return ret;
1405 }
1406
1407 /*
1408 * Initialize the vop->win array elements.
1409 */
1410 static void vop_win_init(struct vop *vop)
1411 {
1412 const struct vop_data *vop_data = vop->data;
1413 unsigned int i;
1414
1415 for (i = 0; i < vop_data->win_size; i++) {
1416 struct vop_win *vop_win = &vop->win[i];
1417 const struct vop_win_data *win_data = &vop_data->win[i];
1418
1419 vop_win->data = win_data;
1420 vop_win->vop = vop;
1421 INIT_LIST_HEAD(&vop_win->pending);
1422 }
1423 }
1424
1425 static int vop_bind(struct device *dev, struct device *master, void *data)
1426 {
1427 struct platform_device *pdev = to_platform_device(dev);
1428 const struct of_device_id *of_id;
1429 const struct vop_data *vop_data;
1430 struct drm_device *drm_dev = data;
1431 struct vop *vop;
1432 struct resource *res;
1433 size_t alloc_size;
1434 int ret, irq;
1435
1436 of_id = of_match_device(vop_driver_dt_match, dev);
1437 vop_data = of_id->data;
1438 if (!vop_data)
1439 return -ENODEV;
1440
1441 /* Allocate vop struct and its vop_win array */
1442 alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
1443 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1444 if (!vop)
1445 return -ENOMEM;
1446
1447 vop->dev = dev;
1448 vop->data = vop_data;
1449 vop->drm_dev = drm_dev;
1450 dev_set_drvdata(dev, vop);
1451
1452 vop_win_init(vop);
1453
1454 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1455 vop->len = resource_size(res);
1456 vop->regs = devm_ioremap_resource(dev, res);
1457 if (IS_ERR(vop->regs))
1458 return PTR_ERR(vop->regs);
1459
1460 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1461 if (!vop->regsbak)
1462 return -ENOMEM;
1463
1464 ret = vop_initial(vop);
1465 if (ret < 0) {
1466 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1467 return ret;
1468 }
1469
1470 irq = platform_get_irq(pdev, 0);
1471 if (irq < 0) {
1472 dev_err(dev, "cannot find irq for vop\n");
1473 return irq;
1474 }
1475 vop->irq = (unsigned int)irq;
1476
1477 spin_lock_init(&vop->reg_lock);
1478 spin_lock_init(&vop->irq_lock);
1479
1480 mutex_init(&vop->vsync_mutex);
1481
1482 ret = devm_request_threaded_irq(dev, vop->irq, vop_isr, vop_isr_thread,
1483 IRQF_SHARED, dev_name(dev), vop);
1484 if (ret)
1485 return ret;
1486
1487 /* IRQ is initially disabled; it gets enabled in power_on */
1488 disable_irq(vop->irq);
1489
1490 ret = vop_create_crtc(vop);
1491 if (ret)
1492 return ret;
1493
1494 pm_runtime_enable(&pdev->dev);
1495 return 0;
1496 }
1497
1498 static void vop_unbind(struct device *dev, struct device *master, void *data)
1499 {
1500 struct vop *vop = dev_get_drvdata(dev);
1501
1502 pm_runtime_disable(dev);
1503 vop_destroy_crtc(vop);
1504 }
1505
1506 static const struct component_ops vop_component_ops = {
1507 .bind = vop_bind,
1508 .unbind = vop_unbind,
1509 };
1510
1511 static int vop_probe(struct platform_device *pdev)
1512 {
1513 struct device *dev = &pdev->dev;
1514
1515 if (!dev->of_node) {
1516 dev_err(dev, "can't find vop devices\n");
1517 return -ENODEV;
1518 }
1519
1520 return component_add(dev, &vop_component_ops);
1521 }
1522
1523 static int vop_remove(struct platform_device *pdev)
1524 {
1525 component_del(&pdev->dev, &vop_component_ops);
1526
1527 return 0;
1528 }
1529
1530 struct platform_driver vop_platform_driver = {
1531 .probe = vop_probe,
1532 .remove = vop_remove,
1533 .driver = {
1534 .name = "rockchip-vop",
1535 .owner = THIS_MODULE,
1536 .of_match_table = of_match_ptr(vop_driver_dt_match),
1537 },
1538 };
1539
1540 module_platform_driver(vop_platform_driver);
1541
1542 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
1543 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
1544 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
This page took 0.06004 seconds and 4 git commands to generate.