2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_plane_helper.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
27 #include <linux/of_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/component.h>
31 #include <linux/reset.h>
32 #include <linux/delay.h>
34 #include "rockchip_drm_drv.h"
35 #include "rockchip_drm_gem.h"
36 #include "rockchip_drm_fb.h"
37 #include "rockchip_drm_vop.h"
39 #define __REG_SET_RELAXED(x, off, mask, shift, v) \
40 vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift)
41 #define __REG_SET_NORMAL(x, off, mask, shift, v) \
42 vop_mask_write(x, off, (mask) << shift, (v) << shift)
44 #define REG_SET(x, base, reg, v, mode) \
45 __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
46 #define REG_SET_MASK(x, base, reg, mask, v, mode) \
47 __REG_SET_##mode(x, base + reg.offset, mask, reg.shift, v)
49 #define VOP_WIN_SET(x, win, name, v) \
50 REG_SET(x, win->base, win->phy->name, v, RELAXED)
51 #define VOP_SCL_SET(x, win, name, v) \
52 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
53 #define VOP_SCL_SET_EXT(x, win, name, v) \
54 REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED)
55 #define VOP_CTRL_SET(x, name, v) \
56 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
58 #define VOP_INTR_GET(vop, name) \
59 vop_read_reg(vop, 0, &vop->data->ctrl->name)
61 #define VOP_INTR_SET(vop, name, mask, v) \
62 REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL)
63 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
65 int i, reg = 0, mask = 0; \
66 for (i = 0; i < vop->data->intr->nintrs; i++) { \
67 if (vop->data->intr->intrs[i] & type) { \
72 VOP_INTR_SET(vop, name, mask, reg); \
74 #define VOP_INTR_GET_TYPE(vop, name, type) \
75 vop_get_intr_type(vop, &vop->data->intr->name, type)
77 #define VOP_WIN_GET(x, win, name) \
78 vop_read_reg(x, win->base, &win->phy->name)
80 #define VOP_WIN_GET_YRGBADDR(vop, win) \
81 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
83 #define to_vop(x) container_of(x, struct vop, crtc)
84 #define to_vop_win(x) container_of(x, struct vop_win, base)
85 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
87 struct vop_plane_state
{
88 struct drm_plane_state base
;
97 struct drm_plane base
;
98 const struct vop_win_data
*data
;
101 struct vop_plane_state state
;
105 struct drm_crtc crtc
;
107 struct drm_device
*drm_dev
;
110 /* mutex vsync_ work */
111 struct mutex vsync_mutex
;
112 bool vsync_work_pending
;
113 struct completion dsp_hold_completion
;
114 struct completion wait_update_complete
;
115 struct drm_pending_vblank_event
*event
;
117 const struct vop_data
*data
;
122 /* physical map length of vop register */
125 /* one time only one process allowed to config the register */
127 /* lock vop irq reg */
136 /* vop share memory frequency */
140 struct reset_control
*dclk_rst
;
142 struct vop_win win
[];
145 static inline void vop_writel(struct vop
*vop
, uint32_t offset
, uint32_t v
)
147 writel(v
, vop
->regs
+ offset
);
148 vop
->regsbak
[offset
>> 2] = v
;
151 static inline uint32_t vop_readl(struct vop
*vop
, uint32_t offset
)
153 return readl(vop
->regs
+ offset
);
156 static inline uint32_t vop_read_reg(struct vop
*vop
, uint32_t base
,
157 const struct vop_reg
*reg
)
159 return (vop_readl(vop
, base
+ reg
->offset
) >> reg
->shift
) & reg
->mask
;
162 static inline void vop_mask_write(struct vop
*vop
, uint32_t offset
,
163 uint32_t mask
, uint32_t v
)
166 uint32_t cached_val
= vop
->regsbak
[offset
>> 2];
168 cached_val
= (cached_val
& ~mask
) | v
;
169 writel(cached_val
, vop
->regs
+ offset
);
170 vop
->regsbak
[offset
>> 2] = cached_val
;
174 static inline void vop_mask_write_relaxed(struct vop
*vop
, uint32_t offset
,
175 uint32_t mask
, uint32_t v
)
178 uint32_t cached_val
= vop
->regsbak
[offset
>> 2];
180 cached_val
= (cached_val
& ~mask
) | v
;
181 writel_relaxed(cached_val
, vop
->regs
+ offset
);
182 vop
->regsbak
[offset
>> 2] = cached_val
;
186 static inline uint32_t vop_get_intr_type(struct vop
*vop
,
187 const struct vop_reg
*reg
, int type
)
190 uint32_t regs
= vop_read_reg(vop
, 0, reg
);
192 for (i
= 0; i
< vop
->data
->intr
->nintrs
; i
++) {
193 if ((type
& vop
->data
->intr
->intrs
[i
]) && (regs
& 1 << i
))
194 ret
|= vop
->data
->intr
->intrs
[i
];
200 static inline void vop_cfg_done(struct vop
*vop
)
202 VOP_CTRL_SET(vop
, cfg_done
, 1);
205 static bool has_rb_swapped(uint32_t format
)
208 case DRM_FORMAT_XBGR8888
:
209 case DRM_FORMAT_ABGR8888
:
210 case DRM_FORMAT_BGR888
:
211 case DRM_FORMAT_BGR565
:
218 static enum vop_data_format
vop_convert_format(uint32_t format
)
221 case DRM_FORMAT_XRGB8888
:
222 case DRM_FORMAT_ARGB8888
:
223 case DRM_FORMAT_XBGR8888
:
224 case DRM_FORMAT_ABGR8888
:
225 return VOP_FMT_ARGB8888
;
226 case DRM_FORMAT_RGB888
:
227 case DRM_FORMAT_BGR888
:
228 return VOP_FMT_RGB888
;
229 case DRM_FORMAT_RGB565
:
230 case DRM_FORMAT_BGR565
:
231 return VOP_FMT_RGB565
;
232 case DRM_FORMAT_NV12
:
233 return VOP_FMT_YUV420SP
;
234 case DRM_FORMAT_NV16
:
235 return VOP_FMT_YUV422SP
;
236 case DRM_FORMAT_NV24
:
237 return VOP_FMT_YUV444SP
;
239 DRM_ERROR("unsupport format[%08x]\n", format
);
244 static bool is_yuv_support(uint32_t format
)
247 case DRM_FORMAT_NV12
:
248 case DRM_FORMAT_NV16
:
249 case DRM_FORMAT_NV24
:
256 static bool is_alpha_support(uint32_t format
)
259 case DRM_FORMAT_ARGB8888
:
260 case DRM_FORMAT_ABGR8888
:
267 static uint16_t scl_vop_cal_scale(enum scale_mode mode
, uint32_t src
,
268 uint32_t dst
, bool is_horizontal
,
269 int vsu_mode
, int *vskiplines
)
271 uint16_t val
= 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT
;
274 if (mode
== SCALE_UP
)
275 val
= GET_SCL_FT_BIC(src
, dst
);
276 else if (mode
== SCALE_DOWN
)
277 val
= GET_SCL_FT_BILI_DN(src
, dst
);
279 if (mode
== SCALE_UP
) {
280 if (vsu_mode
== SCALE_UP_BIL
)
281 val
= GET_SCL_FT_BILI_UP(src
, dst
);
283 val
= GET_SCL_FT_BIC(src
, dst
);
284 } else if (mode
== SCALE_DOWN
) {
286 *vskiplines
= scl_get_vskiplines(src
, dst
);
287 val
= scl_get_bili_dn_vskip(src
, dst
,
290 val
= GET_SCL_FT_BILI_DN(src
, dst
);
298 static void scl_vop_cal_scl_fac(struct vop
*vop
, const struct vop_win_data
*win
,
299 uint32_t src_w
, uint32_t src_h
, uint32_t dst_w
,
300 uint32_t dst_h
, uint32_t pixel_format
)
302 uint16_t yrgb_hor_scl_mode
, yrgb_ver_scl_mode
;
303 uint16_t cbcr_hor_scl_mode
= SCALE_NONE
;
304 uint16_t cbcr_ver_scl_mode
= SCALE_NONE
;
305 int hsub
= drm_format_horz_chroma_subsampling(pixel_format
);
306 int vsub
= drm_format_vert_chroma_subsampling(pixel_format
);
307 bool is_yuv
= is_yuv_support(pixel_format
);
308 uint16_t cbcr_src_w
= src_w
/ hsub
;
309 uint16_t cbcr_src_h
= src_h
/ vsub
;
316 DRM_ERROR("Maximum destination width (3840) exceeded\n");
320 if (!win
->phy
->scl
->ext
) {
321 VOP_SCL_SET(vop
, win
, scale_yrgb_x
,
322 scl_cal_scale2(src_w
, dst_w
));
323 VOP_SCL_SET(vop
, win
, scale_yrgb_y
,
324 scl_cal_scale2(src_h
, dst_h
));
326 VOP_SCL_SET(vop
, win
, scale_cbcr_x
,
327 scl_cal_scale2(src_w
, dst_w
));
328 VOP_SCL_SET(vop
, win
, scale_cbcr_y
,
329 scl_cal_scale2(src_h
, dst_h
));
334 yrgb_hor_scl_mode
= scl_get_scl_mode(src_w
, dst_w
);
335 yrgb_ver_scl_mode
= scl_get_scl_mode(src_h
, dst_h
);
338 cbcr_hor_scl_mode
= scl_get_scl_mode(cbcr_src_w
, dst_w
);
339 cbcr_ver_scl_mode
= scl_get_scl_mode(cbcr_src_h
, dst_h
);
340 if (cbcr_hor_scl_mode
== SCALE_DOWN
)
341 lb_mode
= scl_vop_cal_lb_mode(dst_w
, true);
343 lb_mode
= scl_vop_cal_lb_mode(cbcr_src_w
, true);
345 if (yrgb_hor_scl_mode
== SCALE_DOWN
)
346 lb_mode
= scl_vop_cal_lb_mode(dst_w
, false);
348 lb_mode
= scl_vop_cal_lb_mode(src_w
, false);
351 VOP_SCL_SET_EXT(vop
, win
, lb_mode
, lb_mode
);
352 if (lb_mode
== LB_RGB_3840X2
) {
353 if (yrgb_ver_scl_mode
!= SCALE_NONE
) {
354 DRM_ERROR("ERROR : not allow yrgb ver scale\n");
357 if (cbcr_ver_scl_mode
!= SCALE_NONE
) {
358 DRM_ERROR("ERROR : not allow cbcr ver scale\n");
361 vsu_mode
= SCALE_UP_BIL
;
362 } else if (lb_mode
== LB_RGB_2560X4
) {
363 vsu_mode
= SCALE_UP_BIL
;
365 vsu_mode
= SCALE_UP_BIC
;
368 val
= scl_vop_cal_scale(yrgb_hor_scl_mode
, src_w
, dst_w
,
370 VOP_SCL_SET(vop
, win
, scale_yrgb_x
, val
);
371 val
= scl_vop_cal_scale(yrgb_ver_scl_mode
, src_h
, dst_h
,
372 false, vsu_mode
, &vskiplines
);
373 VOP_SCL_SET(vop
, win
, scale_yrgb_y
, val
);
375 VOP_SCL_SET_EXT(vop
, win
, vsd_yrgb_gt4
, vskiplines
== 4);
376 VOP_SCL_SET_EXT(vop
, win
, vsd_yrgb_gt2
, vskiplines
== 2);
378 VOP_SCL_SET_EXT(vop
, win
, yrgb_hor_scl_mode
, yrgb_hor_scl_mode
);
379 VOP_SCL_SET_EXT(vop
, win
, yrgb_ver_scl_mode
, yrgb_ver_scl_mode
);
380 VOP_SCL_SET_EXT(vop
, win
, yrgb_hsd_mode
, SCALE_DOWN_BIL
);
381 VOP_SCL_SET_EXT(vop
, win
, yrgb_vsd_mode
, SCALE_DOWN_BIL
);
382 VOP_SCL_SET_EXT(vop
, win
, yrgb_vsu_mode
, vsu_mode
);
384 val
= scl_vop_cal_scale(cbcr_hor_scl_mode
, cbcr_src_w
,
385 dst_w
, true, 0, NULL
);
386 VOP_SCL_SET(vop
, win
, scale_cbcr_x
, val
);
387 val
= scl_vop_cal_scale(cbcr_ver_scl_mode
, cbcr_src_h
,
388 dst_h
, false, vsu_mode
, &vskiplines
);
389 VOP_SCL_SET(vop
, win
, scale_cbcr_y
, val
);
391 VOP_SCL_SET_EXT(vop
, win
, vsd_cbcr_gt4
, vskiplines
== 4);
392 VOP_SCL_SET_EXT(vop
, win
, vsd_cbcr_gt2
, vskiplines
== 2);
393 VOP_SCL_SET_EXT(vop
, win
, cbcr_hor_scl_mode
, cbcr_hor_scl_mode
);
394 VOP_SCL_SET_EXT(vop
, win
, cbcr_ver_scl_mode
, cbcr_ver_scl_mode
);
395 VOP_SCL_SET_EXT(vop
, win
, cbcr_hsd_mode
, SCALE_DOWN_BIL
);
396 VOP_SCL_SET_EXT(vop
, win
, cbcr_vsd_mode
, SCALE_DOWN_BIL
);
397 VOP_SCL_SET_EXT(vop
, win
, cbcr_vsu_mode
, vsu_mode
);
401 static void vop_dsp_hold_valid_irq_enable(struct vop
*vop
)
405 if (WARN_ON(!vop
->is_enabled
))
408 spin_lock_irqsave(&vop
->irq_lock
, flags
);
410 VOP_INTR_SET_TYPE(vop
, enable
, DSP_HOLD_VALID_INTR
, 1);
412 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
415 static void vop_dsp_hold_valid_irq_disable(struct vop
*vop
)
419 if (WARN_ON(!vop
->is_enabled
))
422 spin_lock_irqsave(&vop
->irq_lock
, flags
);
424 VOP_INTR_SET_TYPE(vop
, enable
, DSP_HOLD_VALID_INTR
, 0);
426 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
429 static void vop_enable(struct drm_crtc
*crtc
)
431 struct vop
*vop
= to_vop(crtc
);
437 ret
= pm_runtime_get_sync(vop
->dev
);
439 dev_err(vop
->dev
, "failed to get pm runtime: %d\n", ret
);
443 ret
= clk_enable(vop
->hclk
);
445 dev_err(vop
->dev
, "failed to enable hclk - %d\n", ret
);
449 ret
= clk_enable(vop
->dclk
);
451 dev_err(vop
->dev
, "failed to enable dclk - %d\n", ret
);
452 goto err_disable_hclk
;
455 ret
= clk_enable(vop
->aclk
);
457 dev_err(vop
->dev
, "failed to enable aclk - %d\n", ret
);
458 goto err_disable_dclk
;
462 * Slave iommu shares power, irq and clock with vop. It was associated
463 * automatically with this master device via common driver code.
464 * Now that we have enabled the clock we attach it to the shared drm
467 ret
= rockchip_drm_dma_attach_device(vop
->drm_dev
, vop
->dev
);
469 dev_err(vop
->dev
, "failed to attach dma mapping, %d\n", ret
);
470 goto err_disable_aclk
;
473 memcpy(vop
->regs
, vop
->regsbak
, vop
->len
);
475 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
477 vop
->is_enabled
= true;
479 spin_lock(&vop
->reg_lock
);
481 VOP_CTRL_SET(vop
, standby
, 0);
483 spin_unlock(&vop
->reg_lock
);
485 enable_irq(vop
->irq
);
487 drm_crtc_vblank_on(crtc
);
492 clk_disable(vop
->aclk
);
494 clk_disable(vop
->dclk
);
496 clk_disable(vop
->hclk
);
499 static void vop_crtc_disable(struct drm_crtc
*crtc
)
501 struct vop
*vop
= to_vop(crtc
);
503 if (!vop
->is_enabled
)
506 drm_crtc_vblank_off(crtc
);
509 * Vop standby will take effect at end of current frame,
510 * if dsp hold valid irq happen, it means standby complete.
512 * we must wait standby complete when we want to disable aclk,
513 * if not, memory bus maybe dead.
515 reinit_completion(&vop
->dsp_hold_completion
);
516 vop_dsp_hold_valid_irq_enable(vop
);
518 spin_lock(&vop
->reg_lock
);
520 VOP_CTRL_SET(vop
, standby
, 1);
522 spin_unlock(&vop
->reg_lock
);
524 wait_for_completion(&vop
->dsp_hold_completion
);
526 vop_dsp_hold_valid_irq_disable(vop
);
528 disable_irq(vop
->irq
);
530 vop
->is_enabled
= false;
533 * vop standby complete, so iommu detach is safe.
535 rockchip_drm_dma_detach_device(vop
->drm_dev
, vop
->dev
);
537 clk_disable(vop
->dclk
);
538 clk_disable(vop
->aclk
);
539 clk_disable(vop
->hclk
);
540 pm_runtime_put(vop
->dev
);
543 static void vop_plane_destroy(struct drm_plane
*plane
)
545 drm_plane_cleanup(plane
);
548 static int vop_plane_atomic_check(struct drm_plane
*plane
,
549 struct drm_plane_state
*state
)
551 struct drm_crtc
*crtc
= state
->crtc
;
552 struct drm_framebuffer
*fb
= state
->fb
;
553 struct vop_win
*vop_win
= to_vop_win(plane
);
554 struct vop_plane_state
*vop_plane_state
= to_vop_plane_state(state
);
555 const struct vop_win_data
*win
= vop_win
->data
;
558 struct drm_rect
*dest
= &vop_plane_state
->dest
;
559 struct drm_rect
*src
= &vop_plane_state
->src
;
560 struct drm_rect clip
;
561 int min_scale
= win
->phy
->scl
? FRAC_16_16(1, 8) :
562 DRM_PLANE_HELPER_NO_SCALING
;
563 int max_scale
= win
->phy
->scl
? FRAC_16_16(8, 1) :
564 DRM_PLANE_HELPER_NO_SCALING
;
566 crtc
= crtc
? crtc
: plane
->state
->crtc
;
568 * Both crtc or plane->state->crtc can be null.
572 src
->x1
= state
->src_x
;
573 src
->y1
= state
->src_y
;
574 src
->x2
= state
->src_x
+ state
->src_w
;
575 src
->y2
= state
->src_y
+ state
->src_h
;
576 dest
->x1
= state
->crtc_x
;
577 dest
->y1
= state
->crtc_y
;
578 dest
->x2
= state
->crtc_x
+ state
->crtc_w
;
579 dest
->y2
= state
->crtc_y
+ state
->crtc_h
;
583 clip
.x2
= crtc
->mode
.hdisplay
;
584 clip
.y2
= crtc
->mode
.vdisplay
;
586 ret
= drm_plane_helper_check_update(plane
, crtc
, state
->fb
,
590 true, true, &visible
);
597 vop_plane_state
->format
= vop_convert_format(fb
->pixel_format
);
598 if (vop_plane_state
->format
< 0)
599 return vop_plane_state
->format
;
602 * Src.x1 can be odd when do clip, but yuv plane start point
603 * need align with 2 pixel.
605 if (is_yuv_support(fb
->pixel_format
) && ((src
->x1
>> 16) % 2))
608 vop_plane_state
->enable
= true;
613 vop_plane_state
->enable
= false;
617 static void vop_plane_atomic_disable(struct drm_plane
*plane
,
618 struct drm_plane_state
*old_state
)
620 struct vop_plane_state
*vop_plane_state
= to_vop_plane_state(old_state
);
621 struct vop_win
*vop_win
= to_vop_win(plane
);
622 const struct vop_win_data
*win
= vop_win
->data
;
623 struct vop
*vop
= to_vop(old_state
->crtc
);
625 if (!old_state
->crtc
)
628 spin_lock(&vop
->reg_lock
);
630 VOP_WIN_SET(vop
, win
, enable
, 0);
632 spin_unlock(&vop
->reg_lock
);
634 vop_plane_state
->enable
= false;
637 static void vop_plane_atomic_update(struct drm_plane
*plane
,
638 struct drm_plane_state
*old_state
)
640 struct drm_plane_state
*state
= plane
->state
;
641 struct drm_crtc
*crtc
= state
->crtc
;
642 struct vop_win
*vop_win
= to_vop_win(plane
);
643 struct vop_plane_state
*vop_plane_state
= to_vop_plane_state(state
);
644 const struct vop_win_data
*win
= vop_win
->data
;
645 struct vop
*vop
= to_vop(state
->crtc
);
646 struct drm_framebuffer
*fb
= state
->fb
;
647 unsigned int actual_w
, actual_h
;
648 unsigned int dsp_stx
, dsp_sty
;
649 uint32_t act_info
, dsp_info
, dsp_st
;
650 struct drm_rect
*src
= &vop_plane_state
->src
;
651 struct drm_rect
*dest
= &vop_plane_state
->dest
;
652 struct drm_gem_object
*obj
, *uv_obj
;
653 struct rockchip_gem_object
*rk_obj
, *rk_uv_obj
;
654 unsigned long offset
;
660 * can't update plane when vop is disabled.
665 if (WARN_ON(!vop
->is_enabled
))
668 if (!vop_plane_state
->enable
) {
669 vop_plane_atomic_disable(plane
, old_state
);
673 obj
= rockchip_fb_get_gem_obj(fb
, 0);
674 rk_obj
= to_rockchip_obj(obj
);
676 actual_w
= drm_rect_width(src
) >> 16;
677 actual_h
= drm_rect_height(src
) >> 16;
678 act_info
= (actual_h
- 1) << 16 | ((actual_w
- 1) & 0xffff);
680 dsp_info
= (drm_rect_height(dest
) - 1) << 16;
681 dsp_info
|= (drm_rect_width(dest
) - 1) & 0xffff;
683 dsp_stx
= dest
->x1
+ crtc
->mode
.htotal
- crtc
->mode
.hsync_start
;
684 dsp_sty
= dest
->y1
+ crtc
->mode
.vtotal
- crtc
->mode
.vsync_start
;
685 dsp_st
= dsp_sty
<< 16 | (dsp_stx
& 0xffff);
687 offset
= (src
->x1
>> 16) * drm_format_plane_cpp(fb
->pixel_format
, 0);
688 offset
+= (src
->y1
>> 16) * fb
->pitches
[0];
689 vop_plane_state
->yrgb_mst
= rk_obj
->dma_addr
+ offset
+ fb
->offsets
[0];
691 spin_lock(&vop
->reg_lock
);
693 VOP_WIN_SET(vop
, win
, format
, vop_plane_state
->format
);
694 VOP_WIN_SET(vop
, win
, yrgb_vir
, fb
->pitches
[0] >> 2);
695 VOP_WIN_SET(vop
, win
, yrgb_mst
, vop_plane_state
->yrgb_mst
);
696 if (is_yuv_support(fb
->pixel_format
)) {
697 int hsub
= drm_format_horz_chroma_subsampling(fb
->pixel_format
);
698 int vsub
= drm_format_vert_chroma_subsampling(fb
->pixel_format
);
699 int bpp
= drm_format_plane_cpp(fb
->pixel_format
, 1);
701 uv_obj
= rockchip_fb_get_gem_obj(fb
, 1);
702 rk_uv_obj
= to_rockchip_obj(uv_obj
);
704 offset
= (src
->x1
>> 16) * bpp
/ hsub
;
705 offset
+= (src
->y1
>> 16) * fb
->pitches
[1] / vsub
;
707 dma_addr
= rk_uv_obj
->dma_addr
+ offset
+ fb
->offsets
[1];
708 VOP_WIN_SET(vop
, win
, uv_vir
, fb
->pitches
[1] >> 2);
709 VOP_WIN_SET(vop
, win
, uv_mst
, dma_addr
);
713 scl_vop_cal_scl_fac(vop
, win
, actual_w
, actual_h
,
714 drm_rect_width(dest
), drm_rect_height(dest
),
717 VOP_WIN_SET(vop
, win
, act_info
, act_info
);
718 VOP_WIN_SET(vop
, win
, dsp_info
, dsp_info
);
719 VOP_WIN_SET(vop
, win
, dsp_st
, dsp_st
);
721 rb_swap
= has_rb_swapped(fb
->pixel_format
);
722 VOP_WIN_SET(vop
, win
, rb_swap
, rb_swap
);
724 if (is_alpha_support(fb
->pixel_format
)) {
725 VOP_WIN_SET(vop
, win
, dst_alpha_ctl
,
726 DST_FACTOR_M0(ALPHA_SRC_INVERSE
));
727 val
= SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL
) |
728 SRC_ALPHA_M0(ALPHA_STRAIGHT
) |
729 SRC_BLEND_M0(ALPHA_PER_PIX
) |
730 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION
) |
731 SRC_FACTOR_M0(ALPHA_ONE
);
732 VOP_WIN_SET(vop
, win
, src_alpha_ctl
, val
);
734 VOP_WIN_SET(vop
, win
, src_alpha_ctl
, SRC_ALPHA_EN(0));
737 VOP_WIN_SET(vop
, win
, enable
, 1);
738 spin_unlock(&vop
->reg_lock
);
741 static const struct drm_plane_helper_funcs plane_helper_funcs
= {
742 .atomic_check
= vop_plane_atomic_check
,
743 .atomic_update
= vop_plane_atomic_update
,
744 .atomic_disable
= vop_plane_atomic_disable
,
747 void vop_atomic_plane_reset(struct drm_plane
*plane
)
749 struct vop_plane_state
*vop_plane_state
=
750 to_vop_plane_state(plane
->state
);
752 if (plane
->state
&& plane
->state
->fb
)
753 drm_framebuffer_unreference(plane
->state
->fb
);
755 kfree(vop_plane_state
);
756 vop_plane_state
= kzalloc(sizeof(*vop_plane_state
), GFP_KERNEL
);
757 if (!vop_plane_state
)
760 plane
->state
= &vop_plane_state
->base
;
761 plane
->state
->plane
= plane
;
764 struct drm_plane_state
*
765 vop_atomic_plane_duplicate_state(struct drm_plane
*plane
)
767 struct vop_plane_state
*old_vop_plane_state
;
768 struct vop_plane_state
*vop_plane_state
;
770 if (WARN_ON(!plane
->state
))
773 old_vop_plane_state
= to_vop_plane_state(plane
->state
);
774 vop_plane_state
= kmemdup(old_vop_plane_state
,
775 sizeof(*vop_plane_state
), GFP_KERNEL
);
776 if (!vop_plane_state
)
779 __drm_atomic_helper_plane_duplicate_state(plane
,
780 &vop_plane_state
->base
);
782 return &vop_plane_state
->base
;
785 static void vop_atomic_plane_destroy_state(struct drm_plane
*plane
,
786 struct drm_plane_state
*state
)
788 struct vop_plane_state
*vop_state
= to_vop_plane_state(state
);
790 __drm_atomic_helper_plane_destroy_state(plane
, state
);
795 static const struct drm_plane_funcs vop_plane_funcs
= {
796 .update_plane
= drm_atomic_helper_update_plane
,
797 .disable_plane
= drm_atomic_helper_disable_plane
,
798 .destroy
= vop_plane_destroy
,
799 .reset
= vop_atomic_plane_reset
,
800 .atomic_duplicate_state
= vop_atomic_plane_duplicate_state
,
801 .atomic_destroy_state
= vop_atomic_plane_destroy_state
,
804 int rockchip_drm_crtc_mode_config(struct drm_crtc
*crtc
,
808 struct vop
*vop
= to_vop(crtc
);
810 if (WARN_ON(!vop
->is_enabled
))
813 switch (connector_type
) {
814 case DRM_MODE_CONNECTOR_LVDS
:
815 VOP_CTRL_SET(vop
, rgb_en
, 1);
817 case DRM_MODE_CONNECTOR_eDP
:
818 VOP_CTRL_SET(vop
, edp_en
, 1);
820 case DRM_MODE_CONNECTOR_HDMIA
:
821 VOP_CTRL_SET(vop
, hdmi_en
, 1);
823 case DRM_MODE_CONNECTOR_DSI
:
824 VOP_CTRL_SET(vop
, mipi_en
, 1);
827 DRM_ERROR("unsupport connector_type[%d]\n", connector_type
);
830 VOP_CTRL_SET(vop
, out_mode
, out_mode
);
834 EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config
);
836 static int vop_crtc_enable_vblank(struct drm_crtc
*crtc
)
838 struct vop
*vop
= to_vop(crtc
);
841 if (WARN_ON(!vop
->is_enabled
))
844 spin_lock_irqsave(&vop
->irq_lock
, flags
);
846 VOP_INTR_SET_TYPE(vop
, enable
, FS_INTR
, 1);
848 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
853 static void vop_crtc_disable_vblank(struct drm_crtc
*crtc
)
855 struct vop
*vop
= to_vop(crtc
);
858 if (WARN_ON(!vop
->is_enabled
))
861 spin_lock_irqsave(&vop
->irq_lock
, flags
);
863 VOP_INTR_SET_TYPE(vop
, enable
, FS_INTR
, 0);
865 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
868 static void vop_crtc_wait_for_update(struct drm_crtc
*crtc
)
870 struct vop
*vop
= to_vop(crtc
);
872 reinit_completion(&vop
->wait_update_complete
);
873 WARN_ON(!wait_for_completion_timeout(&vop
->wait_update_complete
, 100));
876 static const struct rockchip_crtc_funcs private_crtc_funcs
= {
877 .enable_vblank
= vop_crtc_enable_vblank
,
878 .disable_vblank
= vop_crtc_disable_vblank
,
879 .wait_for_update
= vop_crtc_wait_for_update
,
882 static bool vop_crtc_mode_fixup(struct drm_crtc
*crtc
,
883 const struct drm_display_mode
*mode
,
884 struct drm_display_mode
*adjusted_mode
)
886 struct vop
*vop
= to_vop(crtc
);
888 if (adjusted_mode
->htotal
== 0 || adjusted_mode
->vtotal
== 0)
891 adjusted_mode
->clock
=
892 clk_round_rate(vop
->dclk
, mode
->clock
* 1000) / 1000;
897 static void vop_crtc_enable(struct drm_crtc
*crtc
)
899 struct vop
*vop
= to_vop(crtc
);
900 struct drm_display_mode
*adjusted_mode
= &crtc
->state
->adjusted_mode
;
901 u16 hsync_len
= adjusted_mode
->hsync_end
- adjusted_mode
->hsync_start
;
902 u16 hdisplay
= adjusted_mode
->hdisplay
;
903 u16 htotal
= adjusted_mode
->htotal
;
904 u16 hact_st
= adjusted_mode
->htotal
- adjusted_mode
->hsync_start
;
905 u16 hact_end
= hact_st
+ hdisplay
;
906 u16 vdisplay
= adjusted_mode
->vdisplay
;
907 u16 vtotal
= adjusted_mode
->vtotal
;
908 u16 vsync_len
= adjusted_mode
->vsync_end
- adjusted_mode
->vsync_start
;
909 u16 vact_st
= adjusted_mode
->vtotal
- adjusted_mode
->vsync_start
;
910 u16 vact_end
= vact_st
+ vdisplay
;
915 * If dclk rate is zero, mean that scanout is stop,
916 * we don't need wait any more.
918 if (clk_get_rate(vop
->dclk
)) {
920 * Rk3288 vop timing register is immediately, when configure
921 * display timing on display time, may cause tearing.
923 * Vop standby will take effect at end of current frame,
924 * if dsp hold valid irq happen, it means standby complete.
927 * standby and wait complete --> |----
931 * configure display timing --> |
936 reinit_completion(&vop
->dsp_hold_completion
);
937 vop_dsp_hold_valid_irq_enable(vop
);
939 spin_lock(&vop
->reg_lock
);
941 VOP_CTRL_SET(vop
, standby
, 1);
943 spin_unlock(&vop
->reg_lock
);
945 wait_for_completion(&vop
->dsp_hold_completion
);
947 vop_dsp_hold_valid_irq_disable(vop
);
951 val
|= (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
) ? 0 : 1;
952 val
|= (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
) ? 0 : (1 << 1);
953 VOP_CTRL_SET(vop
, pin_pol
, val
);
955 VOP_CTRL_SET(vop
, htotal_pw
, (htotal
<< 16) | hsync_len
);
958 VOP_CTRL_SET(vop
, hact_st_end
, val
);
959 VOP_CTRL_SET(vop
, hpost_st_end
, val
);
961 VOP_CTRL_SET(vop
, vtotal_pw
, (vtotal
<< 16) | vsync_len
);
964 VOP_CTRL_SET(vop
, vact_st_end
, val
);
965 VOP_CTRL_SET(vop
, vpost_st_end
, val
);
967 clk_set_rate(vop
->dclk
, adjusted_mode
->clock
* 1000);
969 VOP_CTRL_SET(vop
, standby
, 0);
972 static void vop_crtc_atomic_flush(struct drm_crtc
*crtc
,
973 struct drm_crtc_state
*old_crtc_state
)
975 struct vop
*vop
= to_vop(crtc
);
977 if (WARN_ON(!vop
->is_enabled
))
980 spin_lock(&vop
->reg_lock
);
984 spin_unlock(&vop
->reg_lock
);
987 static void vop_crtc_atomic_begin(struct drm_crtc
*crtc
,
988 struct drm_crtc_state
*old_crtc_state
)
990 struct vop
*vop
= to_vop(crtc
);
992 if (crtc
->state
->event
) {
993 WARN_ON(drm_crtc_vblank_get(crtc
) != 0);
995 vop
->event
= crtc
->state
->event
;
996 crtc
->state
->event
= NULL
;
1000 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs
= {
1001 .enable
= vop_crtc_enable
,
1002 .disable
= vop_crtc_disable
,
1003 .mode_fixup
= vop_crtc_mode_fixup
,
1004 .atomic_flush
= vop_crtc_atomic_flush
,
1005 .atomic_begin
= vop_crtc_atomic_begin
,
1008 static void vop_crtc_destroy(struct drm_crtc
*crtc
)
1010 drm_crtc_cleanup(crtc
);
1013 static const struct drm_crtc_funcs vop_crtc_funcs
= {
1014 .set_config
= drm_atomic_helper_set_config
,
1015 .page_flip
= drm_atomic_helper_page_flip
,
1016 .destroy
= vop_crtc_destroy
,
1017 .reset
= drm_atomic_helper_crtc_reset
,
1018 .atomic_duplicate_state
= drm_atomic_helper_crtc_duplicate_state
,
1019 .atomic_destroy_state
= drm_atomic_helper_crtc_destroy_state
,
1022 static bool vop_win_pending_is_complete(struct vop_win
*vop_win
)
1024 struct drm_plane
*plane
= &vop_win
->base
;
1025 struct vop_plane_state
*state
= to_vop_plane_state(plane
->state
);
1026 dma_addr_t yrgb_mst
;
1029 return VOP_WIN_GET(vop_win
->vop
, vop_win
->data
, enable
) == 0;
1031 yrgb_mst
= VOP_WIN_GET_YRGBADDR(vop_win
->vop
, vop_win
->data
);
1033 return yrgb_mst
== state
->yrgb_mst
;
1036 static void vop_handle_vblank(struct vop
*vop
)
1038 struct drm_device
*drm
= vop
->drm_dev
;
1039 struct drm_crtc
*crtc
= &vop
->crtc
;
1040 unsigned long flags
;
1043 for (i
= 0; i
< vop
->data
->win_size
; i
++) {
1044 if (!vop_win_pending_is_complete(&vop
->win
[i
]))
1049 spin_lock_irqsave(&drm
->event_lock
, flags
);
1051 drm_crtc_send_vblank_event(crtc
, vop
->event
);
1052 drm_crtc_vblank_put(crtc
);
1055 spin_unlock_irqrestore(&drm
->event_lock
, flags
);
1057 if (!completion_done(&vop
->wait_update_complete
))
1058 complete(&vop
->wait_update_complete
);
1061 static irqreturn_t
vop_isr(int irq
, void *data
)
1063 struct vop
*vop
= data
;
1064 struct drm_crtc
*crtc
= &vop
->crtc
;
1065 uint32_t active_irqs
;
1066 unsigned long flags
;
1070 * interrupt register has interrupt status, enable and clear bits, we
1071 * must hold irq_lock to avoid a race with enable/disable_vblank().
1073 spin_lock_irqsave(&vop
->irq_lock
, flags
);
1075 active_irqs
= VOP_INTR_GET_TYPE(vop
, status
, INTR_MASK
);
1076 /* Clear all active interrupt sources */
1078 VOP_INTR_SET_TYPE(vop
, clear
, active_irqs
, 1);
1080 spin_unlock_irqrestore(&vop
->irq_lock
, flags
);
1082 /* This is expected for vop iommu irqs, since the irq is shared */
1086 if (active_irqs
& DSP_HOLD_VALID_INTR
) {
1087 complete(&vop
->dsp_hold_completion
);
1088 active_irqs
&= ~DSP_HOLD_VALID_INTR
;
1092 if (active_irqs
& FS_INTR
) {
1093 drm_crtc_handle_vblank(crtc
);
1094 vop_handle_vblank(vop
);
1095 active_irqs
&= ~FS_INTR
;
1099 /* Unhandled irqs are spurious. */
1101 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs
);
1106 static int vop_create_crtc(struct vop
*vop
)
1108 const struct vop_data
*vop_data
= vop
->data
;
1109 struct device
*dev
= vop
->dev
;
1110 struct drm_device
*drm_dev
= vop
->drm_dev
;
1111 struct drm_plane
*primary
= NULL
, *cursor
= NULL
, *plane
;
1112 struct drm_crtc
*crtc
= &vop
->crtc
;
1113 struct device_node
*port
;
1118 * Create drm_plane for primary and cursor planes first, since we need
1119 * to pass them to drm_crtc_init_with_planes, which sets the
1120 * "possible_crtcs" to the newly initialized crtc.
1122 for (i
= 0; i
< vop_data
->win_size
; i
++) {
1123 struct vop_win
*vop_win
= &vop
->win
[i
];
1124 const struct vop_win_data
*win_data
= vop_win
->data
;
1126 if (win_data
->type
!= DRM_PLANE_TYPE_PRIMARY
&&
1127 win_data
->type
!= DRM_PLANE_TYPE_CURSOR
)
1130 ret
= drm_universal_plane_init(vop
->drm_dev
, &vop_win
->base
,
1131 0, &vop_plane_funcs
,
1132 win_data
->phy
->data_formats
,
1133 win_data
->phy
->nformats
,
1134 win_data
->type
, NULL
);
1136 DRM_ERROR("failed to initialize plane\n");
1137 goto err_cleanup_planes
;
1140 plane
= &vop_win
->base
;
1141 drm_plane_helper_add(plane
, &plane_helper_funcs
);
1142 if (plane
->type
== DRM_PLANE_TYPE_PRIMARY
)
1144 else if (plane
->type
== DRM_PLANE_TYPE_CURSOR
)
1148 ret
= drm_crtc_init_with_planes(drm_dev
, crtc
, primary
, cursor
,
1149 &vop_crtc_funcs
, NULL
);
1153 drm_crtc_helper_add(crtc
, &vop_crtc_helper_funcs
);
1156 * Create drm_planes for overlay windows with possible_crtcs restricted
1157 * to the newly created crtc.
1159 for (i
= 0; i
< vop_data
->win_size
; i
++) {
1160 struct vop_win
*vop_win
= &vop
->win
[i
];
1161 const struct vop_win_data
*win_data
= vop_win
->data
;
1162 unsigned long possible_crtcs
= 1 << drm_crtc_index(crtc
);
1164 if (win_data
->type
!= DRM_PLANE_TYPE_OVERLAY
)
1167 ret
= drm_universal_plane_init(vop
->drm_dev
, &vop_win
->base
,
1170 win_data
->phy
->data_formats
,
1171 win_data
->phy
->nformats
,
1172 win_data
->type
, NULL
);
1174 DRM_ERROR("failed to initialize overlay plane\n");
1175 goto err_cleanup_crtc
;
1177 drm_plane_helper_add(&vop_win
->base
, &plane_helper_funcs
);
1180 port
= of_get_child_by_name(dev
->of_node
, "port");
1182 DRM_ERROR("no port node found in %s\n",
1183 dev
->of_node
->full_name
);
1184 goto err_cleanup_crtc
;
1187 init_completion(&vop
->dsp_hold_completion
);
1188 init_completion(&vop
->wait_update_complete
);
1190 rockchip_register_crtc_funcs(crtc
, &private_crtc_funcs
);
1195 drm_crtc_cleanup(crtc
);
1197 list_for_each_entry(plane
, &drm_dev
->mode_config
.plane_list
, head
)
1198 drm_plane_cleanup(plane
);
1202 static void vop_destroy_crtc(struct vop
*vop
)
1204 struct drm_crtc
*crtc
= &vop
->crtc
;
1206 rockchip_unregister_crtc_funcs(crtc
);
1207 of_node_put(crtc
->port
);
1208 drm_crtc_cleanup(crtc
);
1211 static int vop_initial(struct vop
*vop
)
1213 const struct vop_data
*vop_data
= vop
->data
;
1214 const struct vop_reg_data
*init_table
= vop_data
->init_table
;
1215 struct reset_control
*ahb_rst
;
1218 vop
->hclk
= devm_clk_get(vop
->dev
, "hclk_vop");
1219 if (IS_ERR(vop
->hclk
)) {
1220 dev_err(vop
->dev
, "failed to get hclk source\n");
1221 return PTR_ERR(vop
->hclk
);
1223 vop
->aclk
= devm_clk_get(vop
->dev
, "aclk_vop");
1224 if (IS_ERR(vop
->aclk
)) {
1225 dev_err(vop
->dev
, "failed to get aclk source\n");
1226 return PTR_ERR(vop
->aclk
);
1228 vop
->dclk
= devm_clk_get(vop
->dev
, "dclk_vop");
1229 if (IS_ERR(vop
->dclk
)) {
1230 dev_err(vop
->dev
, "failed to get dclk source\n");
1231 return PTR_ERR(vop
->dclk
);
1234 ret
= clk_prepare(vop
->dclk
);
1236 dev_err(vop
->dev
, "failed to prepare dclk\n");
1240 /* Enable both the hclk and aclk to setup the vop */
1241 ret
= clk_prepare_enable(vop
->hclk
);
1243 dev_err(vop
->dev
, "failed to prepare/enable hclk\n");
1244 goto err_unprepare_dclk
;
1247 ret
= clk_prepare_enable(vop
->aclk
);
1249 dev_err(vop
->dev
, "failed to prepare/enable aclk\n");
1250 goto err_disable_hclk
;
1254 * do hclk_reset, reset all vop registers.
1256 ahb_rst
= devm_reset_control_get(vop
->dev
, "ahb");
1257 if (IS_ERR(ahb_rst
)) {
1258 dev_err(vop
->dev
, "failed to get ahb reset\n");
1259 ret
= PTR_ERR(ahb_rst
);
1260 goto err_disable_aclk
;
1262 reset_control_assert(ahb_rst
);
1263 usleep_range(10, 20);
1264 reset_control_deassert(ahb_rst
);
1266 memcpy(vop
->regsbak
, vop
->regs
, vop
->len
);
1268 for (i
= 0; i
< vop_data
->table_size
; i
++)
1269 vop_writel(vop
, init_table
[i
].offset
, init_table
[i
].value
);
1271 for (i
= 0; i
< vop_data
->win_size
; i
++) {
1272 const struct vop_win_data
*win
= &vop_data
->win
[i
];
1274 VOP_WIN_SET(vop
, win
, enable
, 0);
1280 * do dclk_reset, let all config take affect.
1282 vop
->dclk_rst
= devm_reset_control_get(vop
->dev
, "dclk");
1283 if (IS_ERR(vop
->dclk_rst
)) {
1284 dev_err(vop
->dev
, "failed to get dclk reset\n");
1285 ret
= PTR_ERR(vop
->dclk_rst
);
1286 goto err_disable_aclk
;
1288 reset_control_assert(vop
->dclk_rst
);
1289 usleep_range(10, 20);
1290 reset_control_deassert(vop
->dclk_rst
);
1292 clk_disable(vop
->hclk
);
1293 clk_disable(vop
->aclk
);
1295 vop
->is_enabled
= false;
1300 clk_disable_unprepare(vop
->aclk
);
1302 clk_disable_unprepare(vop
->hclk
);
1304 clk_unprepare(vop
->dclk
);
1309 * Initialize the vop->win array elements.
1311 static void vop_win_init(struct vop
*vop
)
1313 const struct vop_data
*vop_data
= vop
->data
;
1316 for (i
= 0; i
< vop_data
->win_size
; i
++) {
1317 struct vop_win
*vop_win
= &vop
->win
[i
];
1318 const struct vop_win_data
*win_data
= &vop_data
->win
[i
];
1320 vop_win
->data
= win_data
;
1325 static int vop_bind(struct device
*dev
, struct device
*master
, void *data
)
1327 struct platform_device
*pdev
= to_platform_device(dev
);
1328 const struct vop_data
*vop_data
;
1329 struct drm_device
*drm_dev
= data
;
1331 struct resource
*res
;
1335 vop_data
= of_device_get_match_data(dev
);
1339 /* Allocate vop struct and its vop_win array */
1340 alloc_size
= sizeof(*vop
) + sizeof(*vop
->win
) * vop_data
->win_size
;
1341 vop
= devm_kzalloc(dev
, alloc_size
, GFP_KERNEL
);
1346 vop
->data
= vop_data
;
1347 vop
->drm_dev
= drm_dev
;
1348 dev_set_drvdata(dev
, vop
);
1352 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1353 vop
->len
= resource_size(res
);
1354 vop
->regs
= devm_ioremap_resource(dev
, res
);
1355 if (IS_ERR(vop
->regs
))
1356 return PTR_ERR(vop
->regs
);
1358 vop
->regsbak
= devm_kzalloc(dev
, vop
->len
, GFP_KERNEL
);
1362 ret
= vop_initial(vop
);
1364 dev_err(&pdev
->dev
, "cannot initial vop dev - err %d\n", ret
);
1368 irq
= platform_get_irq(pdev
, 0);
1370 dev_err(dev
, "cannot find irq for vop\n");
1373 vop
->irq
= (unsigned int)irq
;
1375 spin_lock_init(&vop
->reg_lock
);
1376 spin_lock_init(&vop
->irq_lock
);
1378 mutex_init(&vop
->vsync_mutex
);
1380 ret
= devm_request_irq(dev
, vop
->irq
, vop_isr
,
1381 IRQF_SHARED
, dev_name(dev
), vop
);
1385 /* IRQ is initially disabled; it gets enabled in power_on */
1386 disable_irq(vop
->irq
);
1388 ret
= vop_create_crtc(vop
);
1392 pm_runtime_enable(&pdev
->dev
);
1396 static void vop_unbind(struct device
*dev
, struct device
*master
, void *data
)
1398 struct vop
*vop
= dev_get_drvdata(dev
);
1400 pm_runtime_disable(dev
);
1401 vop_destroy_crtc(vop
);
1404 const struct component_ops vop_component_ops
= {
1406 .unbind
= vop_unbind
,
1408 EXPORT_SYMBOL_GPL(vop_component_ops
);