drivers/gpu/drm/sti/sti_hda.c

   1 /*
   2  * Copyright (C) STMicroelectronics SA 2014
   3  * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
   4  * License terms:  GNU General Public License (GPL), version 2
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/component.h>
   9 #include <linux/module.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/seq_file.h>
  12
  13 #include <drm/drmP.h>
  14 #include <drm/drm_atomic_helper.h>
  15 #include <drm/drm_crtc_helper.h>
  16
  17 /* HDformatter registers */
  18 #define HDA_ANA_CFG                     0x0000
  19 #define HDA_ANA_SCALE_CTRL_Y            0x0004
  20 #define HDA_ANA_SCALE_CTRL_CB           0x0008
  21 #define HDA_ANA_SCALE_CTRL_CR           0x000C
  22 #define HDA_ANA_ANC_CTRL                0x0010
  23 #define HDA_ANA_SRC_Y_CFG               0x0014
  24 #define HDA_COEFF_Y_PH1_TAP123          0x0018
  25 #define HDA_COEFF_Y_PH1_TAP456          0x001C
  26 #define HDA_COEFF_Y_PH2_TAP123          0x0020
  27 #define HDA_COEFF_Y_PH2_TAP456          0x0024
  28 #define HDA_COEFF_Y_PH3_TAP123          0x0028
  29 #define HDA_COEFF_Y_PH3_TAP456          0x002C
  30 #define HDA_COEFF_Y_PH4_TAP123          0x0030
  31 #define HDA_COEFF_Y_PH4_TAP456          0x0034
  32 #define HDA_ANA_SRC_C_CFG               0x0040
  33 #define HDA_COEFF_C_PH1_TAP123          0x0044
  34 #define HDA_COEFF_C_PH1_TAP456          0x0048
  35 #define HDA_COEFF_C_PH2_TAP123          0x004C
  36 #define HDA_COEFF_C_PH2_TAP456          0x0050
  37 #define HDA_COEFF_C_PH3_TAP123          0x0054
  38 #define HDA_COEFF_C_PH3_TAP456          0x0058
  39 #define HDA_COEFF_C_PH4_TAP123          0x005C
  40 #define HDA_COEFF_C_PH4_TAP456          0x0060
  41 #define HDA_SYNC_AWGI                   0x0300
  42
  43 /* HDA_ANA_CFG */
  44 #define CFG_AWG_ASYNC_EN                BIT(0)
  45 #define CFG_AWG_ASYNC_HSYNC_MTD         BIT(1)
  46 #define CFG_AWG_ASYNC_VSYNC_MTD         BIT(2)
  47 #define CFG_AWG_SYNC_DEL                BIT(3)
  48 #define CFG_AWG_FLTR_MODE_SHIFT         4
  49 #define CFG_AWG_FLTR_MODE_MASK          (0xF << CFG_AWG_FLTR_MODE_SHIFT)
  50 #define CFG_AWG_FLTR_MODE_SD            (0 << CFG_AWG_FLTR_MODE_SHIFT)
  51 #define CFG_AWG_FLTR_MODE_ED            (1 << CFG_AWG_FLTR_MODE_SHIFT)
  52 #define CFG_AWG_FLTR_MODE_HD            (2 << CFG_AWG_FLTR_MODE_SHIFT)
  53 #define CFG_SYNC_ON_PBPR_MASK           BIT(8)
  54 #define CFG_PREFILTER_EN_MASK           BIT(9)
  55 #define CFG_PBPR_SYNC_OFF_SHIFT         16
  56 #define CFG_PBPR_SYNC_OFF_MASK          (0x7FF << CFG_PBPR_SYNC_OFF_SHIFT)
  57 #define CFG_PBPR_SYNC_OFF_VAL           0x117 /* Voltage dependent. stiH416 */
  58
  59 /* Default scaling values */
  60 #define SCALE_CTRL_Y_DFLT               0x00C50256
  61 #define SCALE_CTRL_CB_DFLT              0x00DB0249
  62 #define SCALE_CTRL_CR_DFLT              0x00DB0249
  63
  64 /* Video DACs control */
  65 #define VIDEO_DACS_CONTROL_MASK         0x0FFF
  66 #define VIDEO_DACS_CONTROL_SYSCFG2535   0x085C /* for stih416 */
  67 #define DAC_CFG_HD_OFF_SHIFT            5
  68 #define DAC_CFG_HD_OFF_MASK             (0x7 << DAC_CFG_HD_OFF_SHIFT)
  69 #define VIDEO_DACS_CONTROL_SYSCFG5072   0x0120 /* for stih407 */
  70 #define DAC_CFG_HD_HZUVW_OFF_MASK       BIT(1)
  71
  72
  73 /* Upsampler values for the alternative 2X Filter */
  74 #define SAMPLER_COEF_NB                 8
  75 #define HDA_ANA_SRC_Y_CFG_ALT_2X        0x01130000
  76 static u32 coef_y_alt_2x[] = {
  77         0x00FE83FB, 0x1F900401, 0x00000000, 0x00000000,
  78         0x00F408F9, 0x055F7C25, 0x00000000, 0x00000000
  79 };
  80
  81 #define HDA_ANA_SRC_C_CFG_ALT_2X        0x01750004
  82 static u32 coef_c_alt_2x[] = {
  83         0x001305F7, 0x05274BD0, 0x00000000, 0x00000000,
  84         0x0004907C, 0x09C80B9D, 0x00000000, 0x00000000
  85 };
  86
  87 /* Upsampler values for the 4X Filter */
  88 #define HDA_ANA_SRC_Y_CFG_4X            0x01ED0005
  89 #define HDA_ANA_SRC_C_CFG_4X            0x01ED0004
  90 static u32 coef_yc_4x[] = {
  91         0x00FC827F, 0x008FE20B, 0x00F684FC, 0x050F7C24,
  92         0x00F4857C, 0x0A1F402E, 0x00FA027F, 0x0E076E1D
  93 };
  94
  95 /* AWG instructions for some video modes */
  96 #define AWG_MAX_INST                    64
  97
  98 /* 720p@50 */
  99 static u32 AWGi_720p_50[] = {
 100         0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA,
 101         0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B,
 102         0x00000D8E, 0x00000104, 0x00001804, 0x00000971,
 103         0x00000C26, 0x0000003B, 0x00000FB4, 0x00000FB5,
 104         0x00000104, 0x00001AE8
 105 };
 106
 107 #define NN_720p_50 ARRAY_SIZE(AWGi_720p_50)
 108
 109 /* 720p@60 */
 110 static u32 AWGi_720p_60[] = {
 111         0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA,
 112         0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B,
 113         0x00000C44, 0x00000104, 0x00001804, 0x00000971,
 114         0x00000C26, 0x0000003B, 0x00000F0F, 0x00000F10,
 115         0x00000104, 0x00001AE8
 116 };
 117
 118 #define NN_720p_60 ARRAY_SIZE(AWGi_720p_60)
 119
 120 /* 1080p@30 */
 121 static u32 AWGi_1080p_30[] = {
 122         0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
 123         0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
 124         0x00000C2A, 0x00000104, 0x00001804, 0x00000971,
 125         0x00000C2A, 0x0000003B, 0x00000EBE, 0x00000EBF,
 126         0x00000EBF, 0x00000104, 0x00001A2F, 0x00001C4B,
 127         0x00001C52
 128 };
 129
 130 #define NN_1080p_30 ARRAY_SIZE(AWGi_1080p_30)
 131
 132 /* 1080p@25 */
 133 static u32 AWGi_1080p_25[] = {
 134         0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
 135         0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
 136         0x00000DE2, 0x00000104, 0x00001804, 0x00000971,
 137         0x00000C2A, 0x0000003B, 0x00000F51, 0x00000F51,
 138         0x00000F52, 0x00000104, 0x00001A2F, 0x00001C4B,
 139         0x00001C52
 140 };
 141
 142 #define NN_1080p_25 ARRAY_SIZE(AWGi_1080p_25)
 143
 144 /* 1080p@24 */
 145 static u32 AWGi_1080p_24[] = {
 146         0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
 147         0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
 148         0x00000E50, 0x00000104, 0x00001804, 0x00000971,
 149         0x00000C2A, 0x0000003B, 0x00000F76, 0x00000F76,
 150         0x00000F76, 0x00000104, 0x00001A2F, 0x00001C4B,
 151         0x00001C52
 152 };
 153
 154 #define NN_1080p_24 ARRAY_SIZE(AWGi_1080p_24)
 155
 156 /* 720x480p@60 */
 157 static u32 AWGi_720x480p_60[] = {
 158         0x00000904, 0x00000F18, 0x0000013B, 0x00001805,
 159         0x00000904, 0x00000C3D, 0x0000003B, 0x00001A06
 160 };
 161
 162 #define NN_720x480p_60 ARRAY_SIZE(AWGi_720x480p_60)
 163
 164 /* Video mode category */
 165 enum sti_hda_vid_cat {
 166         VID_SD,
 167         VID_ED,
 168         VID_HD_74M,
 169         VID_HD_148M
 170 };
 171
 172 struct sti_hda_video_config {
 173         struct drm_display_mode mode;
 174         u32 *awg_instr;
 175         int nb_instr;
 176         enum sti_hda_vid_cat vid_cat;
 177 };
 178
 179 /* HD analog supported modes
 180  * Interlaced modes may be added when supported by the whole display chain
 181  */
 182 static const struct sti_hda_video_config hda_supported_modes[] = {
 183         /* 1080p30 74.250Mhz */
 184         {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
 185                    2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
 186                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 187          AWGi_1080p_30, NN_1080p_30, VID_HD_74M},
 188         /* 1080p30 74.176Mhz */
 189         {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74176, 1920, 2008,
 190                    2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
 191                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 192          AWGi_1080p_30, NN_1080p_30, VID_HD_74M},
 193         /* 1080p24 74.250Mhz */
 194         {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
 195                    2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
 196                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 197          AWGi_1080p_24, NN_1080p_24, VID_HD_74M},
 198         /* 1080p24 74.176Mhz */
 199         {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74176, 1920, 2558,
 200                    2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
 201                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 202          AWGi_1080p_24, NN_1080p_24, VID_HD_74M},
 203         /* 1080p25 74.250Mhz */
 204         {{DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
 205                    2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
 206                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 207          AWGi_1080p_25, NN_1080p_25, VID_HD_74M},
 208         /* 720p60 74.250Mhz */
 209         {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
 210                    1430, 1650, 0, 720, 725, 730, 750, 0,
 211                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 212          AWGi_720p_60, NN_720p_60, VID_HD_74M},
 213         /* 720p60 74.176Mhz */
 214         {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74176, 1280, 1390,
 215                    1430, 1650, 0, 720, 725, 730, 750, 0,
 216                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 217          AWGi_720p_60, NN_720p_60, VID_HD_74M},
 218         /* 720p50 74.250Mhz */
 219         {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
 220                    1760, 1980, 0, 720, 725, 730, 750, 0,
 221                    DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC)},
 222          AWGi_720p_50, NN_720p_50, VID_HD_74M},
 223         /* 720x480p60 27.027Mhz */
 224         {{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27027, 720, 736,
 225                    798, 858, 0, 480, 489, 495, 525, 0,
 226                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)},
 227          AWGi_720x480p_60, NN_720x480p_60, VID_ED},
 228         /* 720x480p60 27.000Mhz */
 229         {{DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
 230                    798, 858, 0, 480, 489, 495, 525, 0,
 231                    DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)},
 232          AWGi_720x480p_60, NN_720x480p_60, VID_ED}
 233 };
 234
 235 /**
 236  * STI hd analog structure
 237  *
 238  * @dev: driver device
 239  * @drm_dev: pointer to drm device
 240  * @mode: current display mode selected
 241  * @regs: HD analog register
 242  * @video_dacs_ctrl: video DACS control register
 243  * @enabled: true if HD analog is enabled else false
 244  */
 245 struct sti_hda {
 246         struct device dev;
 247         struct drm_device *drm_dev;
 248         struct drm_display_mode mode;
 249         void __iomem *regs;
 250         void __iomem *video_dacs_ctrl;
 251         struct clk *clk_pix;
 252         struct clk *clk_hddac;
 253         bool enabled;
 254 };
 255
 256 struct sti_hda_connector {
 257         struct drm_connector drm_connector;
 258         struct drm_encoder *encoder;
 259         struct sti_hda *hda;
 260 };
 261
 262 #define to_sti_hda_connector(x) \
 263         container_of(x, struct sti_hda_connector, drm_connector)
 264
 265 static u32 hda_read(struct sti_hda *hda, int offset)
 266 {
 267         return readl(hda->regs + offset);
 268 }
 269
 270 static void hda_write(struct sti_hda *hda, u32 val, int offset)
 271 {
 272         writel(val, hda->regs + offset);
 273 }
 274
 275 /**
 276  * Search for a video mode in the supported modes table
 277  *
 278  * @mode: mode being searched
 279  * @idx: index of the found mode
 280  *
 281  * Return true if mode is found
 282  */
 283 static bool hda_get_mode_idx(struct drm_display_mode mode, int *idx)
 284 {
 285         unsigned int i;
 286
 287         for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++)
 288                 if (drm_mode_equal(&hda_supported_modes[i].mode, &mode)) {
 289                         *idx = i;
 290                         return true;
 291                 }
 292         return false;
 293 }
 294
 295 /**
 296  * Enable the HD DACS
 297  *
 298  * @hda: pointer to HD analog structure
 299  * @enable: true if HD DACS need to be enabled, else false
 300  */
 301 static void hda_enable_hd_dacs(struct sti_hda *hda, bool enable)
 302 {
 303         u32 mask;
 304
 305         if (hda->video_dacs_ctrl) {
 306                 u32 val;
 307
 308                 switch ((u32)hda->video_dacs_ctrl & VIDEO_DACS_CONTROL_MASK) {
 309                 case VIDEO_DACS_CONTROL_SYSCFG2535:
 310                         mask = DAC_CFG_HD_OFF_MASK;
 311                         break;
 312                 case VIDEO_DACS_CONTROL_SYSCFG5072:
 313                         mask = DAC_CFG_HD_HZUVW_OFF_MASK;
 314                         break;
 315                 default:
 316                         DRM_INFO("Video DACS control register not supported!");
 317                         return;
 318                 }
 319
 320                 val = readl(hda->video_dacs_ctrl);
 321                 if (enable)
 322                         val &= ~mask;
 323                 else
 324                         val |= mask;
 325
 326                 writel(val, hda->video_dacs_ctrl);
 327         }
 328 }
 329
 330 #define DBGFS_DUMP(reg) seq_printf(s, "\n  %-25s 0x%08X", #reg, \
 331                                    readl(hda->regs + reg))
 332
 333 static void hda_dbg_cfg(struct seq_file *s, int val)
 334 {
 335         seq_puts(s, "\tAWG ");
 336         seq_puts(s, val & CFG_AWG_ASYNC_EN ? "enabled" : "disabled");
 337 }
 338
 339 static void hda_dbg_awg_microcode(struct seq_file *s, void __iomem *reg)
 340 {
 341         unsigned int i;
 342
 343         seq_puts(s, "\n\n");
 344         seq_puts(s, "  HDA AWG microcode:");
 345         for (i = 0; i < AWG_MAX_INST; i++) {
 346                 if (i % 8 == 0)
 347                         seq_printf(s, "\n  %04X:", i);
 348                 seq_printf(s, " %04X", readl(reg + i * 4));
 349         }
 350 }
 351
 352 static void hda_dbg_video_dacs_ctrl(struct seq_file *s, void __iomem *reg)
 353 {
 354         u32 val = readl(reg);
 355         u32 mask;
 356
 357         switch ((u32)reg & VIDEO_DACS_CONTROL_MASK) {
 358         case VIDEO_DACS_CONTROL_SYSCFG2535:
 359                 mask = DAC_CFG_HD_OFF_MASK;
 360                 break;
 361         case VIDEO_DACS_CONTROL_SYSCFG5072:
 362                 mask = DAC_CFG_HD_HZUVW_OFF_MASK;
 363                 break;
 364         default:
 365                 DRM_DEBUG_DRIVER("Warning: DACS ctrl register not supported!");
 366                 return;
 367         }
 368
 369         seq_puts(s, "\n");
 370         seq_printf(s, "\n  %-25s 0x%08X", "VIDEO_DACS_CONTROL", val);
 371         seq_puts(s, "\tHD DACs ");
 372         seq_puts(s, val & mask ? "disabled" : "enabled");
 373 }
 374
 375 static int hda_dbg_show(struct seq_file *s, void *data)
 376 {
 377         struct drm_info_node *node = s->private;
 378         struct sti_hda *hda = (struct sti_hda *)node->info_ent->data;
 379         struct drm_device *dev = node->minor->dev;
 380         int ret;
 381
 382         ret = mutex_lock_interruptible(&dev->struct_mutex);
 383         if (ret)
 384                 return ret;
 385
 386         seq_printf(s, "HD Analog: (vaddr = 0x%p)", hda->regs);
 387         DBGFS_DUMP(HDA_ANA_CFG);
 388         hda_dbg_cfg(s, readl(hda->regs + HDA_ANA_CFG));
 389         DBGFS_DUMP(HDA_ANA_SCALE_CTRL_Y);
 390         DBGFS_DUMP(HDA_ANA_SCALE_CTRL_CB);
 391         DBGFS_DUMP(HDA_ANA_SCALE_CTRL_CR);
 392         DBGFS_DUMP(HDA_ANA_ANC_CTRL);
 393         DBGFS_DUMP(HDA_ANA_SRC_Y_CFG);
 394         DBGFS_DUMP(HDA_ANA_SRC_C_CFG);
 395         hda_dbg_awg_microcode(s, hda->regs + HDA_SYNC_AWGI);
 396         if (hda->video_dacs_ctrl)
 397                 hda_dbg_video_dacs_ctrl(s, hda->video_dacs_ctrl);
 398         seq_puts(s, "\n");
 399
 400         mutex_unlock(&dev->struct_mutex);
 401         return 0;
 402 }
 403
 404 static struct drm_info_list hda_debugfs_files[] = {
 405         { "hda", hda_dbg_show, 0, NULL },
 406 };
 407
 408 static void hda_debugfs_exit(struct sti_hda *hda, struct drm_minor *minor)
 409 {
 410         drm_debugfs_remove_files(hda_debugfs_files,
 411                                  ARRAY_SIZE(hda_debugfs_files),
 412                                  minor);
 413 }
 414
 415 static int hda_debugfs_init(struct sti_hda *hda, struct drm_minor *minor)
 416 {
 417         unsigned int i;
 418
 419         for (i = 0; i < ARRAY_SIZE(hda_debugfs_files); i++)
 420                 hda_debugfs_files[i].data = hda;
 421
 422         return drm_debugfs_create_files(hda_debugfs_files,
 423                                         ARRAY_SIZE(hda_debugfs_files),
 424                                         minor->debugfs_root, minor);
 425 }
 426
 427 /**
 428  * Configure AWG, writing instructions
 429  *
 430  * @hda: pointer to HD analog structure
 431  * @awg_instr: pointer to AWG instructions table
 432  * @nb: nb of AWG instructions
 433  */
 434 static void sti_hda_configure_awg(struct sti_hda *hda, u32 *awg_instr, int nb)
 435 {
 436         unsigned int i;
 437
 438         DRM_DEBUG_DRIVER("\n");
 439
 440         for (i = 0; i < nb; i++)
 441                 hda_write(hda, awg_instr[i], HDA_SYNC_AWGI + i * 4);
 442         for (i = nb; i < AWG_MAX_INST; i++)
 443                 hda_write(hda, 0, HDA_SYNC_AWGI + i * 4);
 444 }
 445
 446 static void sti_hda_disable(struct drm_bridge *bridge)
 447 {
 448         struct sti_hda *hda = bridge->driver_private;
 449         u32 val;
 450
 451         if (!hda->enabled)
 452                 return;
 453
 454         DRM_DEBUG_DRIVER("\n");
 455
 456         /* Disable HD DAC and AWG */
 457         val = hda_read(hda, HDA_ANA_CFG);
 458         val &= ~CFG_AWG_ASYNC_EN;
 459         hda_write(hda, val, HDA_ANA_CFG);
 460         hda_write(hda, 0, HDA_ANA_ANC_CTRL);
 461
 462         hda_enable_hd_dacs(hda, false);
 463
 464         /* Disable/unprepare hda clock */
 465         clk_disable_unprepare(hda->clk_hddac);
 466         clk_disable_unprepare(hda->clk_pix);
 467
 468         hda->enabled = false;
 469 }
 470
 471 static void sti_hda_pre_enable(struct drm_bridge *bridge)
 472 {
 473         struct sti_hda *hda = bridge->driver_private;
 474         u32 val, i, mode_idx;
 475         u32 src_filter_y, src_filter_c;
 476         u32 *coef_y, *coef_c;
 477         u32 filter_mode;
 478
 479         DRM_DEBUG_DRIVER("\n");
 480
 481         if (hda->enabled)
 482                 return;
 483
 484         /* Prepare/enable clocks */
 485         if (clk_prepare_enable(hda->clk_pix))
 486                 DRM_ERROR("Failed to prepare/enable hda_pix clk\n");
 487         if (clk_prepare_enable(hda->clk_hddac))
 488                 DRM_ERROR("Failed to prepare/enable hda_hddac clk\n");
 489
 490         if (!hda_get_mode_idx(hda->mode, &mode_idx)) {
 491                 DRM_ERROR("Undefined mode\n");
 492                 return;
 493         }
 494
 495         switch (hda_supported_modes[mode_idx].vid_cat) {
 496         case VID_HD_148M:
 497                 DRM_ERROR("Beyond HD analog capabilities\n");
 498                 return;
 499         case VID_HD_74M:
 500                 /* HD use alternate 2x filter */
 501                 filter_mode = CFG_AWG_FLTR_MODE_HD;
 502                 src_filter_y = HDA_ANA_SRC_Y_CFG_ALT_2X;
 503                 src_filter_c = HDA_ANA_SRC_C_CFG_ALT_2X;
 504                 coef_y = coef_y_alt_2x;
 505                 coef_c = coef_c_alt_2x;
 506                 break;
 507         case VID_ED:
 508                 /* ED uses 4x filter */
 509                 filter_mode = CFG_AWG_FLTR_MODE_ED;
 510                 src_filter_y = HDA_ANA_SRC_Y_CFG_4X;
 511                 src_filter_c = HDA_ANA_SRC_C_CFG_4X;
 512                 coef_y = coef_yc_4x;
 513                 coef_c = coef_yc_4x;
 514                 break;
 515         case VID_SD:
 516                 DRM_ERROR("Not supported\n");
 517                 return;
 518         default:
 519                 DRM_ERROR("Undefined resolution\n");
 520                 return;
 521         }
 522         DRM_DEBUG_DRIVER("Using HDA mode #%d\n", mode_idx);
 523
 524         /* Enable HD Video DACs */
 525         hda_enable_hd_dacs(hda, true);
 526
 527         /* Configure scaler */
 528         hda_write(hda, SCALE_CTRL_Y_DFLT, HDA_ANA_SCALE_CTRL_Y);
 529         hda_write(hda, SCALE_CTRL_CB_DFLT, HDA_ANA_SCALE_CTRL_CB);
 530         hda_write(hda, SCALE_CTRL_CR_DFLT, HDA_ANA_SCALE_CTRL_CR);
 531
 532         /* Configure sampler */
 533         hda_write(hda , src_filter_y, HDA_ANA_SRC_Y_CFG);
 534         hda_write(hda, src_filter_c,  HDA_ANA_SRC_C_CFG);
 535         for (i = 0; i < SAMPLER_COEF_NB; i++) {
 536                 hda_write(hda, coef_y[i], HDA_COEFF_Y_PH1_TAP123 + i * 4);
 537                 hda_write(hda, coef_c[i], HDA_COEFF_C_PH1_TAP123 + i * 4);
 538         }
 539
 540         /* Configure main HDFormatter */
 541         val = 0;
 542         val |= (hda->mode.flags & DRM_MODE_FLAG_INTERLACE) ?
 543             0 : CFG_AWG_ASYNC_VSYNC_MTD;
 544         val |= (CFG_PBPR_SYNC_OFF_VAL << CFG_PBPR_SYNC_OFF_SHIFT);
 545         val |= filter_mode;
 546         hda_write(hda, val, HDA_ANA_CFG);
 547
 548         /* Configure AWG */
 549         sti_hda_configure_awg(hda, hda_supported_modes[mode_idx].awg_instr,
 550                               hda_supported_modes[mode_idx].nb_instr);
 551
 552         /* Enable AWG */
 553         val = hda_read(hda, HDA_ANA_CFG);
 554         val |= CFG_AWG_ASYNC_EN;
 555         hda_write(hda, val, HDA_ANA_CFG);
 556
 557         hda->enabled = true;
 558 }
 559
 560 static void sti_hda_set_mode(struct drm_bridge *bridge,
 561                 struct drm_display_mode *mode,
 562                 struct drm_display_mode *adjusted_mode)
 563 {
 564         struct sti_hda *hda = bridge->driver_private;
 565         u32 mode_idx;
 566         int hddac_rate;
 567         int ret;
 568
 569         DRM_DEBUG_DRIVER("\n");
 570
 571         memcpy(&hda->mode, mode, sizeof(struct drm_display_mode));
 572
 573         if (!hda_get_mode_idx(hda->mode, &mode_idx)) {
 574                 DRM_ERROR("Undefined mode\n");
 575                 return;
 576         }
 577
 578         switch (hda_supported_modes[mode_idx].vid_cat) {
 579         case VID_HD_74M:
 580                 /* HD use alternate 2x filter */
 581                 hddac_rate = mode->clock * 1000 * 2;
 582                 break;
 583         case VID_ED:
 584                 /* ED uses 4x filter */
 585                 hddac_rate = mode->clock * 1000 * 4;
 586                 break;
 587         default:
 588                 DRM_ERROR("Undefined mode\n");
 589                 return;
 590         }
 591
 592         /* HD DAC = 148.5Mhz or 108 Mhz */
 593         ret = clk_set_rate(hda->clk_hddac, hddac_rate);
 594         if (ret < 0)
 595                 DRM_ERROR("Cannot set rate (%dHz) for hda_hddac clk\n",
 596                           hddac_rate);
 597
 598         /* HDformatter clock = compositor clock */
 599         ret = clk_set_rate(hda->clk_pix, mode->clock * 1000);
 600         if (ret < 0)
 601                 DRM_ERROR("Cannot set rate (%dHz) for hda_pix clk\n",
 602                           mode->clock * 1000);
 603 }
 604
 605 static void sti_hda_bridge_nope(struct drm_bridge *bridge)
 606 {
 607         /* do nothing */
 608 }
 609
 610 static const struct drm_bridge_funcs sti_hda_bridge_funcs = {
 611         .pre_enable = sti_hda_pre_enable,
 612         .enable = sti_hda_bridge_nope,
 613         .disable = sti_hda_disable,
 614         .post_disable = sti_hda_bridge_nope,
 615         .mode_set = sti_hda_set_mode,
 616 };
 617
 618 static int sti_hda_connector_get_modes(struct drm_connector *connector)
 619 {
 620         unsigned int i;
 621         int count = 0;
 622         struct sti_hda_connector *hda_connector
 623                 = to_sti_hda_connector(connector);
 624         struct sti_hda *hda = hda_connector->hda;
 625
 626         DRM_DEBUG_DRIVER("\n");
 627
 628         for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++) {
 629                 struct drm_display_mode *mode =
 630                         drm_mode_duplicate(hda->drm_dev,
 631                                         &hda_supported_modes[i].mode);
 632                 if (!mode)
 633                         continue;
 634                 mode->vrefresh = drm_mode_vrefresh(mode);
 635
 636                 /* the first mode is the preferred mode */
 637                 if (i == 0)
 638                         mode->type |= DRM_MODE_TYPE_PREFERRED;
 639
 640                 drm_mode_probed_add(connector, mode);
 641                 count++;
 642         }
 643
 644         return count;
 645 }
 646
 647 #define CLK_TOLERANCE_HZ 50
 648
 649 static int sti_hda_connector_mode_valid(struct drm_connector *connector,
 650                                         struct drm_display_mode *mode)
 651 {
 652         int target = mode->clock * 1000;
 653         int target_min = target - CLK_TOLERANCE_HZ;
 654         int target_max = target + CLK_TOLERANCE_HZ;
 655         int result;
 656         int idx;
 657         struct sti_hda_connector *hda_connector
 658                 = to_sti_hda_connector(connector);
 659         struct sti_hda *hda = hda_connector->hda;
 660
 661         if (!hda_get_mode_idx(*mode, &idx)) {
 662                 return MODE_BAD;
 663         } else {
 664                 result = clk_round_rate(hda->clk_pix, target);
 665
 666                 DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
 667                                  target, result);
 668
 669                 if ((result < target_min) || (result > target_max)) {
 670                         DRM_DEBUG_DRIVER("hda pixclk=%d not supported\n",
 671                                          target);
 672                         return MODE_BAD;
 673                 }
 674         }
 675
 676         return MODE_OK;
 677 }
 678
 679 struct drm_encoder *sti_hda_best_encoder(struct drm_connector *connector)
 680 {
 681         struct sti_hda_connector *hda_connector
 682                 = to_sti_hda_connector(connector);
 683
 684         /* Best encoder is the one associated during connector creation */
 685         return hda_connector->encoder;
 686 }
 687
 688 static const
 689 struct drm_connector_helper_funcs sti_hda_connector_helper_funcs = {
 690         .get_modes = sti_hda_connector_get_modes,
 691         .mode_valid = sti_hda_connector_mode_valid,
 692         .best_encoder = sti_hda_best_encoder,
 693 };
 694
 695 static enum drm_connector_status
 696 sti_hda_connector_detect(struct drm_connector *connector, bool force)
 697 {
 698         return connector_status_connected;
 699 }
 700
 701 static void sti_hda_connector_destroy(struct drm_connector *connector)
 702 {
 703         struct sti_hda_connector *hda_connector
 704                 = to_sti_hda_connector(connector);
 705
 706         drm_connector_unregister(connector);
 707         drm_connector_cleanup(connector);
 708         kfree(hda_connector);
 709 }
 710
 711 static const struct drm_connector_funcs sti_hda_connector_funcs = {
 712         .dpms = drm_atomic_helper_connector_dpms,
 713         .fill_modes = drm_helper_probe_single_connector_modes,
 714         .detect = sti_hda_connector_detect,
 715         .destroy = sti_hda_connector_destroy,
 716         .reset = drm_atomic_helper_connector_reset,
 717         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 718         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 719 };
 720
 721 static struct drm_encoder *sti_hda_find_encoder(struct drm_device *dev)
 722 {
 723         struct drm_encoder *encoder;
 724
 725         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 726                 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC)
 727                         return encoder;
 728         }
 729
 730         return NULL;
 731 }
 732
 733 static int sti_hda_bind(struct device *dev, struct device *master, void *data)
 734 {
 735         struct sti_hda *hda = dev_get_drvdata(dev);
 736         struct drm_device *drm_dev = data;
 737         struct drm_encoder *encoder;
 738         struct sti_hda_connector *connector;
 739         struct drm_connector *drm_connector;
 740         struct drm_bridge *bridge;
 741         int err;
 742
 743         /* Set the drm device handle */
 744         hda->drm_dev = drm_dev;
 745
 746         encoder = sti_hda_find_encoder(drm_dev);
 747         if (!encoder)
 748                 return -ENOMEM;
 749
 750         connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL);
 751         if (!connector)
 752                 return -ENOMEM;
 753
 754         connector->hda = hda;
 755
 756                 bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
 757         if (!bridge)
 758                 return -ENOMEM;
 759
 760         bridge->driver_private = hda;
 761         bridge->funcs = &sti_hda_bridge_funcs;
 762         drm_bridge_attach(drm_dev, bridge);
 763
 764         encoder->bridge = bridge;
 765         connector->encoder = encoder;
 766
 767         drm_connector = (struct drm_connector *)connector;
 768
 769         drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
 770
 771         drm_connector_init(drm_dev, drm_connector,
 772                         &sti_hda_connector_funcs, DRM_MODE_CONNECTOR_Component);
 773         drm_connector_helper_add(drm_connector,
 774                         &sti_hda_connector_helper_funcs);
 775
 776         err = drm_connector_register(drm_connector);
 777         if (err)
 778                 goto err_connector;
 779
 780         err = drm_mode_connector_attach_encoder(drm_connector, encoder);
 781         if (err) {
 782                 DRM_ERROR("Failed to attach a connector to a encoder\n");
 783                 goto err_sysfs;
 784         }
 785
 786         /* force to disable hd dacs at startup */
 787         hda_enable_hd_dacs(hda, false);
 788
 789         if (hda_debugfs_init(hda, drm_dev->primary))
 790                 DRM_ERROR("HDA debugfs setup failed\n");
 791
 792         return 0;
 793
 794 err_sysfs:
 795         drm_connector_unregister(drm_connector);
 796 err_connector:
 797         drm_connector_cleanup(drm_connector);
 798         return -EINVAL;
 799 }
 800
 801 static void sti_hda_unbind(struct device *dev,
 802                 struct device *master, void *data)
 803 {
 804         struct sti_hda *hda = dev_get_drvdata(dev);
 805         struct drm_device *drm_dev = data;
 806
 807         hda_debugfs_exit(hda, drm_dev->primary);
 808 }
 809
 810 static const struct component_ops sti_hda_ops = {
 811         .bind = sti_hda_bind,
 812         .unbind = sti_hda_unbind,
 813 };
 814
 815 static int sti_hda_probe(struct platform_device *pdev)
 816 {
 817         struct device *dev = &pdev->dev;
 818         struct sti_hda *hda;
 819         struct resource *res;
 820
 821         DRM_INFO("%s\n", __func__);
 822
 823         hda = devm_kzalloc(dev, sizeof(*hda), GFP_KERNEL);
 824         if (!hda)
 825                 return -ENOMEM;
 826
 827         hda->dev = pdev->dev;
 828
 829         /* Get resources */
 830         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hda-reg");
 831         if (!res) {
 832                 DRM_ERROR("Invalid hda resource\n");
 833                 return -ENOMEM;
 834         }
 835         hda->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
 836         if (!hda->regs)
 837                 return -ENOMEM;
 838
 839         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 840                         "video-dacs-ctrl");
 841         if (res) {
 842                 hda->video_dacs_ctrl = devm_ioremap_nocache(dev, res->start,
 843                                 resource_size(res));
 844                 if (!hda->video_dacs_ctrl)
 845                         return -ENOMEM;
 846         } else {
 847                 /* If no existing video-dacs-ctrl resource continue the probe */
 848                 DRM_DEBUG_DRIVER("No video-dacs-ctrl resource\n");
 849                 hda->video_dacs_ctrl = NULL;
 850         }
 851
 852         /* Get clock resources */
 853         hda->clk_pix = devm_clk_get(dev, "pix");
 854         if (IS_ERR(hda->clk_pix)) {
 855                 DRM_ERROR("Cannot get hda_pix clock\n");
 856                 return PTR_ERR(hda->clk_pix);
 857         }
 858
 859         hda->clk_hddac = devm_clk_get(dev, "hddac");
 860         if (IS_ERR(hda->clk_hddac)) {
 861                 DRM_ERROR("Cannot get hda_hddac clock\n");
 862                 return PTR_ERR(hda->clk_hddac);
 863         }
 864
 865         platform_set_drvdata(pdev, hda);
 866
 867         return component_add(&pdev->dev, &sti_hda_ops);
 868 }
 869
 870 static int sti_hda_remove(struct platform_device *pdev)
 871 {
 872         component_del(&pdev->dev, &sti_hda_ops);
 873         return 0;
 874 }
 875
 876 static const struct of_device_id hda_of_match[] = {
 877         { .compatible = "st,stih416-hda", },
 878         { .compatible = "st,stih407-hda", },
 879         { /* end node */ }
 880 };
 881 MODULE_DEVICE_TABLE(of, hda_of_match);
 882
 883 struct platform_driver sti_hda_driver = {
 884         .driver = {
 885                 .name = "sti-hda",
 886                 .owner = THIS_MODULE,
 887                 .of_match_table = hda_of_match,
 888         },
 889         .probe = sti_hda_probe,
 890         .remove = sti_hda_remove,
 891 };
 892
 893 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
 894 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
 895 MODULE_LICENSE("GPL");