2 * Copyright (C) STMicroelectronics SA 2014
3 * Authors: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
4 * License terms: GNU General Public License (GPL), version 2
7 #include <linux/component.h>
8 #include <linux/firmware.h>
9 #include <linux/reset.h>
11 #include <drm/drm_atomic.h>
12 #include <drm/drm_fb_cma_helper.h>
13 #include <drm/drm_gem_cma_helper.h>
15 #include "sti_compositor.h"
16 #include "sti_hqvdp_lut.h"
17 #include "sti_plane.h"
21 #define HQVDP_FMW_NAME "hqvdp-stih407.bin"
24 #define HQVDP_DMEM 0x00000000 /* 0x00000000 */
25 #define HQVDP_PMEM 0x00040000 /* 0x00040000 */
26 #define HQVDP_RD_PLUG 0x000E0000 /* 0x000E0000 */
27 #define HQVDP_RD_PLUG_CONTROL (HQVDP_RD_PLUG + 0x1000) /* 0x000E1000 */
28 #define HQVDP_RD_PLUG_PAGE_SIZE (HQVDP_RD_PLUG + 0x1004) /* 0x000E1004 */
29 #define HQVDP_RD_PLUG_MIN_OPC (HQVDP_RD_PLUG + 0x1008) /* 0x000E1008 */
30 #define HQVDP_RD_PLUG_MAX_OPC (HQVDP_RD_PLUG + 0x100C) /* 0x000E100C */
31 #define HQVDP_RD_PLUG_MAX_CHK (HQVDP_RD_PLUG + 0x1010) /* 0x000E1010 */
32 #define HQVDP_RD_PLUG_MAX_MSG (HQVDP_RD_PLUG + 0x1014) /* 0x000E1014 */
33 #define HQVDP_RD_PLUG_MIN_SPACE (HQVDP_RD_PLUG + 0x1018) /* 0x000E1018 */
34 #define HQVDP_WR_PLUG 0x000E2000 /* 0x000E2000 */
35 #define HQVDP_WR_PLUG_CONTROL (HQVDP_WR_PLUG + 0x1000) /* 0x000E3000 */
36 #define HQVDP_WR_PLUG_PAGE_SIZE (HQVDP_WR_PLUG + 0x1004) /* 0x000E3004 */
37 #define HQVDP_WR_PLUG_MIN_OPC (HQVDP_WR_PLUG + 0x1008) /* 0x000E3008 */
38 #define HQVDP_WR_PLUG_MAX_OPC (HQVDP_WR_PLUG + 0x100C) /* 0x000E300C */
39 #define HQVDP_WR_PLUG_MAX_CHK (HQVDP_WR_PLUG + 0x1010) /* 0x000E3010 */
40 #define HQVDP_WR_PLUG_MAX_MSG (HQVDP_WR_PLUG + 0x1014) /* 0x000E3014 */
41 #define HQVDP_WR_PLUG_MIN_SPACE (HQVDP_WR_PLUG + 0x1018) /* 0x000E3018 */
42 #define HQVDP_MBX 0x000E4000 /* 0x000E4000 */
43 #define HQVDP_MBX_IRQ_TO_XP70 (HQVDP_MBX + 0x0000) /* 0x000E4000 */
44 #define HQVDP_MBX_INFO_HOST (HQVDP_MBX + 0x0004) /* 0x000E4004 */
45 #define HQVDP_MBX_IRQ_TO_HOST (HQVDP_MBX + 0x0008) /* 0x000E4008 */
46 #define HQVDP_MBX_INFO_XP70 (HQVDP_MBX + 0x000C) /* 0x000E400C */
47 #define HQVDP_MBX_SW_RESET_CTRL (HQVDP_MBX + 0x0010) /* 0x000E4010 */
48 #define HQVDP_MBX_STARTUP_CTRL1 (HQVDP_MBX + 0x0014) /* 0x000E4014 */
49 #define HQVDP_MBX_STARTUP_CTRL2 (HQVDP_MBX + 0x0018) /* 0x000E4018 */
50 #define HQVDP_MBX_GP_STATUS (HQVDP_MBX + 0x001C) /* 0x000E401C */
51 #define HQVDP_MBX_NEXT_CMD (HQVDP_MBX + 0x0020) /* 0x000E4020 */
52 #define HQVDP_MBX_CURRENT_CMD (HQVDP_MBX + 0x0024) /* 0x000E4024 */
53 #define HQVDP_MBX_SOFT_VSYNC (HQVDP_MBX + 0x0028) /* 0x000E4028 */
56 #define PLUG_CONTROL_ENABLE 0x00000001
57 #define PLUG_PAGE_SIZE_256 0x00000002
58 #define PLUG_MIN_OPC_8 0x00000003
59 #define PLUG_MAX_OPC_64 0x00000006
60 #define PLUG_MAX_CHK_2X 0x00000001
61 #define PLUG_MAX_MSG_1X 0x00000000
62 #define PLUG_MIN_SPACE_1 0x00000000
65 #define SW_RESET_CTRL_FULL BIT(0)
66 #define SW_RESET_CTRL_CORE BIT(1)
69 #define STARTUP_CTRL1_RST_DONE BIT(0)
70 #define STARTUP_CTRL1_AUTH_IDLE BIT(2)
73 #define STARTUP_CTRL2_FETCH_EN BIT(1)
76 #define INFO_XP70_FW_READY BIT(15)
77 #define INFO_XP70_FW_PROCESSING BIT(14)
78 #define INFO_XP70_FW_INITQUEUES BIT(13)
81 #define SOFT_VSYNC_HW 0x00000000
82 #define SOFT_VSYNC_SW_CMD 0x00000001
83 #define SOFT_VSYNC_SW_CTRL_IRQ 0x00000003
85 /* Reset & boot poll config */
86 #define POLL_MAX_ATTEMPT 50
87 #define POLL_DELAY_MS 20
89 #define SCALE_FACTOR 8192
90 #define SCALE_MAX_FOR_LEG_LUT_F 4096
91 #define SCALE_MAX_FOR_LEG_LUT_E 4915
92 #define SCALE_MAX_FOR_LEG_LUT_D 6654
93 #define SCALE_MAX_FOR_LEG_LUT_C 8192
95 enum sti_hvsrc_orient
{
100 /* Command structures */
101 struct sti_hqvdp_top
{
105 u32 current_enh_luma
;
106 u32 current_right_luma
;
107 u32 current_enh_right_luma
;
109 u32 current_enh_chroma
;
110 u32 current_right_chroma
;
111 u32 current_enh_right_chroma
;
115 u32 luma_enh_src_pitch
;
116 u32 luma_right_src_pitch
;
117 u32 luma_enh_right_src_pitch
;
118 u32 chroma_src_pitch
;
119 u32 chroma_enh_src_pitch
;
120 u32 chroma_right_src_pitch
;
121 u32 chroma_enh_right_src_pitch
;
122 u32 luma_processed_pitch
;
123 u32 chroma_processed_pitch
;
124 u32 input_frame_size
;
125 u32 input_viewport_ori
;
126 u32 input_viewport_ori_right
;
127 u32 input_viewport_size
;
128 u32 left_view_border_width
;
129 u32 right_view_border_width
;
130 u32 left_view_3d_offset_width
;
131 u32 right_view_3d_offset_width
;
132 u32 side_stripe_color
;
136 /* Configs for interlaced : no IT, no pass thru, 3 fields */
137 #define TOP_CONFIG_INTER_BTM 0x00000000
138 #define TOP_CONFIG_INTER_TOP 0x00000002
140 /* Config for progressive : no IT, no pass thru, 3 fields */
141 #define TOP_CONFIG_PROGRESSIVE 0x00000001
143 /* Default MemFormat: in=420_raster_dual out=444_raster;opaque Mem2Tv mode */
144 #define TOP_MEM_FORMAT_DFLT 0x00018060
147 #define MAX_WIDTH 0x1FFF
148 #define MAX_HEIGHT 0x0FFF
149 #define MIN_WIDTH 0x0030
150 #define MIN_HEIGHT 0x0010
152 struct sti_hqvdp_vc1re
{
160 struct sti_hqvdp_fmd
{
165 u32 next_next_right_luma
;
166 u32 next_next_next_luma
;
167 u32 next_next_next_right_luma
;
174 struct sti_hqvdp_csdi
{
181 u32 prev_enh_right_luma
;
185 u32 next_enh_right_luma
;
188 u32 prev_right_chroma
;
189 u32 prev_enh_right_chroma
;
192 u32 next_right_chroma
;
193 u32 next_enh_right_chroma
;
195 u32 prev_right_motion
;
197 u32 cur_right_motion
;
199 u32 next_right_motion
;
202 /* Config for progressive: by pass */
203 #define CSDI_CONFIG_PROG 0x00000000
204 /* Config for directional deinterlacing without motion */
205 #define CSDI_CONFIG_INTER_DIR 0x00000016
206 /* Additional configs for fader, blender, motion,... deinterlace algorithms */
207 #define CSDI_CONFIG2_DFLT 0x000001B3
208 #define CSDI_DCDI_CONFIG_DFLT 0x00203803
210 struct sti_hqvdp_hvsrc
{
211 u32 hor_panoramic_ctrl
;
212 u32 output_picture_size
;
216 u32 yh_coef
[NB_COEF
];
217 u32 ch_coef
[NB_COEF
];
218 u32 yv_coef
[NB_COEF
];
219 u32 cv_coef
[NB_COEF
];
224 /* Default ParamCtrl: all controls enabled */
225 #define HVSRC_PARAM_CTRL_DFLT 0xFFFFFFFF
227 struct sti_hqvdp_iqi
{
246 /* Default Config : IQI bypassed */
247 #define IQI_CONFIG_DFLT 0x00000001
248 /* Default Contrast & Brightness gain = 256 */
249 #define IQI_CON_BRI_DFLT 0x00000100
250 /* Default Saturation gain = 256 */
251 #define IQI_SAT_GAIN_DFLT 0x00000100
252 /* Default PxfConf : P2I bypassed */
253 #define IQI_PXF_CONF_DFLT 0x00000001
255 struct sti_hqvdp_top_status
{
261 struct sti_hqvdp_fmd_status
{
262 u32 fmd_repeat_move_status
;
263 u32 fmd_scene_count_status
;
267 u32 next_next_y_fmd_crc
;
268 u32 next_next_next_y_fmd_crc
;
271 struct sti_hqvdp_csdi_status
{
275 u32 prev_uv_csdi_crc
;
277 u32 next_uv_csdi_crc
;
282 u32 mot_cur_csdi_crc
;
283 u32 mot_prev_csdi_crc
;
286 struct sti_hqvdp_hvsrc_status
{
292 struct sti_hqvdp_iqi_status
{
299 /* Main commands. We use 2 commands one being processed by the firmware, one
300 * ready to be fetched upon next Vsync*/
303 struct sti_hqvdp_cmd
{
304 struct sti_hqvdp_top top
;
305 struct sti_hqvdp_vc1re vc1re
;
306 struct sti_hqvdp_fmd fmd
;
307 struct sti_hqvdp_csdi csdi
;
308 struct sti_hqvdp_hvsrc hvsrc
;
309 struct sti_hqvdp_iqi iqi
;
310 struct sti_hqvdp_top_status top_status
;
311 struct sti_hqvdp_fmd_status fmd_status
;
312 struct sti_hqvdp_csdi_status csdi_status
;
313 struct sti_hqvdp_hvsrc_status hvsrc_status
;
314 struct sti_hqvdp_iqi_status iqi_status
;
318 * STI HQVDP structure
320 * @dev: driver device
321 * @drm_dev: the drm device
323 * @plane: plane structure for hqvdp it self
325 * @clk_pix_main: pix main clock
326 * @reset: reset control
327 * @vtg_nb: notifier to handle VTG Vsync
328 * @btm_field_pending: is there any bottom field (interlaced frame) to display
329 * @hqvdp_cmd: buffer of commands
330 * @hqvdp_cmd_paddr: physical address of hqvdp_cmd
331 * @vtg: vtg for main data path
332 * @xp70_initialized: true if xp70 is already initialized
336 struct drm_device
*drm_dev
;
338 struct sti_plane plane
;
340 struct clk
*clk_pix_main
;
341 struct reset_control
*reset
;
342 struct notifier_block vtg_nb
;
343 bool btm_field_pending
;
347 bool xp70_initialized
;
350 #define to_sti_hqvdp(x) container_of(x, struct sti_hqvdp, plane)
352 static const uint32_t hqvdp_supported_formats
[] = {
357 * sti_hqvdp_get_free_cmd
358 * @hqvdp: hqvdp structure
360 * Look for a hqvdp_cmd that is not being used (or about to be used) by the FW.
363 * the offset of the command to be used.
366 static int sti_hqvdp_get_free_cmd(struct sti_hqvdp
*hqvdp
)
368 u32 curr_cmd
, next_cmd
;
369 u32 cmd
= hqvdp
->hqvdp_cmd_paddr
;
372 curr_cmd
= readl(hqvdp
->regs
+ HQVDP_MBX_CURRENT_CMD
);
373 next_cmd
= readl(hqvdp
->regs
+ HQVDP_MBX_NEXT_CMD
);
375 for (i
= 0; i
< NB_VDP_CMD
; i
++) {
376 if ((cmd
!= curr_cmd
) && (cmd
!= next_cmd
))
377 return i
* sizeof(struct sti_hqvdp_cmd
);
378 cmd
+= sizeof(struct sti_hqvdp_cmd
);
385 * sti_hqvdp_get_curr_cmd
386 * @hqvdp: hqvdp structure
388 * Look for the hqvdp_cmd that is being used by the FW.
391 * the offset of the command to be used.
394 static int sti_hqvdp_get_curr_cmd(struct sti_hqvdp
*hqvdp
)
397 u32 cmd
= hqvdp
->hqvdp_cmd_paddr
;
400 curr_cmd
= readl(hqvdp
->regs
+ HQVDP_MBX_CURRENT_CMD
);
402 for (i
= 0; i
< NB_VDP_CMD
; i
++) {
404 return i
* sizeof(struct sti_hqvdp_cmd
);
406 cmd
+= sizeof(struct sti_hqvdp_cmd
);
413 * sti_hqvdp_get_next_cmd
414 * @hqvdp: hqvdp structure
416 * Look for the next hqvdp_cmd that will be used by the FW.
419 * the offset of the next command that will be used.
422 static int sti_hqvdp_get_next_cmd(struct sti_hqvdp
*hqvdp
)
425 dma_addr_t cmd
= hqvdp
->hqvdp_cmd_paddr
;
428 next_cmd
= readl(hqvdp
->regs
+ HQVDP_MBX_NEXT_CMD
);
430 for (i
= 0; i
< NB_VDP_CMD
; i
++) {
432 return i
* sizeof(struct sti_hqvdp_cmd
);
434 cmd
+= sizeof(struct sti_hqvdp_cmd
);
440 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \
441 readl(hqvdp->regs + reg))
443 static const char *hqvdp_dbg_get_lut(u32
*coef
)
445 if (!memcmp(coef
, coef_lut_a_legacy
, 16))
447 if (!memcmp(coef
, coef_lut_b
, 16))
449 if (!memcmp(coef
, coef_lut_c_y_legacy
, 16))
451 if (!memcmp(coef
, coef_lut_c_c_legacy
, 16))
453 if (!memcmp(coef
, coef_lut_d_y_legacy
, 16))
455 if (!memcmp(coef
, coef_lut_d_c_legacy
, 16))
457 if (!memcmp(coef
, coef_lut_e_y_legacy
, 16))
459 if (!memcmp(coef
, coef_lut_e_c_legacy
, 16))
461 if (!memcmp(coef
, coef_lut_f_y_legacy
, 16))
463 if (!memcmp(coef
, coef_lut_f_c_legacy
, 16))
468 static void hqvdp_dbg_dump_cmd(struct seq_file
*s
, struct sti_hqvdp_cmd
*c
)
470 int src_w
, src_h
, dst_w
, dst_h
;
472 seq_puts(s
, "\n\tTOP:");
473 seq_printf(s
, "\n\t %-20s 0x%08X", "Config", c
->top
.config
);
474 switch (c
->top
.config
) {
475 case TOP_CONFIG_PROGRESSIVE
:
476 seq_puts(s
, "\tProgressive");
478 case TOP_CONFIG_INTER_TOP
:
479 seq_puts(s
, "\tInterlaced, top field");
481 case TOP_CONFIG_INTER_BTM
:
482 seq_puts(s
, "\tInterlaced, bottom field");
485 seq_puts(s
, "\t<UNKNOWN>");
489 seq_printf(s
, "\n\t %-20s 0x%08X", "MemFormat", c
->top
.mem_format
);
490 seq_printf(s
, "\n\t %-20s 0x%08X", "CurrentY", c
->top
.current_luma
);
491 seq_printf(s
, "\n\t %-20s 0x%08X", "CurrentC", c
->top
.current_chroma
);
492 seq_printf(s
, "\n\t %-20s 0x%08X", "YSrcPitch", c
->top
.luma_src_pitch
);
493 seq_printf(s
, "\n\t %-20s 0x%08X", "CSrcPitch",
494 c
->top
.chroma_src_pitch
);
495 seq_printf(s
, "\n\t %-20s 0x%08X", "InputFrameSize",
496 c
->top
.input_frame_size
);
497 seq_printf(s
, "\t%dx%d",
498 c
->top
.input_frame_size
& 0x0000FFFF,
499 c
->top
.input_frame_size
>> 16);
500 seq_printf(s
, "\n\t %-20s 0x%08X", "InputViewportSize",
501 c
->top
.input_viewport_size
);
502 src_w
= c
->top
.input_viewport_size
& 0x0000FFFF;
503 src_h
= c
->top
.input_viewport_size
>> 16;
504 seq_printf(s
, "\t%dx%d", src_w
, src_h
);
506 seq_puts(s
, "\n\tHVSRC:");
507 seq_printf(s
, "\n\t %-20s 0x%08X", "OutputPictureSize",
508 c
->hvsrc
.output_picture_size
);
509 dst_w
= c
->hvsrc
.output_picture_size
& 0x0000FFFF;
510 dst_h
= c
->hvsrc
.output_picture_size
>> 16;
511 seq_printf(s
, "\t%dx%d", dst_w
, dst_h
);
512 seq_printf(s
, "\n\t %-20s 0x%08X", "ParamCtrl", c
->hvsrc
.param_ctrl
);
514 seq_printf(s
, "\n\t %-20s %s", "yh_coef",
515 hqvdp_dbg_get_lut(c
->hvsrc
.yh_coef
));
516 seq_printf(s
, "\n\t %-20s %s", "ch_coef",
517 hqvdp_dbg_get_lut(c
->hvsrc
.ch_coef
));
518 seq_printf(s
, "\n\t %-20s %s", "yv_coef",
519 hqvdp_dbg_get_lut(c
->hvsrc
.yv_coef
));
520 seq_printf(s
, "\n\t %-20s %s", "cv_coef",
521 hqvdp_dbg_get_lut(c
->hvsrc
.cv_coef
));
523 seq_printf(s
, "\n\t %-20s", "ScaleH");
525 seq_printf(s
, " %d/1", dst_w
/ src_w
);
527 seq_printf(s
, " 1/%d", src_w
/ dst_w
);
529 seq_printf(s
, "\n\t %-20s", "tScaleV");
531 seq_printf(s
, " %d/1", dst_h
/ src_h
);
533 seq_printf(s
, " 1/%d", src_h
/ dst_h
);
535 seq_puts(s
, "\n\tCSDI:");
536 seq_printf(s
, "\n\t %-20s 0x%08X\t", "Config", c
->csdi
.config
);
537 switch (c
->csdi
.config
) {
538 case CSDI_CONFIG_PROG
:
539 seq_puts(s
, "Bypass");
541 case CSDI_CONFIG_INTER_DIR
:
542 seq_puts(s
, "Deinterlace, directional");
545 seq_puts(s
, "<UNKNOWN>");
549 seq_printf(s
, "\n\t %-20s 0x%08X", "Config2", c
->csdi
.config2
);
550 seq_printf(s
, "\n\t %-20s 0x%08X", "DcdiConfig", c
->csdi
.dcdi_config
);
553 static int hqvdp_dbg_show(struct seq_file
*s
, void *data
)
555 struct drm_info_node
*node
= s
->private;
556 struct sti_hqvdp
*hqvdp
= (struct sti_hqvdp
*)node
->info_ent
->data
;
557 struct drm_device
*dev
= node
->minor
->dev
;
558 int cmd
, cmd_offset
, infoxp70
;
562 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
566 seq_printf(s
, "%s: (vaddr = 0x%p)",
567 sti_plane_to_str(&hqvdp
->plane
), hqvdp
->regs
);
569 DBGFS_DUMP(HQVDP_MBX_IRQ_TO_XP70
);
570 DBGFS_DUMP(HQVDP_MBX_INFO_HOST
);
571 DBGFS_DUMP(HQVDP_MBX_IRQ_TO_HOST
);
572 DBGFS_DUMP(HQVDP_MBX_INFO_XP70
);
573 infoxp70
= readl(hqvdp
->regs
+ HQVDP_MBX_INFO_XP70
);
574 seq_puts(s
, "\tFirmware state: ");
575 if (infoxp70
& INFO_XP70_FW_READY
)
576 seq_puts(s
, "idle and ready");
577 else if (infoxp70
& INFO_XP70_FW_PROCESSING
)
578 seq_puts(s
, "processing a picture");
579 else if (infoxp70
& INFO_XP70_FW_INITQUEUES
)
580 seq_puts(s
, "programming queues");
582 seq_puts(s
, "NOT READY");
584 DBGFS_DUMP(HQVDP_MBX_SW_RESET_CTRL
);
585 DBGFS_DUMP(HQVDP_MBX_STARTUP_CTRL1
);
586 if (readl(hqvdp
->regs
+ HQVDP_MBX_STARTUP_CTRL1
)
587 & STARTUP_CTRL1_RST_DONE
)
588 seq_puts(s
, "\tReset is done");
590 seq_puts(s
, "\tReset is NOT done");
591 DBGFS_DUMP(HQVDP_MBX_STARTUP_CTRL2
);
592 if (readl(hqvdp
->regs
+ HQVDP_MBX_STARTUP_CTRL2
)
593 & STARTUP_CTRL2_FETCH_EN
)
594 seq_puts(s
, "\tFetch is enabled");
596 seq_puts(s
, "\tFetch is NOT enabled");
597 DBGFS_DUMP(HQVDP_MBX_GP_STATUS
);
598 DBGFS_DUMP(HQVDP_MBX_NEXT_CMD
);
599 DBGFS_DUMP(HQVDP_MBX_CURRENT_CMD
);
600 DBGFS_DUMP(HQVDP_MBX_SOFT_VSYNC
);
601 if (!(readl(hqvdp
->regs
+ HQVDP_MBX_SOFT_VSYNC
) & 3))
602 seq_puts(s
, "\tHW Vsync");
604 seq_puts(s
, "\tSW Vsync ?!?!");
607 cmd
= readl(hqvdp
->regs
+ HQVDP_MBX_CURRENT_CMD
);
608 cmd_offset
= sti_hqvdp_get_curr_cmd(hqvdp
);
609 if (cmd_offset
== -1) {
610 seq_puts(s
, "\n\n Last command: unknown");
612 virt
= hqvdp
->hqvdp_cmd
+ cmd_offset
;
613 seq_printf(s
, "\n\n Last command: address @ 0x%x (0x%p)",
615 hqvdp_dbg_dump_cmd(s
, (struct sti_hqvdp_cmd
*)virt
);
619 cmd
= readl(hqvdp
->regs
+ HQVDP_MBX_NEXT_CMD
);
620 cmd_offset
= sti_hqvdp_get_next_cmd(hqvdp
);
621 if (cmd_offset
== -1) {
622 seq_puts(s
, "\n\n Next command: unknown");
624 virt
= hqvdp
->hqvdp_cmd
+ cmd_offset
;
625 seq_printf(s
, "\n\n Next command address: @ 0x%x (0x%p)",
627 hqvdp_dbg_dump_cmd(s
, (struct sti_hqvdp_cmd
*)virt
);
632 mutex_unlock(&dev
->struct_mutex
);
636 static struct drm_info_list hqvdp_debugfs_files
[] = {
637 { "hqvdp", hqvdp_dbg_show
, 0, NULL
},
640 static int hqvdp_debugfs_init(struct sti_hqvdp
*hqvdp
, struct drm_minor
*minor
)
644 for (i
= 0; i
< ARRAY_SIZE(hqvdp_debugfs_files
); i
++)
645 hqvdp_debugfs_files
[i
].data
= hqvdp
;
647 return drm_debugfs_create_files(hqvdp_debugfs_files
,
648 ARRAY_SIZE(hqvdp_debugfs_files
),
649 minor
->debugfs_root
, minor
);
653 * sti_hqvdp_update_hvsrc
654 * @orient: horizontal or vertical
655 * @scale: scaling/zoom factor
656 * @hvsrc: the structure containing the LUT coef
658 * Update the Y and C Lut coef, as well as the shift param
663 static void sti_hqvdp_update_hvsrc(enum sti_hvsrc_orient orient
, int scale
,
664 struct sti_hqvdp_hvsrc
*hvsrc
)
666 const int *coef_c
, *coef_y
;
667 int shift_c
, shift_y
;
669 /* Get the appropriate coef tables */
670 if (scale
< SCALE_MAX_FOR_LEG_LUT_F
) {
671 coef_y
= coef_lut_f_y_legacy
;
672 coef_c
= coef_lut_f_c_legacy
;
673 shift_y
= SHIFT_LUT_F_Y_LEGACY
;
674 shift_c
= SHIFT_LUT_F_C_LEGACY
;
675 } else if (scale
< SCALE_MAX_FOR_LEG_LUT_E
) {
676 coef_y
= coef_lut_e_y_legacy
;
677 coef_c
= coef_lut_e_c_legacy
;
678 shift_y
= SHIFT_LUT_E_Y_LEGACY
;
679 shift_c
= SHIFT_LUT_E_C_LEGACY
;
680 } else if (scale
< SCALE_MAX_FOR_LEG_LUT_D
) {
681 coef_y
= coef_lut_d_y_legacy
;
682 coef_c
= coef_lut_d_c_legacy
;
683 shift_y
= SHIFT_LUT_D_Y_LEGACY
;
684 shift_c
= SHIFT_LUT_D_C_LEGACY
;
685 } else if (scale
< SCALE_MAX_FOR_LEG_LUT_C
) {
686 coef_y
= coef_lut_c_y_legacy
;
687 coef_c
= coef_lut_c_c_legacy
;
688 shift_y
= SHIFT_LUT_C_Y_LEGACY
;
689 shift_c
= SHIFT_LUT_C_C_LEGACY
;
690 } else if (scale
== SCALE_MAX_FOR_LEG_LUT_C
) {
691 coef_y
= coef_c
= coef_lut_b
;
692 shift_y
= shift_c
= SHIFT_LUT_B
;
694 coef_y
= coef_c
= coef_lut_a_legacy
;
695 shift_y
= shift_c
= SHIFT_LUT_A_LEGACY
;
698 if (orient
== HVSRC_HORI
) {
699 hvsrc
->hori_shift
= (shift_c
<< 16) | shift_y
;
700 memcpy(hvsrc
->yh_coef
, coef_y
, sizeof(hvsrc
->yh_coef
));
701 memcpy(hvsrc
->ch_coef
, coef_c
, sizeof(hvsrc
->ch_coef
));
703 hvsrc
->vert_shift
= (shift_c
<< 16) | shift_y
;
704 memcpy(hvsrc
->yv_coef
, coef_y
, sizeof(hvsrc
->yv_coef
));
705 memcpy(hvsrc
->cv_coef
, coef_c
, sizeof(hvsrc
->cv_coef
));
710 * sti_hqvdp_check_hw_scaling
711 * @hqvdp: hqvdp pointer
712 * @mode: display mode with timing constraints
713 * @src_w: source width
714 * @src_h: source height
715 * @dst_w: destination width
716 * @dst_h: destination height
718 * Check if the HW is able to perform the scaling request
719 * The firmware scaling limitation is "CEIL(1/Zy) <= FLOOR(LFW)" where:
720 * Zy = OutputHeight / InputHeight
721 * LFW = (Tx * IPClock) / (MaxNbCycles * Cp)
722 * Tx : Total video mode horizontal resolution
723 * IPClock : HQVDP IP clock (Mhz)
724 * MaxNbCycles: max(InputWidth, OutputWidth)
725 * Cp: Video mode pixel clock (Mhz)
728 * True if the HW can scale.
730 static bool sti_hqvdp_check_hw_scaling(struct sti_hqvdp
*hqvdp
,
731 struct drm_display_mode
*mode
,
732 int src_w
, int src_h
,
733 int dst_w
, int dst_h
)
738 lfw
= mode
->htotal
* (clk_get_rate(hqvdp
->clk
) / 1000000);
739 lfw
/= max(src_w
, dst_w
) * mode
->clock
/ 1000;
741 inv_zy
= DIV_ROUND_UP(src_h
, dst_h
);
743 return (inv_zy
<= lfw
) ? true : false;
748 * @hqvdp: hqvdp pointer
750 * Disables the HQVDP plane
752 static void sti_hqvdp_disable(struct sti_hqvdp
*hqvdp
)
756 DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&hqvdp
->plane
));
758 /* Unregister VTG Vsync callback */
759 if (sti_vtg_unregister_client(hqvdp
->vtg
, &hqvdp
->vtg_nb
))
760 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
762 /* Set next cmd to NULL */
763 writel(0, hqvdp
->regs
+ HQVDP_MBX_NEXT_CMD
);
765 for (i
= 0; i
< POLL_MAX_ATTEMPT
; i
++) {
766 if (readl(hqvdp
->regs
+ HQVDP_MBX_INFO_XP70
)
767 & INFO_XP70_FW_READY
)
769 msleep(POLL_DELAY_MS
);
772 /* VTG can stop now */
773 clk_disable_unprepare(hqvdp
->clk_pix_main
);
775 if (i
== POLL_MAX_ATTEMPT
)
776 DRM_ERROR("XP70 could not revert to idle\n");
778 hqvdp
->plane
.status
= STI_PLANE_DISABLED
;
783 * @nb: notifier block
784 * @evt: event message
785 * @data: private data
787 * Handle VTG Vsync event, display pending bottom field
792 int sti_hqvdp_vtg_cb(struct notifier_block
*nb
, unsigned long evt
, void *data
)
794 struct sti_hqvdp
*hqvdp
= container_of(nb
, struct sti_hqvdp
, vtg_nb
);
795 int btm_cmd_offset
, top_cmd_offest
;
796 struct sti_hqvdp_cmd
*btm_cmd
, *top_cmd
;
798 if ((evt
!= VTG_TOP_FIELD_EVENT
) && (evt
!= VTG_BOTTOM_FIELD_EVENT
)) {
799 DRM_DEBUG_DRIVER("Unknown event\n");
803 if (hqvdp
->plane
.status
== STI_PLANE_FLUSHING
) {
804 /* disable need to be synchronize on vsync event */
805 DRM_DEBUG_DRIVER("Vsync event received => disable %s\n",
806 sti_plane_to_str(&hqvdp
->plane
));
808 sti_hqvdp_disable(hqvdp
);
811 if (hqvdp
->btm_field_pending
) {
812 /* Create the btm field command from the current one */
813 btm_cmd_offset
= sti_hqvdp_get_free_cmd(hqvdp
);
814 top_cmd_offest
= sti_hqvdp_get_curr_cmd(hqvdp
);
815 if ((btm_cmd_offset
== -1) || (top_cmd_offest
== -1)) {
816 DRM_DEBUG_DRIVER("Warning: no cmd, will skip field\n");
820 btm_cmd
= hqvdp
->hqvdp_cmd
+ btm_cmd_offset
;
821 top_cmd
= hqvdp
->hqvdp_cmd
+ top_cmd_offest
;
823 memcpy(btm_cmd
, top_cmd
, sizeof(*btm_cmd
));
825 btm_cmd
->top
.config
= TOP_CONFIG_INTER_BTM
;
826 btm_cmd
->top
.current_luma
+=
827 btm_cmd
->top
.luma_src_pitch
/ 2;
828 btm_cmd
->top
.current_chroma
+=
829 btm_cmd
->top
.chroma_src_pitch
/ 2;
831 /* Post the command to mailbox */
832 writel(hqvdp
->hqvdp_cmd_paddr
+ btm_cmd_offset
,
833 hqvdp
->regs
+ HQVDP_MBX_NEXT_CMD
);
835 hqvdp
->btm_field_pending
= false;
837 dev_dbg(hqvdp
->dev
, "%s Posted command:0x%x\n",
838 __func__
, hqvdp
->hqvdp_cmd_paddr
);
840 sti_plane_update_fps(&hqvdp
->plane
, false, true);
846 static void sti_hqvdp_init(struct sti_hqvdp
*hqvdp
)
851 hqvdp
->vtg_nb
.notifier_call
= sti_hqvdp_vtg_cb
;
853 /* Allocate memory for the VDP commands */
854 size
= NB_VDP_CMD
* sizeof(struct sti_hqvdp_cmd
);
855 hqvdp
->hqvdp_cmd
= dma_alloc_wc(hqvdp
->dev
, size
,
857 GFP_KERNEL
| GFP_DMA
);
858 if (!hqvdp
->hqvdp_cmd
) {
859 DRM_ERROR("Failed to allocate memory for VDP cmd\n");
863 hqvdp
->hqvdp_cmd_paddr
= (u32
)dma_addr
;
864 memset(hqvdp
->hqvdp_cmd
, 0, size
);
867 static void sti_hqvdp_init_plugs(struct sti_hqvdp
*hqvdp
)
869 /* Configure Plugs (same for RD & WR) */
870 writel(PLUG_PAGE_SIZE_256
, hqvdp
->regs
+ HQVDP_RD_PLUG_PAGE_SIZE
);
871 writel(PLUG_MIN_OPC_8
, hqvdp
->regs
+ HQVDP_RD_PLUG_MIN_OPC
);
872 writel(PLUG_MAX_OPC_64
, hqvdp
->regs
+ HQVDP_RD_PLUG_MAX_OPC
);
873 writel(PLUG_MAX_CHK_2X
, hqvdp
->regs
+ HQVDP_RD_PLUG_MAX_CHK
);
874 writel(PLUG_MAX_MSG_1X
, hqvdp
->regs
+ HQVDP_RD_PLUG_MAX_MSG
);
875 writel(PLUG_MIN_SPACE_1
, hqvdp
->regs
+ HQVDP_RD_PLUG_MIN_SPACE
);
876 writel(PLUG_CONTROL_ENABLE
, hqvdp
->regs
+ HQVDP_RD_PLUG_CONTROL
);
878 writel(PLUG_PAGE_SIZE_256
, hqvdp
->regs
+ HQVDP_WR_PLUG_PAGE_SIZE
);
879 writel(PLUG_MIN_OPC_8
, hqvdp
->regs
+ HQVDP_WR_PLUG_MIN_OPC
);
880 writel(PLUG_MAX_OPC_64
, hqvdp
->regs
+ HQVDP_WR_PLUG_MAX_OPC
);
881 writel(PLUG_MAX_CHK_2X
, hqvdp
->regs
+ HQVDP_WR_PLUG_MAX_CHK
);
882 writel(PLUG_MAX_MSG_1X
, hqvdp
->regs
+ HQVDP_WR_PLUG_MAX_MSG
);
883 writel(PLUG_MIN_SPACE_1
, hqvdp
->regs
+ HQVDP_WR_PLUG_MIN_SPACE
);
884 writel(PLUG_CONTROL_ENABLE
, hqvdp
->regs
+ HQVDP_WR_PLUG_CONTROL
);
888 * sti_hqvdp_start_xp70
889 * @hqvdp: hqvdp pointer
891 * Run the xP70 initialization sequence
893 static void sti_hqvdp_start_xp70(struct sti_hqvdp
*hqvdp
)
895 const struct firmware
*firmware
;
896 u32
*fw_rd_plug
, *fw_wr_plug
, *fw_pmem
, *fw_dmem
;
906 DRM_DEBUG_DRIVER("\n");
908 if (hqvdp
->xp70_initialized
) {
909 DRM_DEBUG_DRIVER("HQVDP XP70 already initialized\n");
913 /* Request firmware */
914 if (request_firmware(&firmware
, HQVDP_FMW_NAME
, hqvdp
->dev
)) {
915 DRM_ERROR("Can't get HQVDP firmware\n");
919 /* Check firmware parts */
921 DRM_ERROR("Firmware not available\n");
925 header
= (struct fw_header
*)firmware
->data
;
926 if (firmware
->size
< sizeof(*header
)) {
927 DRM_ERROR("Invalid firmware size (%d)\n", firmware
->size
);
930 if ((sizeof(*header
) + header
->rd_size
+ header
->wr_size
+
931 header
->pmem_size
+ header
->dmem_size
) != firmware
->size
) {
932 DRM_ERROR("Invalid fmw structure (%d+%d+%d+%d+%d != %d)\n",
933 sizeof(*header
), header
->rd_size
, header
->wr_size
,
934 header
->pmem_size
, header
->dmem_size
,
939 data
= (u8
*)firmware
->data
;
940 data
+= sizeof(*header
);
941 fw_rd_plug
= (void *)data
;
942 data
+= header
->rd_size
;
943 fw_wr_plug
= (void *)data
;
944 data
+= header
->wr_size
;
945 fw_pmem
= (void *)data
;
946 data
+= header
->pmem_size
;
947 fw_dmem
= (void *)data
;
950 if (clk_prepare_enable(hqvdp
->clk
))
951 DRM_ERROR("Failed to prepare/enable HQVDP clk\n");
954 writel(SW_RESET_CTRL_FULL
, hqvdp
->regs
+ HQVDP_MBX_SW_RESET_CTRL
);
956 for (i
= 0; i
< POLL_MAX_ATTEMPT
; i
++) {
957 if (readl(hqvdp
->regs
+ HQVDP_MBX_STARTUP_CTRL1
)
958 & STARTUP_CTRL1_RST_DONE
)
960 msleep(POLL_DELAY_MS
);
962 if (i
== POLL_MAX_ATTEMPT
) {
963 DRM_ERROR("Could not reset\n");
967 /* Init Read & Write plugs */
968 for (i
= 0; i
< header
->rd_size
/ 4; i
++)
969 writel(fw_rd_plug
[i
], hqvdp
->regs
+ HQVDP_RD_PLUG
+ i
* 4);
970 for (i
= 0; i
< header
->wr_size
/ 4; i
++)
971 writel(fw_wr_plug
[i
], hqvdp
->regs
+ HQVDP_WR_PLUG
+ i
* 4);
973 sti_hqvdp_init_plugs(hqvdp
);
975 /* Authorize Idle Mode */
976 writel(STARTUP_CTRL1_AUTH_IDLE
, hqvdp
->regs
+ HQVDP_MBX_STARTUP_CTRL1
);
978 /* Prevent VTG interruption during the boot */
979 writel(SOFT_VSYNC_SW_CTRL_IRQ
, hqvdp
->regs
+ HQVDP_MBX_SOFT_VSYNC
);
980 writel(0, hqvdp
->regs
+ HQVDP_MBX_NEXT_CMD
);
982 /* Download PMEM & DMEM */
983 for (i
= 0; i
< header
->pmem_size
/ 4; i
++)
984 writel(fw_pmem
[i
], hqvdp
->regs
+ HQVDP_PMEM
+ i
* 4);
985 for (i
= 0; i
< header
->dmem_size
/ 4; i
++)
986 writel(fw_dmem
[i
], hqvdp
->regs
+ HQVDP_DMEM
+ i
* 4);
989 writel(STARTUP_CTRL2_FETCH_EN
, hqvdp
->regs
+ HQVDP_MBX_STARTUP_CTRL2
);
991 /* Wait end of boot */
992 for (i
= 0; i
< POLL_MAX_ATTEMPT
; i
++) {
993 if (readl(hqvdp
->regs
+ HQVDP_MBX_INFO_XP70
)
994 & INFO_XP70_FW_READY
)
996 msleep(POLL_DELAY_MS
);
998 if (i
== POLL_MAX_ATTEMPT
) {
999 DRM_ERROR("Could not boot\n");
1004 writel(SOFT_VSYNC_HW
, hqvdp
->regs
+ HQVDP_MBX_SOFT_VSYNC
);
1006 DRM_INFO("HQVDP XP70 initialized\n");
1008 hqvdp
->xp70_initialized
= true;
1011 release_firmware(firmware
);
1014 static int sti_hqvdp_atomic_check(struct drm_plane
*drm_plane
,
1015 struct drm_plane_state
*state
)
1017 struct sti_plane
*plane
= to_sti_plane(drm_plane
);
1018 struct sti_hqvdp
*hqvdp
= to_sti_hqvdp(plane
);
1019 struct drm_crtc
*crtc
= state
->crtc
;
1020 struct drm_framebuffer
*fb
= state
->fb
;
1021 bool first_prepare
= plane
->status
== STI_PLANE_DISABLED
? true : false;
1022 struct drm_crtc_state
*crtc_state
;
1023 struct drm_display_mode
*mode
;
1024 int dst_x
, dst_y
, dst_w
, dst_h
;
1025 int src_x
, src_y
, src_w
, src_h
;
1027 /* no need for further checks if the plane is being disabled */
1031 crtc_state
= drm_atomic_get_crtc_state(state
->state
, crtc
);
1032 mode
= &crtc_state
->mode
;
1033 dst_x
= state
->crtc_x
;
1034 dst_y
= state
->crtc_y
;
1035 dst_w
= clamp_val(state
->crtc_w
, 0, mode
->crtc_hdisplay
- dst_x
);
1036 dst_h
= clamp_val(state
->crtc_h
, 0, mode
->crtc_vdisplay
- dst_y
);
1037 /* src_x are in 16.16 format */
1038 src_x
= state
->src_x
>> 16;
1039 src_y
= state
->src_y
>> 16;
1040 src_w
= state
->src_w
>> 16;
1041 src_h
= state
->src_h
>> 16;
1043 if (!sti_hqvdp_check_hw_scaling(hqvdp
, mode
,
1046 DRM_ERROR("Scaling beyond HW capabilities\n");
1050 if (!drm_fb_cma_get_gem_obj(fb
, 0)) {
1051 DRM_ERROR("Can't get CMA GEM object for fb\n");
1056 * Input / output size
1057 * Align to upper even value
1059 dst_w
= ALIGN(dst_w
, 2);
1060 dst_h
= ALIGN(dst_h
, 2);
1062 if ((src_w
> MAX_WIDTH
) || (src_w
< MIN_WIDTH
) ||
1063 (src_h
> MAX_HEIGHT
) || (src_h
< MIN_HEIGHT
) ||
1064 (dst_w
> MAX_WIDTH
) || (dst_w
< MIN_WIDTH
) ||
1065 (dst_h
> MAX_HEIGHT
) || (dst_h
< MIN_HEIGHT
)) {
1066 DRM_ERROR("Invalid in/out size %dx%d -> %dx%d\n",
1072 if (first_prepare
) {
1073 /* Start HQVDP XP70 coprocessor */
1074 sti_hqvdp_start_xp70(hqvdp
);
1076 /* Prevent VTG shutdown */
1077 if (clk_prepare_enable(hqvdp
->clk_pix_main
)) {
1078 DRM_ERROR("Failed to prepare/enable pix main clk\n");
1082 /* Register VTG Vsync callback to handle bottom fields */
1083 if (sti_vtg_register_client(hqvdp
->vtg
,
1086 DRM_ERROR("Cannot register VTG notifier\n");
1091 DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n",
1092 crtc
->base
.id
, sti_mixer_to_str(to_sti_mixer(crtc
)),
1093 drm_plane
->base
.id
, sti_plane_to_str(plane
));
1094 DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n",
1095 sti_plane_to_str(plane
),
1096 dst_w
, dst_h
, dst_x
, dst_y
,
1097 src_w
, src_h
, src_x
, src_y
);
1102 static void sti_hqvdp_atomic_update(struct drm_plane
*drm_plane
,
1103 struct drm_plane_state
*oldstate
)
1105 struct drm_plane_state
*state
= drm_plane
->state
;
1106 struct sti_plane
*plane
= to_sti_plane(drm_plane
);
1107 struct sti_hqvdp
*hqvdp
= to_sti_hqvdp(plane
);
1108 struct drm_crtc
*crtc
= state
->crtc
;
1109 struct drm_framebuffer
*fb
= state
->fb
;
1110 struct drm_display_mode
*mode
;
1111 int dst_x
, dst_y
, dst_w
, dst_h
;
1112 int src_x
, src_y
, src_w
, src_h
;
1113 struct drm_gem_cma_object
*cma_obj
;
1114 struct sti_hqvdp_cmd
*cmd
;
1115 int scale_h
, scale_v
;
1122 dst_x
= state
->crtc_x
;
1123 dst_y
= state
->crtc_y
;
1124 dst_w
= clamp_val(state
->crtc_w
, 0, mode
->crtc_hdisplay
- dst_x
);
1125 dst_h
= clamp_val(state
->crtc_h
, 0, mode
->crtc_vdisplay
- dst_y
);
1126 /* src_x are in 16.16 format */
1127 src_x
= state
->src_x
>> 16;
1128 src_y
= state
->src_y
>> 16;
1129 src_w
= state
->src_w
>> 16;
1130 src_h
= state
->src_h
>> 16;
1132 cmd_offset
= sti_hqvdp_get_free_cmd(hqvdp
);
1133 if (cmd_offset
== -1) {
1134 DRM_DEBUG_DRIVER("Warning: no cmd, will skip frame\n");
1137 cmd
= hqvdp
->hqvdp_cmd
+ cmd_offset
;
1139 /* Static parameters, defaulting to progressive mode */
1140 cmd
->top
.config
= TOP_CONFIG_PROGRESSIVE
;
1141 cmd
->top
.mem_format
= TOP_MEM_FORMAT_DFLT
;
1142 cmd
->hvsrc
.param_ctrl
= HVSRC_PARAM_CTRL_DFLT
;
1143 cmd
->csdi
.config
= CSDI_CONFIG_PROG
;
1145 /* VC1RE, FMD bypassed : keep everything set to 0
1146 * IQI/P2I bypassed */
1147 cmd
->iqi
.config
= IQI_CONFIG_DFLT
;
1148 cmd
->iqi
.con_bri
= IQI_CON_BRI_DFLT
;
1149 cmd
->iqi
.sat_gain
= IQI_SAT_GAIN_DFLT
;
1150 cmd
->iqi
.pxf_conf
= IQI_PXF_CONF_DFLT
;
1152 cma_obj
= drm_fb_cma_get_gem_obj(fb
, 0);
1154 DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb
->base
.id
,
1155 (char *)&fb
->pixel_format
,
1156 (unsigned long)cma_obj
->paddr
);
1158 /* Buffer planes address */
1159 cmd
->top
.current_luma
= (u32
)cma_obj
->paddr
+ fb
->offsets
[0];
1160 cmd
->top
.current_chroma
= (u32
)cma_obj
->paddr
+ fb
->offsets
[1];
1163 cmd
->top
.luma_processed_pitch
= fb
->pitches
[0];
1164 cmd
->top
.luma_src_pitch
= fb
->pitches
[0];
1165 cmd
->top
.chroma_processed_pitch
= fb
->pitches
[1];
1166 cmd
->top
.chroma_src_pitch
= fb
->pitches
[1];
1168 /* Input / output size
1169 * Align to upper even value */
1170 dst_w
= ALIGN(dst_w
, 2);
1171 dst_h
= ALIGN(dst_h
, 2);
1173 cmd
->top
.input_viewport_size
= src_h
<< 16 | src_w
;
1174 cmd
->top
.input_frame_size
= src_h
<< 16 | src_w
;
1175 cmd
->hvsrc
.output_picture_size
= dst_h
<< 16 | dst_w
;
1176 cmd
->top
.input_viewport_ori
= src_y
<< 16 | src_x
;
1178 /* Handle interlaced */
1179 if (fb
->flags
& DRM_MODE_FB_INTERLACED
) {
1180 /* Top field to display */
1181 cmd
->top
.config
= TOP_CONFIG_INTER_TOP
;
1183 /* Update pitches and vert size */
1184 cmd
->top
.input_frame_size
= (src_h
/ 2) << 16 | src_w
;
1185 cmd
->top
.luma_processed_pitch
*= 2;
1186 cmd
->top
.luma_src_pitch
*= 2;
1187 cmd
->top
.chroma_processed_pitch
*= 2;
1188 cmd
->top
.chroma_src_pitch
*= 2;
1190 /* Enable directional deinterlacing processing */
1191 cmd
->csdi
.config
= CSDI_CONFIG_INTER_DIR
;
1192 cmd
->csdi
.config2
= CSDI_CONFIG2_DFLT
;
1193 cmd
->csdi
.dcdi_config
= CSDI_DCDI_CONFIG_DFLT
;
1196 /* Update hvsrc lut coef */
1197 scale_h
= SCALE_FACTOR
* dst_w
/ src_w
;
1198 sti_hqvdp_update_hvsrc(HVSRC_HORI
, scale_h
, &cmd
->hvsrc
);
1200 scale_v
= SCALE_FACTOR
* dst_h
/ src_h
;
1201 sti_hqvdp_update_hvsrc(HVSRC_VERT
, scale_v
, &cmd
->hvsrc
);
1203 writel(hqvdp
->hqvdp_cmd_paddr
+ cmd_offset
,
1204 hqvdp
->regs
+ HQVDP_MBX_NEXT_CMD
);
1206 /* Interlaced : get ready to display the bottom field at next Vsync */
1207 if (fb
->flags
& DRM_MODE_FB_INTERLACED
)
1208 hqvdp
->btm_field_pending
= true;
1210 dev_dbg(hqvdp
->dev
, "%s Posted command:0x%x\n",
1211 __func__
, hqvdp
->hqvdp_cmd_paddr
+ cmd_offset
);
1213 sti_plane_update_fps(plane
, true, true);
1215 plane
->status
= STI_PLANE_UPDATED
;
1218 static void sti_hqvdp_atomic_disable(struct drm_plane
*drm_plane
,
1219 struct drm_plane_state
*oldstate
)
1221 struct sti_plane
*plane
= to_sti_plane(drm_plane
);
1223 if (!drm_plane
->crtc
) {
1224 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n",
1225 drm_plane
->base
.id
);
1229 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n",
1230 drm_plane
->crtc
->base
.id
,
1231 sti_mixer_to_str(to_sti_mixer(drm_plane
->crtc
)),
1232 drm_plane
->base
.id
, sti_plane_to_str(plane
));
1234 plane
->status
= STI_PLANE_DISABLING
;
1237 static const struct drm_plane_helper_funcs sti_hqvdp_helpers_funcs
= {
1238 .atomic_check
= sti_hqvdp_atomic_check
,
1239 .atomic_update
= sti_hqvdp_atomic_update
,
1240 .atomic_disable
= sti_hqvdp_atomic_disable
,
1243 static struct drm_plane
*sti_hqvdp_create(struct drm_device
*drm_dev
,
1244 struct device
*dev
, int desc
)
1246 struct sti_hqvdp
*hqvdp
= dev_get_drvdata(dev
);
1249 hqvdp
->plane
.desc
= desc
;
1250 hqvdp
->plane
.status
= STI_PLANE_DISABLED
;
1252 sti_hqvdp_init(hqvdp
);
1254 res
= drm_universal_plane_init(drm_dev
, &hqvdp
->plane
.drm_plane
, 1,
1255 &sti_plane_helpers_funcs
,
1256 hqvdp_supported_formats
,
1257 ARRAY_SIZE(hqvdp_supported_formats
),
1258 DRM_PLANE_TYPE_OVERLAY
, NULL
);
1260 DRM_ERROR("Failed to initialize universal plane\n");
1264 drm_plane_helper_add(&hqvdp
->plane
.drm_plane
, &sti_hqvdp_helpers_funcs
);
1266 sti_plane_init_property(&hqvdp
->plane
, DRM_PLANE_TYPE_OVERLAY
);
1268 if (hqvdp_debugfs_init(hqvdp
, drm_dev
->primary
))
1269 DRM_ERROR("HQVDP debugfs setup failed\n");
1271 return &hqvdp
->plane
.drm_plane
;
1274 int sti_hqvdp_bind(struct device
*dev
, struct device
*master
, void *data
)
1276 struct sti_hqvdp
*hqvdp
= dev_get_drvdata(dev
);
1277 struct drm_device
*drm_dev
= data
;
1278 struct drm_plane
*plane
;
1280 DRM_DEBUG_DRIVER("\n");
1282 hqvdp
->drm_dev
= drm_dev
;
1284 /* Create HQVDP plane once xp70 is initialized */
1285 plane
= sti_hqvdp_create(drm_dev
, hqvdp
->dev
, STI_HQVDP_0
);
1287 DRM_ERROR("Can't create HQVDP plane\n");
1292 static void sti_hqvdp_unbind(struct device
*dev
,
1293 struct device
*master
, void *data
)
1298 static const struct component_ops sti_hqvdp_ops
= {
1299 .bind
= sti_hqvdp_bind
,
1300 .unbind
= sti_hqvdp_unbind
,
1303 static int sti_hqvdp_probe(struct platform_device
*pdev
)
1305 struct device
*dev
= &pdev
->dev
;
1306 struct device_node
*vtg_np
;
1307 struct sti_hqvdp
*hqvdp
;
1308 struct resource
*res
;
1310 DRM_DEBUG_DRIVER("\n");
1312 hqvdp
= devm_kzalloc(dev
, sizeof(*hqvdp
), GFP_KERNEL
);
1314 DRM_ERROR("Failed to allocate HQVDP context\n");
1320 /* Get Memory resources */
1321 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1323 DRM_ERROR("Get memory resource failed\n");
1326 hqvdp
->regs
= devm_ioremap(dev
, res
->start
, resource_size(res
));
1327 if (hqvdp
->regs
== NULL
) {
1328 DRM_ERROR("Register mapping failed\n");
1332 /* Get clock resources */
1333 hqvdp
->clk
= devm_clk_get(dev
, "hqvdp");
1334 hqvdp
->clk_pix_main
= devm_clk_get(dev
, "pix_main");
1335 if (IS_ERR(hqvdp
->clk
) || IS_ERR(hqvdp
->clk_pix_main
)) {
1336 DRM_ERROR("Cannot get clocks\n");
1340 /* Get reset resources */
1341 hqvdp
->reset
= devm_reset_control_get(dev
, "hqvdp");
1342 if (!IS_ERR(hqvdp
->reset
))
1343 reset_control_deassert(hqvdp
->reset
);
1345 vtg_np
= of_parse_phandle(pdev
->dev
.of_node
, "st,vtg", 0);
1347 hqvdp
->vtg
= of_vtg_find(vtg_np
);
1349 platform_set_drvdata(pdev
, hqvdp
);
1351 return component_add(&pdev
->dev
, &sti_hqvdp_ops
);
1354 static int sti_hqvdp_remove(struct platform_device
*pdev
)
1356 component_del(&pdev
->dev
, &sti_hqvdp_ops
);
1360 static struct of_device_id hqvdp_of_match
[] = {
1361 { .compatible
= "st,stih407-hqvdp", },
1364 MODULE_DEVICE_TABLE(of
, hqvdp_of_match
);
1366 struct platform_driver sti_hqvdp_driver
= {
1368 .name
= "sti-hqvdp",
1369 .owner
= THIS_MODULE
,
1370 .of_match_table
= hqvdp_of_match
,
1372 .probe
= sti_hqvdp_probe
,
1373 .remove
= sti_hqvdp_remove
,
1376 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
1377 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
1378 MODULE_LICENSE("GPL");