2 * Copyright (C) STMicroelectronics SA 2014
3 * Authors: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
4 * License terms: GNU General Public License (GPL), version 2
7 #include <linux/component.h>
8 #include <linux/firmware.h>
9 #include <linux/reset.h>
10 #include <linux/seq_file.h>
12 #include <drm/drm_atomic.h>
13 #include <drm/drm_fb_cma_helper.h>
14 #include <drm/drm_gem_cma_helper.h>
16 #include "sti_compositor.h"
17 #include "sti_hqvdp_lut.h"
18 #include "sti_plane.h"
22 #define HQVDP_FMW_NAME "hqvdp-stih407.bin"
25 #define HQVDP_DMEM 0x00000000 /* 0x00000000 */
26 #define HQVDP_PMEM 0x00040000 /* 0x00040000 */
27 #define HQVDP_RD_PLUG 0x000E0000 /* 0x000E0000 */
28 #define HQVDP_RD_PLUG_CONTROL (HQVDP_RD_PLUG + 0x1000) /* 0x000E1000 */
29 #define HQVDP_RD_PLUG_PAGE_SIZE (HQVDP_RD_PLUG + 0x1004) /* 0x000E1004 */
30 #define HQVDP_RD_PLUG_MIN_OPC (HQVDP_RD_PLUG + 0x1008) /* 0x000E1008 */
31 #define HQVDP_RD_PLUG_MAX_OPC (HQVDP_RD_PLUG + 0x100C) /* 0x000E100C */
32 #define HQVDP_RD_PLUG_MAX_CHK (HQVDP_RD_PLUG + 0x1010) /* 0x000E1010 */
33 #define HQVDP_RD_PLUG_MAX_MSG (HQVDP_RD_PLUG + 0x1014) /* 0x000E1014 */
34 #define HQVDP_RD_PLUG_MIN_SPACE (HQVDP_RD_PLUG + 0x1018) /* 0x000E1018 */
35 #define HQVDP_WR_PLUG 0x000E2000 /* 0x000E2000 */
36 #define HQVDP_WR_PLUG_CONTROL (HQVDP_WR_PLUG + 0x1000) /* 0x000E3000 */
37 #define HQVDP_WR_PLUG_PAGE_SIZE (HQVDP_WR_PLUG + 0x1004) /* 0x000E3004 */
38 #define HQVDP_WR_PLUG_MIN_OPC (HQVDP_WR_PLUG + 0x1008) /* 0x000E3008 */
39 #define HQVDP_WR_PLUG_MAX_OPC (HQVDP_WR_PLUG + 0x100C) /* 0x000E300C */
40 #define HQVDP_WR_PLUG_MAX_CHK (HQVDP_WR_PLUG + 0x1010) /* 0x000E3010 */
41 #define HQVDP_WR_PLUG_MAX_MSG (HQVDP_WR_PLUG + 0x1014) /* 0x000E3014 */
42 #define HQVDP_WR_PLUG_MIN_SPACE (HQVDP_WR_PLUG + 0x1018) /* 0x000E3018 */
43 #define HQVDP_MBX 0x000E4000 /* 0x000E4000 */
44 #define HQVDP_MBX_IRQ_TO_XP70 (HQVDP_MBX + 0x0000) /* 0x000E4000 */
45 #define HQVDP_MBX_INFO_HOST (HQVDP_MBX + 0x0004) /* 0x000E4004 */
46 #define HQVDP_MBX_IRQ_TO_HOST (HQVDP_MBX + 0x0008) /* 0x000E4008 */
47 #define HQVDP_MBX_INFO_XP70 (HQVDP_MBX + 0x000C) /* 0x000E400C */
48 #define HQVDP_MBX_SW_RESET_CTRL (HQVDP_MBX + 0x0010) /* 0x000E4010 */
49 #define HQVDP_MBX_STARTUP_CTRL1 (HQVDP_MBX + 0x0014) /* 0x000E4014 */
50 #define HQVDP_MBX_STARTUP_CTRL2 (HQVDP_MBX + 0x0018) /* 0x000E4018 */
51 #define HQVDP_MBX_GP_STATUS (HQVDP_MBX + 0x001C) /* 0x000E401C */
52 #define HQVDP_MBX_NEXT_CMD (HQVDP_MBX + 0x0020) /* 0x000E4020 */
53 #define HQVDP_MBX_CURRENT_CMD (HQVDP_MBX + 0x0024) /* 0x000E4024 */
54 #define HQVDP_MBX_SOFT_VSYNC (HQVDP_MBX + 0x0028) /* 0x000E4028 */
57 #define PLUG_CONTROL_ENABLE 0x00000001
58 #define PLUG_PAGE_SIZE_256 0x00000002
59 #define PLUG_MIN_OPC_8 0x00000003
60 #define PLUG_MAX_OPC_64 0x00000006
61 #define PLUG_MAX_CHK_2X 0x00000001
62 #define PLUG_MAX_MSG_1X 0x00000000
63 #define PLUG_MIN_SPACE_1 0x00000000
66 #define SW_RESET_CTRL_FULL BIT(0)
67 #define SW_RESET_CTRL_CORE BIT(1)
70 #define STARTUP_CTRL1_RST_DONE BIT(0)
71 #define STARTUP_CTRL1_AUTH_IDLE BIT(2)
74 #define STARTUP_CTRL2_FETCH_EN BIT(1)
77 #define INFO_XP70_FW_READY BIT(15)
78 #define INFO_XP70_FW_PROCESSING BIT(14)
79 #define INFO_XP70_FW_INITQUEUES BIT(13)
82 #define SOFT_VSYNC_HW 0x00000000
83 #define SOFT_VSYNC_SW_CMD 0x00000001
84 #define SOFT_VSYNC_SW_CTRL_IRQ 0x00000003
86 /* Reset & boot poll config */
87 #define POLL_MAX_ATTEMPT 50
88 #define POLL_DELAY_MS 20
90 #define SCALE_FACTOR 8192
91 #define SCALE_MAX_FOR_LEG_LUT_F 4096
92 #define SCALE_MAX_FOR_LEG_LUT_E 4915
93 #define SCALE_MAX_FOR_LEG_LUT_D 6654
94 #define SCALE_MAX_FOR_LEG_LUT_C 8192
96 enum sti_hvsrc_orient
{
101 /* Command structures */
102 struct sti_hqvdp_top
{
106 u32 current_enh_luma
;
107 u32 current_right_luma
;
108 u32 current_enh_right_luma
;
110 u32 current_enh_chroma
;
111 u32 current_right_chroma
;
112 u32 current_enh_right_chroma
;
116 u32 luma_enh_src_pitch
;
117 u32 luma_right_src_pitch
;
118 u32 luma_enh_right_src_pitch
;
119 u32 chroma_src_pitch
;
120 u32 chroma_enh_src_pitch
;
121 u32 chroma_right_src_pitch
;
122 u32 chroma_enh_right_src_pitch
;
123 u32 luma_processed_pitch
;
124 u32 chroma_processed_pitch
;
125 u32 input_frame_size
;
126 u32 input_viewport_ori
;
127 u32 input_viewport_ori_right
;
128 u32 input_viewport_size
;
129 u32 left_view_border_width
;
130 u32 right_view_border_width
;
131 u32 left_view_3d_offset_width
;
132 u32 right_view_3d_offset_width
;
133 u32 side_stripe_color
;
137 /* Configs for interlaced : no IT, no pass thru, 3 fields */
138 #define TOP_CONFIG_INTER_BTM 0x00000000
139 #define TOP_CONFIG_INTER_TOP 0x00000002
141 /* Config for progressive : no IT, no pass thru, 3 fields */
142 #define TOP_CONFIG_PROGRESSIVE 0x00000001
144 /* Default MemFormat: in=420_raster_dual out=444_raster;opaque Mem2Tv mode */
145 #define TOP_MEM_FORMAT_DFLT 0x00018060
148 #define MAX_WIDTH 0x1FFF
149 #define MAX_HEIGHT 0x0FFF
150 #define MIN_WIDTH 0x0030
151 #define MIN_HEIGHT 0x0010
153 struct sti_hqvdp_vc1re
{
161 struct sti_hqvdp_fmd
{
166 u32 next_next_right_luma
;
167 u32 next_next_next_luma
;
168 u32 next_next_next_right_luma
;
175 struct sti_hqvdp_csdi
{
182 u32 prev_enh_right_luma
;
186 u32 next_enh_right_luma
;
189 u32 prev_right_chroma
;
190 u32 prev_enh_right_chroma
;
193 u32 next_right_chroma
;
194 u32 next_enh_right_chroma
;
196 u32 prev_right_motion
;
198 u32 cur_right_motion
;
200 u32 next_right_motion
;
203 /* Config for progressive: by pass */
204 #define CSDI_CONFIG_PROG 0x00000000
205 /* Config for directional deinterlacing without motion */
206 #define CSDI_CONFIG_INTER_DIR 0x00000016
207 /* Additional configs for fader, blender, motion,... deinterlace algorithms */
208 #define CSDI_CONFIG2_DFLT 0x000001B3
209 #define CSDI_DCDI_CONFIG_DFLT 0x00203803
211 struct sti_hqvdp_hvsrc
{
212 u32 hor_panoramic_ctrl
;
213 u32 output_picture_size
;
217 u32 yh_coef
[NB_COEF
];
218 u32 ch_coef
[NB_COEF
];
219 u32 yv_coef
[NB_COEF
];
220 u32 cv_coef
[NB_COEF
];
225 /* Default ParamCtrl: all controls enabled */
226 #define HVSRC_PARAM_CTRL_DFLT 0xFFFFFFFF
228 struct sti_hqvdp_iqi
{
247 /* Default Config : IQI bypassed */
248 #define IQI_CONFIG_DFLT 0x00000001
249 /* Default Contrast & Brightness gain = 256 */
250 #define IQI_CON_BRI_DFLT 0x00000100
251 /* Default Saturation gain = 256 */
252 #define IQI_SAT_GAIN_DFLT 0x00000100
253 /* Default PxfConf : P2I bypassed */
254 #define IQI_PXF_CONF_DFLT 0x00000001
256 struct sti_hqvdp_top_status
{
262 struct sti_hqvdp_fmd_status
{
263 u32 fmd_repeat_move_status
;
264 u32 fmd_scene_count_status
;
268 u32 next_next_y_fmd_crc
;
269 u32 next_next_next_y_fmd_crc
;
272 struct sti_hqvdp_csdi_status
{
276 u32 prev_uv_csdi_crc
;
278 u32 next_uv_csdi_crc
;
283 u32 mot_cur_csdi_crc
;
284 u32 mot_prev_csdi_crc
;
287 struct sti_hqvdp_hvsrc_status
{
293 struct sti_hqvdp_iqi_status
{
300 /* Main commands. We use 2 commands one being processed by the firmware, one
301 * ready to be fetched upon next Vsync*/
304 struct sti_hqvdp_cmd
{
305 struct sti_hqvdp_top top
;
306 struct sti_hqvdp_vc1re vc1re
;
307 struct sti_hqvdp_fmd fmd
;
308 struct sti_hqvdp_csdi csdi
;
309 struct sti_hqvdp_hvsrc hvsrc
;
310 struct sti_hqvdp_iqi iqi
;
311 struct sti_hqvdp_top_status top_status
;
312 struct sti_hqvdp_fmd_status fmd_status
;
313 struct sti_hqvdp_csdi_status csdi_status
;
314 struct sti_hqvdp_hvsrc_status hvsrc_status
;
315 struct sti_hqvdp_iqi_status iqi_status
;
319 * STI HQVDP structure
321 * @dev: driver device
322 * @drm_dev: the drm device
324 * @plane: plane structure for hqvdp it self
326 * @clk_pix_main: pix main clock
327 * @reset: reset control
328 * @vtg_nb: notifier to handle VTG Vsync
329 * @btm_field_pending: is there any bottom field (interlaced frame) to display
330 * @hqvdp_cmd: buffer of commands
331 * @hqvdp_cmd_paddr: physical address of hqvdp_cmd
332 * @vtg: vtg for main data path
333 * @xp70_initialized: true if xp70 is already initialized
337 struct drm_device
*drm_dev
;
339 struct sti_plane plane
;
341 struct clk
*clk_pix_main
;
342 struct reset_control
*reset
;
343 struct notifier_block vtg_nb
;
344 bool btm_field_pending
;
348 bool xp70_initialized
;
351 #define to_sti_hqvdp(x) container_of(x, struct sti_hqvdp, plane)
353 static const uint32_t hqvdp_supported_formats
[] = {
358 * sti_hqvdp_get_free_cmd
359 * @hqvdp: hqvdp structure
361 * Look for a hqvdp_cmd that is not being used (or about to be used) by the FW.
364 * the offset of the command to be used.
367 static int sti_hqvdp_get_free_cmd(struct sti_hqvdp
*hqvdp
)
369 u32 curr_cmd
, next_cmd
;
370 u32 cmd
= hqvdp
->hqvdp_cmd_paddr
;
373 curr_cmd
= readl(hqvdp
->regs
+ HQVDP_MBX_CURRENT_CMD
);
374 next_cmd
= readl(hqvdp
->regs
+ HQVDP_MBX_NEXT_CMD
);
376 for (i
= 0; i
< NB_VDP_CMD
; i
++) {
377 if ((cmd
!= curr_cmd
) && (cmd
!= next_cmd
))
378 return i
* sizeof(struct sti_hqvdp_cmd
);
379 cmd
+= sizeof(struct sti_hqvdp_cmd
);
386 * sti_hqvdp_get_curr_cmd
387 * @hqvdp: hqvdp structure
389 * Look for the hqvdp_cmd that is being used by the FW.
392 * the offset of the command to be used.
395 static int sti_hqvdp_get_curr_cmd(struct sti_hqvdp
*hqvdp
)
398 u32 cmd
= hqvdp
->hqvdp_cmd_paddr
;
401 curr_cmd
= readl(hqvdp
->regs
+ HQVDP_MBX_CURRENT_CMD
);
403 for (i
= 0; i
< NB_VDP_CMD
; i
++) {
405 return i
* sizeof(struct sti_hqvdp_cmd
);
407 cmd
+= sizeof(struct sti_hqvdp_cmd
);
414 * sti_hqvdp_get_next_cmd
415 * @hqvdp: hqvdp structure
417 * Look for the next hqvdp_cmd that will be used by the FW.
420 * the offset of the next command that will be used.
423 static int sti_hqvdp_get_next_cmd(struct sti_hqvdp
*hqvdp
)
426 dma_addr_t cmd
= hqvdp
->hqvdp_cmd_paddr
;
429 next_cmd
= readl(hqvdp
->regs
+ HQVDP_MBX_NEXT_CMD
);
431 for (i
= 0; i
< NB_VDP_CMD
; i
++) {
433 return i
* sizeof(struct sti_hqvdp_cmd
);
435 cmd
+= sizeof(struct sti_hqvdp_cmd
);
441 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \
442 readl(hqvdp->regs + reg))
444 static const char *hqvdp_dbg_get_lut(u32
*coef
)
446 if (!memcmp(coef
, coef_lut_a_legacy
, 16))
448 if (!memcmp(coef
, coef_lut_b
, 16))
450 if (!memcmp(coef
, coef_lut_c_y_legacy
, 16))
452 if (!memcmp(coef
, coef_lut_c_c_legacy
, 16))
454 if (!memcmp(coef
, coef_lut_d_y_legacy
, 16))
456 if (!memcmp(coef
, coef_lut_d_c_legacy
, 16))
458 if (!memcmp(coef
, coef_lut_e_y_legacy
, 16))
460 if (!memcmp(coef
, coef_lut_e_c_legacy
, 16))
462 if (!memcmp(coef
, coef_lut_f_y_legacy
, 16))
464 if (!memcmp(coef
, coef_lut_f_c_legacy
, 16))
469 static void hqvdp_dbg_dump_cmd(struct seq_file
*s
, struct sti_hqvdp_cmd
*c
)
471 int src_w
, src_h
, dst_w
, dst_h
;
473 seq_puts(s
, "\n\tTOP:");
474 seq_printf(s
, "\n\t %-20s 0x%08X", "Config", c
->top
.config
);
475 switch (c
->top
.config
) {
476 case TOP_CONFIG_PROGRESSIVE
:
477 seq_puts(s
, "\tProgressive");
479 case TOP_CONFIG_INTER_TOP
:
480 seq_puts(s
, "\tInterlaced, top field");
482 case TOP_CONFIG_INTER_BTM
:
483 seq_puts(s
, "\tInterlaced, bottom field");
486 seq_puts(s
, "\t<UNKNOWN>");
490 seq_printf(s
, "\n\t %-20s 0x%08X", "MemFormat", c
->top
.mem_format
);
491 seq_printf(s
, "\n\t %-20s 0x%08X", "CurrentY", c
->top
.current_luma
);
492 seq_printf(s
, "\n\t %-20s 0x%08X", "CurrentC", c
->top
.current_chroma
);
493 seq_printf(s
, "\n\t %-20s 0x%08X", "YSrcPitch", c
->top
.luma_src_pitch
);
494 seq_printf(s
, "\n\t %-20s 0x%08X", "CSrcPitch",
495 c
->top
.chroma_src_pitch
);
496 seq_printf(s
, "\n\t %-20s 0x%08X", "InputFrameSize",
497 c
->top
.input_frame_size
);
498 seq_printf(s
, "\t%dx%d",
499 c
->top
.input_frame_size
& 0x0000FFFF,
500 c
->top
.input_frame_size
>> 16);
501 seq_printf(s
, "\n\t %-20s 0x%08X", "InputViewportSize",
502 c
->top
.input_viewport_size
);
503 src_w
= c
->top
.input_viewport_size
& 0x0000FFFF;
504 src_h
= c
->top
.input_viewport_size
>> 16;
505 seq_printf(s
, "\t%dx%d", src_w
, src_h
);
507 seq_puts(s
, "\n\tHVSRC:");
508 seq_printf(s
, "\n\t %-20s 0x%08X", "OutputPictureSize",
509 c
->hvsrc
.output_picture_size
);
510 dst_w
= c
->hvsrc
.output_picture_size
& 0x0000FFFF;
511 dst_h
= c
->hvsrc
.output_picture_size
>> 16;
512 seq_printf(s
, "\t%dx%d", dst_w
, dst_h
);
513 seq_printf(s
, "\n\t %-20s 0x%08X", "ParamCtrl", c
->hvsrc
.param_ctrl
);
515 seq_printf(s
, "\n\t %-20s %s", "yh_coef",
516 hqvdp_dbg_get_lut(c
->hvsrc
.yh_coef
));
517 seq_printf(s
, "\n\t %-20s %s", "ch_coef",
518 hqvdp_dbg_get_lut(c
->hvsrc
.ch_coef
));
519 seq_printf(s
, "\n\t %-20s %s", "yv_coef",
520 hqvdp_dbg_get_lut(c
->hvsrc
.yv_coef
));
521 seq_printf(s
, "\n\t %-20s %s", "cv_coef",
522 hqvdp_dbg_get_lut(c
->hvsrc
.cv_coef
));
524 seq_printf(s
, "\n\t %-20s", "ScaleH");
526 seq_printf(s
, " %d/1", dst_w
/ src_w
);
528 seq_printf(s
, " 1/%d", src_w
/ dst_w
);
530 seq_printf(s
, "\n\t %-20s", "tScaleV");
532 seq_printf(s
, " %d/1", dst_h
/ src_h
);
534 seq_printf(s
, " 1/%d", src_h
/ dst_h
);
536 seq_puts(s
, "\n\tCSDI:");
537 seq_printf(s
, "\n\t %-20s 0x%08X\t", "Config", c
->csdi
.config
);
538 switch (c
->csdi
.config
) {
539 case CSDI_CONFIG_PROG
:
540 seq_puts(s
, "Bypass");
542 case CSDI_CONFIG_INTER_DIR
:
543 seq_puts(s
, "Deinterlace, directional");
546 seq_puts(s
, "<UNKNOWN>");
550 seq_printf(s
, "\n\t %-20s 0x%08X", "Config2", c
->csdi
.config2
);
551 seq_printf(s
, "\n\t %-20s 0x%08X", "DcdiConfig", c
->csdi
.dcdi_config
);
554 static int hqvdp_dbg_show(struct seq_file
*s
, void *data
)
556 struct drm_info_node
*node
= s
->private;
557 struct sti_hqvdp
*hqvdp
= (struct sti_hqvdp
*)node
->info_ent
->data
;
558 int cmd
, cmd_offset
, infoxp70
;
561 seq_printf(s
, "%s: (vaddr = 0x%p)",
562 sti_plane_to_str(&hqvdp
->plane
), hqvdp
->regs
);
564 DBGFS_DUMP(HQVDP_MBX_IRQ_TO_XP70
);
565 DBGFS_DUMP(HQVDP_MBX_INFO_HOST
);
566 DBGFS_DUMP(HQVDP_MBX_IRQ_TO_HOST
);
567 DBGFS_DUMP(HQVDP_MBX_INFO_XP70
);
568 infoxp70
= readl(hqvdp
->regs
+ HQVDP_MBX_INFO_XP70
);
569 seq_puts(s
, "\tFirmware state: ");
570 if (infoxp70
& INFO_XP70_FW_READY
)
571 seq_puts(s
, "idle and ready");
572 else if (infoxp70
& INFO_XP70_FW_PROCESSING
)
573 seq_puts(s
, "processing a picture");
574 else if (infoxp70
& INFO_XP70_FW_INITQUEUES
)
575 seq_puts(s
, "programming queues");
577 seq_puts(s
, "NOT READY");
579 DBGFS_DUMP(HQVDP_MBX_SW_RESET_CTRL
);
580 DBGFS_DUMP(HQVDP_MBX_STARTUP_CTRL1
);
581 if (readl(hqvdp
->regs
+ HQVDP_MBX_STARTUP_CTRL1
)
582 & STARTUP_CTRL1_RST_DONE
)
583 seq_puts(s
, "\tReset is done");
585 seq_puts(s
, "\tReset is NOT done");
586 DBGFS_DUMP(HQVDP_MBX_STARTUP_CTRL2
);
587 if (readl(hqvdp
->regs
+ HQVDP_MBX_STARTUP_CTRL2
)
588 & STARTUP_CTRL2_FETCH_EN
)
589 seq_puts(s
, "\tFetch is enabled");
591 seq_puts(s
, "\tFetch is NOT enabled");
592 DBGFS_DUMP(HQVDP_MBX_GP_STATUS
);
593 DBGFS_DUMP(HQVDP_MBX_NEXT_CMD
);
594 DBGFS_DUMP(HQVDP_MBX_CURRENT_CMD
);
595 DBGFS_DUMP(HQVDP_MBX_SOFT_VSYNC
);
596 if (!(readl(hqvdp
->regs
+ HQVDP_MBX_SOFT_VSYNC
) & 3))
597 seq_puts(s
, "\tHW Vsync");
599 seq_puts(s
, "\tSW Vsync ?!?!");
602 cmd
= readl(hqvdp
->regs
+ HQVDP_MBX_CURRENT_CMD
);
603 cmd_offset
= sti_hqvdp_get_curr_cmd(hqvdp
);
604 if (cmd_offset
== -1) {
605 seq_puts(s
, "\n\n Last command: unknown");
607 virt
= hqvdp
->hqvdp_cmd
+ cmd_offset
;
608 seq_printf(s
, "\n\n Last command: address @ 0x%x (0x%p)",
610 hqvdp_dbg_dump_cmd(s
, (struct sti_hqvdp_cmd
*)virt
);
614 cmd
= readl(hqvdp
->regs
+ HQVDP_MBX_NEXT_CMD
);
615 cmd_offset
= sti_hqvdp_get_next_cmd(hqvdp
);
616 if (cmd_offset
== -1) {
617 seq_puts(s
, "\n\n Next command: unknown");
619 virt
= hqvdp
->hqvdp_cmd
+ cmd_offset
;
620 seq_printf(s
, "\n\n Next command address: @ 0x%x (0x%p)",
622 hqvdp_dbg_dump_cmd(s
, (struct sti_hqvdp_cmd
*)virt
);
630 static struct drm_info_list hqvdp_debugfs_files
[] = {
631 { "hqvdp", hqvdp_dbg_show
, 0, NULL
},
634 static int hqvdp_debugfs_init(struct sti_hqvdp
*hqvdp
, struct drm_minor
*minor
)
638 for (i
= 0; i
< ARRAY_SIZE(hqvdp_debugfs_files
); i
++)
639 hqvdp_debugfs_files
[i
].data
= hqvdp
;
641 return drm_debugfs_create_files(hqvdp_debugfs_files
,
642 ARRAY_SIZE(hqvdp_debugfs_files
),
643 minor
->debugfs_root
, minor
);
647 * sti_hqvdp_update_hvsrc
648 * @orient: horizontal or vertical
649 * @scale: scaling/zoom factor
650 * @hvsrc: the structure containing the LUT coef
652 * Update the Y and C Lut coef, as well as the shift param
657 static void sti_hqvdp_update_hvsrc(enum sti_hvsrc_orient orient
, int scale
,
658 struct sti_hqvdp_hvsrc
*hvsrc
)
660 const int *coef_c
, *coef_y
;
661 int shift_c
, shift_y
;
663 /* Get the appropriate coef tables */
664 if (scale
< SCALE_MAX_FOR_LEG_LUT_F
) {
665 coef_y
= coef_lut_f_y_legacy
;
666 coef_c
= coef_lut_f_c_legacy
;
667 shift_y
= SHIFT_LUT_F_Y_LEGACY
;
668 shift_c
= SHIFT_LUT_F_C_LEGACY
;
669 } else if (scale
< SCALE_MAX_FOR_LEG_LUT_E
) {
670 coef_y
= coef_lut_e_y_legacy
;
671 coef_c
= coef_lut_e_c_legacy
;
672 shift_y
= SHIFT_LUT_E_Y_LEGACY
;
673 shift_c
= SHIFT_LUT_E_C_LEGACY
;
674 } else if (scale
< SCALE_MAX_FOR_LEG_LUT_D
) {
675 coef_y
= coef_lut_d_y_legacy
;
676 coef_c
= coef_lut_d_c_legacy
;
677 shift_y
= SHIFT_LUT_D_Y_LEGACY
;
678 shift_c
= SHIFT_LUT_D_C_LEGACY
;
679 } else if (scale
< SCALE_MAX_FOR_LEG_LUT_C
) {
680 coef_y
= coef_lut_c_y_legacy
;
681 coef_c
= coef_lut_c_c_legacy
;
682 shift_y
= SHIFT_LUT_C_Y_LEGACY
;
683 shift_c
= SHIFT_LUT_C_C_LEGACY
;
684 } else if (scale
== SCALE_MAX_FOR_LEG_LUT_C
) {
685 coef_y
= coef_c
= coef_lut_b
;
686 shift_y
= shift_c
= SHIFT_LUT_B
;
688 coef_y
= coef_c
= coef_lut_a_legacy
;
689 shift_y
= shift_c
= SHIFT_LUT_A_LEGACY
;
692 if (orient
== HVSRC_HORI
) {
693 hvsrc
->hori_shift
= (shift_c
<< 16) | shift_y
;
694 memcpy(hvsrc
->yh_coef
, coef_y
, sizeof(hvsrc
->yh_coef
));
695 memcpy(hvsrc
->ch_coef
, coef_c
, sizeof(hvsrc
->ch_coef
));
697 hvsrc
->vert_shift
= (shift_c
<< 16) | shift_y
;
698 memcpy(hvsrc
->yv_coef
, coef_y
, sizeof(hvsrc
->yv_coef
));
699 memcpy(hvsrc
->cv_coef
, coef_c
, sizeof(hvsrc
->cv_coef
));
704 * sti_hqvdp_check_hw_scaling
705 * @hqvdp: hqvdp pointer
706 * @mode: display mode with timing constraints
707 * @src_w: source width
708 * @src_h: source height
709 * @dst_w: destination width
710 * @dst_h: destination height
712 * Check if the HW is able to perform the scaling request
713 * The firmware scaling limitation is "CEIL(1/Zy) <= FLOOR(LFW)" where:
714 * Zy = OutputHeight / InputHeight
715 * LFW = (Tx * IPClock) / (MaxNbCycles * Cp)
716 * Tx : Total video mode horizontal resolution
717 * IPClock : HQVDP IP clock (Mhz)
718 * MaxNbCycles: max(InputWidth, OutputWidth)
719 * Cp: Video mode pixel clock (Mhz)
722 * True if the HW can scale.
724 static bool sti_hqvdp_check_hw_scaling(struct sti_hqvdp
*hqvdp
,
725 struct drm_display_mode
*mode
,
726 int src_w
, int src_h
,
727 int dst_w
, int dst_h
)
732 lfw
= mode
->htotal
* (clk_get_rate(hqvdp
->clk
) / 1000000);
733 lfw
/= max(src_w
, dst_w
) * mode
->clock
/ 1000;
735 inv_zy
= DIV_ROUND_UP(src_h
, dst_h
);
737 return (inv_zy
<= lfw
) ? true : false;
742 * @hqvdp: hqvdp pointer
744 * Disables the HQVDP plane
746 static void sti_hqvdp_disable(struct sti_hqvdp
*hqvdp
)
750 DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&hqvdp
->plane
));
752 /* Unregister VTG Vsync callback */
753 if (sti_vtg_unregister_client(hqvdp
->vtg
, &hqvdp
->vtg_nb
))
754 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
756 /* Set next cmd to NULL */
757 writel(0, hqvdp
->regs
+ HQVDP_MBX_NEXT_CMD
);
759 for (i
= 0; i
< POLL_MAX_ATTEMPT
; i
++) {
760 if (readl(hqvdp
->regs
+ HQVDP_MBX_INFO_XP70
)
761 & INFO_XP70_FW_READY
)
763 msleep(POLL_DELAY_MS
);
766 /* VTG can stop now */
767 clk_disable_unprepare(hqvdp
->clk_pix_main
);
769 if (i
== POLL_MAX_ATTEMPT
)
770 DRM_ERROR("XP70 could not revert to idle\n");
772 hqvdp
->plane
.status
= STI_PLANE_DISABLED
;
777 * @nb: notifier block
778 * @evt: event message
779 * @data: private data
781 * Handle VTG Vsync event, display pending bottom field
786 int sti_hqvdp_vtg_cb(struct notifier_block
*nb
, unsigned long evt
, void *data
)
788 struct sti_hqvdp
*hqvdp
= container_of(nb
, struct sti_hqvdp
, vtg_nb
);
789 int btm_cmd_offset
, top_cmd_offest
;
790 struct sti_hqvdp_cmd
*btm_cmd
, *top_cmd
;
792 if ((evt
!= VTG_TOP_FIELD_EVENT
) && (evt
!= VTG_BOTTOM_FIELD_EVENT
)) {
793 DRM_DEBUG_DRIVER("Unknown event\n");
797 if (hqvdp
->plane
.status
== STI_PLANE_FLUSHING
) {
798 /* disable need to be synchronize on vsync event */
799 DRM_DEBUG_DRIVER("Vsync event received => disable %s\n",
800 sti_plane_to_str(&hqvdp
->plane
));
802 sti_hqvdp_disable(hqvdp
);
805 if (hqvdp
->btm_field_pending
) {
806 /* Create the btm field command from the current one */
807 btm_cmd_offset
= sti_hqvdp_get_free_cmd(hqvdp
);
808 top_cmd_offest
= sti_hqvdp_get_curr_cmd(hqvdp
);
809 if ((btm_cmd_offset
== -1) || (top_cmd_offest
== -1)) {
810 DRM_DEBUG_DRIVER("Warning: no cmd, will skip field\n");
814 btm_cmd
= hqvdp
->hqvdp_cmd
+ btm_cmd_offset
;
815 top_cmd
= hqvdp
->hqvdp_cmd
+ top_cmd_offest
;
817 memcpy(btm_cmd
, top_cmd
, sizeof(*btm_cmd
));
819 btm_cmd
->top
.config
= TOP_CONFIG_INTER_BTM
;
820 btm_cmd
->top
.current_luma
+=
821 btm_cmd
->top
.luma_src_pitch
/ 2;
822 btm_cmd
->top
.current_chroma
+=
823 btm_cmd
->top
.chroma_src_pitch
/ 2;
825 /* Post the command to mailbox */
826 writel(hqvdp
->hqvdp_cmd_paddr
+ btm_cmd_offset
,
827 hqvdp
->regs
+ HQVDP_MBX_NEXT_CMD
);
829 hqvdp
->btm_field_pending
= false;
831 dev_dbg(hqvdp
->dev
, "%s Posted command:0x%x\n",
832 __func__
, hqvdp
->hqvdp_cmd_paddr
);
834 sti_plane_update_fps(&hqvdp
->plane
, false, true);
840 static void sti_hqvdp_init(struct sti_hqvdp
*hqvdp
)
845 hqvdp
->vtg_nb
.notifier_call
= sti_hqvdp_vtg_cb
;
847 /* Allocate memory for the VDP commands */
848 size
= NB_VDP_CMD
* sizeof(struct sti_hqvdp_cmd
);
849 hqvdp
->hqvdp_cmd
= dma_alloc_wc(hqvdp
->dev
, size
,
851 GFP_KERNEL
| GFP_DMA
);
852 if (!hqvdp
->hqvdp_cmd
) {
853 DRM_ERROR("Failed to allocate memory for VDP cmd\n");
857 hqvdp
->hqvdp_cmd_paddr
= (u32
)dma_addr
;
858 memset(hqvdp
->hqvdp_cmd
, 0, size
);
861 static void sti_hqvdp_init_plugs(struct sti_hqvdp
*hqvdp
)
863 /* Configure Plugs (same for RD & WR) */
864 writel(PLUG_PAGE_SIZE_256
, hqvdp
->regs
+ HQVDP_RD_PLUG_PAGE_SIZE
);
865 writel(PLUG_MIN_OPC_8
, hqvdp
->regs
+ HQVDP_RD_PLUG_MIN_OPC
);
866 writel(PLUG_MAX_OPC_64
, hqvdp
->regs
+ HQVDP_RD_PLUG_MAX_OPC
);
867 writel(PLUG_MAX_CHK_2X
, hqvdp
->regs
+ HQVDP_RD_PLUG_MAX_CHK
);
868 writel(PLUG_MAX_MSG_1X
, hqvdp
->regs
+ HQVDP_RD_PLUG_MAX_MSG
);
869 writel(PLUG_MIN_SPACE_1
, hqvdp
->regs
+ HQVDP_RD_PLUG_MIN_SPACE
);
870 writel(PLUG_CONTROL_ENABLE
, hqvdp
->regs
+ HQVDP_RD_PLUG_CONTROL
);
872 writel(PLUG_PAGE_SIZE_256
, hqvdp
->regs
+ HQVDP_WR_PLUG_PAGE_SIZE
);
873 writel(PLUG_MIN_OPC_8
, hqvdp
->regs
+ HQVDP_WR_PLUG_MIN_OPC
);
874 writel(PLUG_MAX_OPC_64
, hqvdp
->regs
+ HQVDP_WR_PLUG_MAX_OPC
);
875 writel(PLUG_MAX_CHK_2X
, hqvdp
->regs
+ HQVDP_WR_PLUG_MAX_CHK
);
876 writel(PLUG_MAX_MSG_1X
, hqvdp
->regs
+ HQVDP_WR_PLUG_MAX_MSG
);
877 writel(PLUG_MIN_SPACE_1
, hqvdp
->regs
+ HQVDP_WR_PLUG_MIN_SPACE
);
878 writel(PLUG_CONTROL_ENABLE
, hqvdp
->regs
+ HQVDP_WR_PLUG_CONTROL
);
882 * sti_hqvdp_start_xp70
883 * @hqvdp: hqvdp pointer
885 * Run the xP70 initialization sequence
887 static void sti_hqvdp_start_xp70(struct sti_hqvdp
*hqvdp
)
889 const struct firmware
*firmware
;
890 u32
*fw_rd_plug
, *fw_wr_plug
, *fw_pmem
, *fw_dmem
;
900 DRM_DEBUG_DRIVER("\n");
902 if (hqvdp
->xp70_initialized
) {
903 DRM_DEBUG_DRIVER("HQVDP XP70 already initialized\n");
907 /* Request firmware */
908 if (request_firmware(&firmware
, HQVDP_FMW_NAME
, hqvdp
->dev
)) {
909 DRM_ERROR("Can't get HQVDP firmware\n");
913 /* Check firmware parts */
915 DRM_ERROR("Firmware not available\n");
919 header
= (struct fw_header
*)firmware
->data
;
920 if (firmware
->size
< sizeof(*header
)) {
921 DRM_ERROR("Invalid firmware size (%d)\n", firmware
->size
);
924 if ((sizeof(*header
) + header
->rd_size
+ header
->wr_size
+
925 header
->pmem_size
+ header
->dmem_size
) != firmware
->size
) {
926 DRM_ERROR("Invalid fmw structure (%d+%d+%d+%d+%d != %d)\n",
927 sizeof(*header
), header
->rd_size
, header
->wr_size
,
928 header
->pmem_size
, header
->dmem_size
,
933 data
= (u8
*)firmware
->data
;
934 data
+= sizeof(*header
);
935 fw_rd_plug
= (void *)data
;
936 data
+= header
->rd_size
;
937 fw_wr_plug
= (void *)data
;
938 data
+= header
->wr_size
;
939 fw_pmem
= (void *)data
;
940 data
+= header
->pmem_size
;
941 fw_dmem
= (void *)data
;
944 if (clk_prepare_enable(hqvdp
->clk
))
945 DRM_ERROR("Failed to prepare/enable HQVDP clk\n");
948 writel(SW_RESET_CTRL_FULL
, hqvdp
->regs
+ HQVDP_MBX_SW_RESET_CTRL
);
950 for (i
= 0; i
< POLL_MAX_ATTEMPT
; i
++) {
951 if (readl(hqvdp
->regs
+ HQVDP_MBX_STARTUP_CTRL1
)
952 & STARTUP_CTRL1_RST_DONE
)
954 msleep(POLL_DELAY_MS
);
956 if (i
== POLL_MAX_ATTEMPT
) {
957 DRM_ERROR("Could not reset\n");
961 /* Init Read & Write plugs */
962 for (i
= 0; i
< header
->rd_size
/ 4; i
++)
963 writel(fw_rd_plug
[i
], hqvdp
->regs
+ HQVDP_RD_PLUG
+ i
* 4);
964 for (i
= 0; i
< header
->wr_size
/ 4; i
++)
965 writel(fw_wr_plug
[i
], hqvdp
->regs
+ HQVDP_WR_PLUG
+ i
* 4);
967 sti_hqvdp_init_plugs(hqvdp
);
969 /* Authorize Idle Mode */
970 writel(STARTUP_CTRL1_AUTH_IDLE
, hqvdp
->regs
+ HQVDP_MBX_STARTUP_CTRL1
);
972 /* Prevent VTG interruption during the boot */
973 writel(SOFT_VSYNC_SW_CTRL_IRQ
, hqvdp
->regs
+ HQVDP_MBX_SOFT_VSYNC
);
974 writel(0, hqvdp
->regs
+ HQVDP_MBX_NEXT_CMD
);
976 /* Download PMEM & DMEM */
977 for (i
= 0; i
< header
->pmem_size
/ 4; i
++)
978 writel(fw_pmem
[i
], hqvdp
->regs
+ HQVDP_PMEM
+ i
* 4);
979 for (i
= 0; i
< header
->dmem_size
/ 4; i
++)
980 writel(fw_dmem
[i
], hqvdp
->regs
+ HQVDP_DMEM
+ i
* 4);
983 writel(STARTUP_CTRL2_FETCH_EN
, hqvdp
->regs
+ HQVDP_MBX_STARTUP_CTRL2
);
985 /* Wait end of boot */
986 for (i
= 0; i
< POLL_MAX_ATTEMPT
; i
++) {
987 if (readl(hqvdp
->regs
+ HQVDP_MBX_INFO_XP70
)
988 & INFO_XP70_FW_READY
)
990 msleep(POLL_DELAY_MS
);
992 if (i
== POLL_MAX_ATTEMPT
) {
993 DRM_ERROR("Could not boot\n");
998 writel(SOFT_VSYNC_HW
, hqvdp
->regs
+ HQVDP_MBX_SOFT_VSYNC
);
1000 DRM_INFO("HQVDP XP70 initialized\n");
1002 hqvdp
->xp70_initialized
= true;
1005 release_firmware(firmware
);
1008 static int sti_hqvdp_atomic_check(struct drm_plane
*drm_plane
,
1009 struct drm_plane_state
*state
)
1011 struct sti_plane
*plane
= to_sti_plane(drm_plane
);
1012 struct sti_hqvdp
*hqvdp
= to_sti_hqvdp(plane
);
1013 struct drm_crtc
*crtc
= state
->crtc
;
1014 struct drm_framebuffer
*fb
= state
->fb
;
1015 bool first_prepare
= plane
->status
== STI_PLANE_DISABLED
? true : false;
1016 struct drm_crtc_state
*crtc_state
;
1017 struct drm_display_mode
*mode
;
1018 int dst_x
, dst_y
, dst_w
, dst_h
;
1019 int src_x
, src_y
, src_w
, src_h
;
1021 /* no need for further checks if the plane is being disabled */
1025 crtc_state
= drm_atomic_get_crtc_state(state
->state
, crtc
);
1026 mode
= &crtc_state
->mode
;
1027 dst_x
= state
->crtc_x
;
1028 dst_y
= state
->crtc_y
;
1029 dst_w
= clamp_val(state
->crtc_w
, 0, mode
->crtc_hdisplay
- dst_x
);
1030 dst_h
= clamp_val(state
->crtc_h
, 0, mode
->crtc_vdisplay
- dst_y
);
1031 /* src_x are in 16.16 format */
1032 src_x
= state
->src_x
>> 16;
1033 src_y
= state
->src_y
>> 16;
1034 src_w
= state
->src_w
>> 16;
1035 src_h
= state
->src_h
>> 16;
1037 if (!sti_hqvdp_check_hw_scaling(hqvdp
, mode
,
1040 DRM_ERROR("Scaling beyond HW capabilities\n");
1044 if (!drm_fb_cma_get_gem_obj(fb
, 0)) {
1045 DRM_ERROR("Can't get CMA GEM object for fb\n");
1050 * Input / output size
1051 * Align to upper even value
1053 dst_w
= ALIGN(dst_w
, 2);
1054 dst_h
= ALIGN(dst_h
, 2);
1056 if ((src_w
> MAX_WIDTH
) || (src_w
< MIN_WIDTH
) ||
1057 (src_h
> MAX_HEIGHT
) || (src_h
< MIN_HEIGHT
) ||
1058 (dst_w
> MAX_WIDTH
) || (dst_w
< MIN_WIDTH
) ||
1059 (dst_h
> MAX_HEIGHT
) || (dst_h
< MIN_HEIGHT
)) {
1060 DRM_ERROR("Invalid in/out size %dx%d -> %dx%d\n",
1066 if (first_prepare
) {
1067 /* Start HQVDP XP70 coprocessor */
1068 sti_hqvdp_start_xp70(hqvdp
);
1070 /* Prevent VTG shutdown */
1071 if (clk_prepare_enable(hqvdp
->clk_pix_main
)) {
1072 DRM_ERROR("Failed to prepare/enable pix main clk\n");
1076 /* Register VTG Vsync callback to handle bottom fields */
1077 if (sti_vtg_register_client(hqvdp
->vtg
,
1080 DRM_ERROR("Cannot register VTG notifier\n");
1085 DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n",
1086 crtc
->base
.id
, sti_mixer_to_str(to_sti_mixer(crtc
)),
1087 drm_plane
->base
.id
, sti_plane_to_str(plane
));
1088 DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n",
1089 sti_plane_to_str(plane
),
1090 dst_w
, dst_h
, dst_x
, dst_y
,
1091 src_w
, src_h
, src_x
, src_y
);
1096 static void sti_hqvdp_atomic_update(struct drm_plane
*drm_plane
,
1097 struct drm_plane_state
*oldstate
)
1099 struct drm_plane_state
*state
= drm_plane
->state
;
1100 struct sti_plane
*plane
= to_sti_plane(drm_plane
);
1101 struct sti_hqvdp
*hqvdp
= to_sti_hqvdp(plane
);
1102 struct drm_crtc
*crtc
= state
->crtc
;
1103 struct drm_framebuffer
*fb
= state
->fb
;
1104 struct drm_display_mode
*mode
;
1105 int dst_x
, dst_y
, dst_w
, dst_h
;
1106 int src_x
, src_y
, src_w
, src_h
;
1107 struct drm_gem_cma_object
*cma_obj
;
1108 struct sti_hqvdp_cmd
*cmd
;
1109 int scale_h
, scale_v
;
1116 dst_x
= state
->crtc_x
;
1117 dst_y
= state
->crtc_y
;
1118 dst_w
= clamp_val(state
->crtc_w
, 0, mode
->crtc_hdisplay
- dst_x
);
1119 dst_h
= clamp_val(state
->crtc_h
, 0, mode
->crtc_vdisplay
- dst_y
);
1120 /* src_x are in 16.16 format */
1121 src_x
= state
->src_x
>> 16;
1122 src_y
= state
->src_y
>> 16;
1123 src_w
= state
->src_w
>> 16;
1124 src_h
= state
->src_h
>> 16;
1126 cmd_offset
= sti_hqvdp_get_free_cmd(hqvdp
);
1127 if (cmd_offset
== -1) {
1128 DRM_DEBUG_DRIVER("Warning: no cmd, will skip frame\n");
1131 cmd
= hqvdp
->hqvdp_cmd
+ cmd_offset
;
1133 /* Static parameters, defaulting to progressive mode */
1134 cmd
->top
.config
= TOP_CONFIG_PROGRESSIVE
;
1135 cmd
->top
.mem_format
= TOP_MEM_FORMAT_DFLT
;
1136 cmd
->hvsrc
.param_ctrl
= HVSRC_PARAM_CTRL_DFLT
;
1137 cmd
->csdi
.config
= CSDI_CONFIG_PROG
;
1139 /* VC1RE, FMD bypassed : keep everything set to 0
1140 * IQI/P2I bypassed */
1141 cmd
->iqi
.config
= IQI_CONFIG_DFLT
;
1142 cmd
->iqi
.con_bri
= IQI_CON_BRI_DFLT
;
1143 cmd
->iqi
.sat_gain
= IQI_SAT_GAIN_DFLT
;
1144 cmd
->iqi
.pxf_conf
= IQI_PXF_CONF_DFLT
;
1146 cma_obj
= drm_fb_cma_get_gem_obj(fb
, 0);
1148 DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb
->base
.id
,
1149 (char *)&fb
->pixel_format
,
1150 (unsigned long)cma_obj
->paddr
);
1152 /* Buffer planes address */
1153 cmd
->top
.current_luma
= (u32
)cma_obj
->paddr
+ fb
->offsets
[0];
1154 cmd
->top
.current_chroma
= (u32
)cma_obj
->paddr
+ fb
->offsets
[1];
1157 cmd
->top
.luma_processed_pitch
= fb
->pitches
[0];
1158 cmd
->top
.luma_src_pitch
= fb
->pitches
[0];
1159 cmd
->top
.chroma_processed_pitch
= fb
->pitches
[1];
1160 cmd
->top
.chroma_src_pitch
= fb
->pitches
[1];
1162 /* Input / output size
1163 * Align to upper even value */
1164 dst_w
= ALIGN(dst_w
, 2);
1165 dst_h
= ALIGN(dst_h
, 2);
1167 cmd
->top
.input_viewport_size
= src_h
<< 16 | src_w
;
1168 cmd
->top
.input_frame_size
= src_h
<< 16 | src_w
;
1169 cmd
->hvsrc
.output_picture_size
= dst_h
<< 16 | dst_w
;
1170 cmd
->top
.input_viewport_ori
= src_y
<< 16 | src_x
;
1172 /* Handle interlaced */
1173 if (fb
->flags
& DRM_MODE_FB_INTERLACED
) {
1174 /* Top field to display */
1175 cmd
->top
.config
= TOP_CONFIG_INTER_TOP
;
1177 /* Update pitches and vert size */
1178 cmd
->top
.input_frame_size
= (src_h
/ 2) << 16 | src_w
;
1179 cmd
->top
.luma_processed_pitch
*= 2;
1180 cmd
->top
.luma_src_pitch
*= 2;
1181 cmd
->top
.chroma_processed_pitch
*= 2;
1182 cmd
->top
.chroma_src_pitch
*= 2;
1184 /* Enable directional deinterlacing processing */
1185 cmd
->csdi
.config
= CSDI_CONFIG_INTER_DIR
;
1186 cmd
->csdi
.config2
= CSDI_CONFIG2_DFLT
;
1187 cmd
->csdi
.dcdi_config
= CSDI_DCDI_CONFIG_DFLT
;
1190 /* Update hvsrc lut coef */
1191 scale_h
= SCALE_FACTOR
* dst_w
/ src_w
;
1192 sti_hqvdp_update_hvsrc(HVSRC_HORI
, scale_h
, &cmd
->hvsrc
);
1194 scale_v
= SCALE_FACTOR
* dst_h
/ src_h
;
1195 sti_hqvdp_update_hvsrc(HVSRC_VERT
, scale_v
, &cmd
->hvsrc
);
1197 writel(hqvdp
->hqvdp_cmd_paddr
+ cmd_offset
,
1198 hqvdp
->regs
+ HQVDP_MBX_NEXT_CMD
);
1200 /* Interlaced : get ready to display the bottom field at next Vsync */
1201 if (fb
->flags
& DRM_MODE_FB_INTERLACED
)
1202 hqvdp
->btm_field_pending
= true;
1204 dev_dbg(hqvdp
->dev
, "%s Posted command:0x%x\n",
1205 __func__
, hqvdp
->hqvdp_cmd_paddr
+ cmd_offset
);
1207 sti_plane_update_fps(plane
, true, true);
1209 plane
->status
= STI_PLANE_UPDATED
;
1212 static void sti_hqvdp_atomic_disable(struct drm_plane
*drm_plane
,
1213 struct drm_plane_state
*oldstate
)
1215 struct sti_plane
*plane
= to_sti_plane(drm_plane
);
1217 if (!drm_plane
->crtc
) {
1218 DRM_DEBUG_DRIVER("drm plane:%d not enabled\n",
1219 drm_plane
->base
.id
);
1223 DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n",
1224 drm_plane
->crtc
->base
.id
,
1225 sti_mixer_to_str(to_sti_mixer(drm_plane
->crtc
)),
1226 drm_plane
->base
.id
, sti_plane_to_str(plane
));
1228 plane
->status
= STI_PLANE_DISABLING
;
1231 static const struct drm_plane_helper_funcs sti_hqvdp_helpers_funcs
= {
1232 .atomic_check
= sti_hqvdp_atomic_check
,
1233 .atomic_update
= sti_hqvdp_atomic_update
,
1234 .atomic_disable
= sti_hqvdp_atomic_disable
,
1237 static void sti_hqvdp_destroy(struct drm_plane
*drm_plane
)
1239 DRM_DEBUG_DRIVER("\n");
1241 drm_plane_helper_disable(drm_plane
);
1242 drm_plane_cleanup(drm_plane
);
1245 static int sti_hqvdp_late_register(struct drm_plane
*drm_plane
)
1247 struct sti_plane
*plane
= to_sti_plane(drm_plane
);
1248 struct sti_hqvdp
*hqvdp
= to_sti_hqvdp(plane
);
1250 return hqvdp_debugfs_init(hqvdp
, drm_plane
->dev
->primary
);
1253 struct drm_plane_funcs sti_hqvdp_plane_helpers_funcs
= {
1254 .update_plane
= drm_atomic_helper_update_plane
,
1255 .disable_plane
= drm_atomic_helper_disable_plane
,
1256 .destroy
= sti_hqvdp_destroy
,
1257 .set_property
= sti_plane_set_property
,
1258 .reset
= drm_atomic_helper_plane_reset
,
1259 .atomic_duplicate_state
= drm_atomic_helper_plane_duplicate_state
,
1260 .atomic_destroy_state
= drm_atomic_helper_plane_destroy_state
,
1261 .late_register
= sti_hqvdp_late_register
,
1264 static struct drm_plane
*sti_hqvdp_create(struct drm_device
*drm_dev
,
1265 struct device
*dev
, int desc
)
1267 struct sti_hqvdp
*hqvdp
= dev_get_drvdata(dev
);
1270 hqvdp
->plane
.desc
= desc
;
1271 hqvdp
->plane
.status
= STI_PLANE_DISABLED
;
1273 sti_hqvdp_init(hqvdp
);
1275 res
= drm_universal_plane_init(drm_dev
, &hqvdp
->plane
.drm_plane
, 1,
1276 &sti_hqvdp_plane_helpers_funcs
,
1277 hqvdp_supported_formats
,
1278 ARRAY_SIZE(hqvdp_supported_formats
),
1279 DRM_PLANE_TYPE_OVERLAY
, NULL
);
1281 DRM_ERROR("Failed to initialize universal plane\n");
1285 drm_plane_helper_add(&hqvdp
->plane
.drm_plane
, &sti_hqvdp_helpers_funcs
);
1287 sti_plane_init_property(&hqvdp
->plane
, DRM_PLANE_TYPE_OVERLAY
);
1289 return &hqvdp
->plane
.drm_plane
;
1292 int sti_hqvdp_bind(struct device
*dev
, struct device
*master
, void *data
)
1294 struct sti_hqvdp
*hqvdp
= dev_get_drvdata(dev
);
1295 struct drm_device
*drm_dev
= data
;
1296 struct drm_plane
*plane
;
1298 DRM_DEBUG_DRIVER("\n");
1300 hqvdp
->drm_dev
= drm_dev
;
1302 /* Create HQVDP plane once xp70 is initialized */
1303 plane
= sti_hqvdp_create(drm_dev
, hqvdp
->dev
, STI_HQVDP_0
);
1305 DRM_ERROR("Can't create HQVDP plane\n");
1310 static void sti_hqvdp_unbind(struct device
*dev
,
1311 struct device
*master
, void *data
)
1316 static const struct component_ops sti_hqvdp_ops
= {
1317 .bind
= sti_hqvdp_bind
,
1318 .unbind
= sti_hqvdp_unbind
,
1321 static int sti_hqvdp_probe(struct platform_device
*pdev
)
1323 struct device
*dev
= &pdev
->dev
;
1324 struct device_node
*vtg_np
;
1325 struct sti_hqvdp
*hqvdp
;
1326 struct resource
*res
;
1328 DRM_DEBUG_DRIVER("\n");
1330 hqvdp
= devm_kzalloc(dev
, sizeof(*hqvdp
), GFP_KERNEL
);
1332 DRM_ERROR("Failed to allocate HQVDP context\n");
1338 /* Get Memory resources */
1339 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1341 DRM_ERROR("Get memory resource failed\n");
1344 hqvdp
->regs
= devm_ioremap(dev
, res
->start
, resource_size(res
));
1345 if (hqvdp
->regs
== NULL
) {
1346 DRM_ERROR("Register mapping failed\n");
1350 /* Get clock resources */
1351 hqvdp
->clk
= devm_clk_get(dev
, "hqvdp");
1352 hqvdp
->clk_pix_main
= devm_clk_get(dev
, "pix_main");
1353 if (IS_ERR(hqvdp
->clk
) || IS_ERR(hqvdp
->clk_pix_main
)) {
1354 DRM_ERROR("Cannot get clocks\n");
1358 /* Get reset resources */
1359 hqvdp
->reset
= devm_reset_control_get(dev
, "hqvdp");
1360 if (!IS_ERR(hqvdp
->reset
))
1361 reset_control_deassert(hqvdp
->reset
);
1363 vtg_np
= of_parse_phandle(pdev
->dev
.of_node
, "st,vtg", 0);
1365 hqvdp
->vtg
= of_vtg_find(vtg_np
);
1366 of_node_put(vtg_np
);
1368 platform_set_drvdata(pdev
, hqvdp
);
1370 return component_add(&pdev
->dev
, &sti_hqvdp_ops
);
1373 static int sti_hqvdp_remove(struct platform_device
*pdev
)
1375 component_del(&pdev
->dev
, &sti_hqvdp_ops
);
1379 static struct of_device_id hqvdp_of_match
[] = {
1380 { .compatible
= "st,stih407-hqvdp", },
1383 MODULE_DEVICE_TABLE(of
, hqvdp_of_match
);
1385 struct platform_driver sti_hqvdp_driver
= {
1387 .name
= "sti-hqvdp",
1388 .owner
= THIS_MODULE
,
1389 .of_match_table
= hqvdp_of_match
,
1391 .probe
= sti_hqvdp_probe
,
1392 .remove
= sti_hqvdp_remove
,
1395 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
1396 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
1397 MODULE_LICENSE("GPL");