drivers/gpu/drm/sti/sti_mixer.c

   1 /*
   2  * Copyright (C) STMicroelectronics SA 2014
   3  * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
   4  *          Fabien Dessenne <fabien.dessenne@st.com>
   5  *          for STMicroelectronics.
   6  * License terms:  GNU General Public License (GPL), version 2
   7  */
   8
   9 #include "sti_compositor.h"
  10 #include "sti_mixer.h"
  11 #include "sti_vtg.h"
  12
  13 /* Identity: G=Y , B=Cb , R=Cr */
  14 static const u32 mixerColorSpaceMatIdentity[] = {
  15         0x10000000, 0x00000000, 0x10000000, 0x00001000,
  16         0x00000000, 0x00000000, 0x00000000, 0x00000000
  17 };
  18
  19 /* regs offset */
  20 #define GAM_MIXER_CTL      0x00
  21 #define GAM_MIXER_BKC      0x04
  22 #define GAM_MIXER_BCO      0x0C
  23 #define GAM_MIXER_BCS      0x10
  24 #define GAM_MIXER_AVO      0x28
  25 #define GAM_MIXER_AVS      0x2C
  26 #define GAM_MIXER_CRB      0x34
  27 #define GAM_MIXER_ACT      0x38
  28 #define GAM_MIXER_MBP      0x3C
  29 #define GAM_MIXER_MX0      0x80
  30
  31 /* id for depth of CRB reg */
  32 #define GAM_DEPTH_VID0_ID  1
  33 #define GAM_DEPTH_VID1_ID  2
  34 #define GAM_DEPTH_GDP0_ID  3
  35 #define GAM_DEPTH_GDP1_ID  4
  36 #define GAM_DEPTH_GDP2_ID  5
  37 #define GAM_DEPTH_GDP3_ID  6
  38 #define GAM_DEPTH_MASK_ID  7
  39
  40 /* mask in CTL reg */
  41 #define GAM_CTL_BACK_MASK  BIT(0)
  42 #define GAM_CTL_VID0_MASK  BIT(1)
  43 #define GAM_CTL_VID1_MASK  BIT(2)
  44 #define GAM_CTL_GDP0_MASK  BIT(3)
  45 #define GAM_CTL_GDP1_MASK  BIT(4)
  46 #define GAM_CTL_GDP2_MASK  BIT(5)
  47 #define GAM_CTL_GDP3_MASK  BIT(6)
  48
  49 const char *sti_mixer_to_str(struct sti_mixer *mixer)
  50 {
  51         switch (mixer->id) {
  52         case STI_MIXER_MAIN:
  53                 return "MAIN_MIXER";
  54         case STI_MIXER_AUX:
  55                 return "AUX_MIXER";
  56         default:
  57                 return "<UNKNOWN MIXER>";
  58         }
  59 }
  60
  61 static inline u32 sti_mixer_reg_read(struct sti_mixer *mixer, u32 reg_id)
  62 {
  63         return readl(mixer->regs + reg_id);
  64 }
  65
  66 static inline void sti_mixer_reg_write(struct sti_mixer *mixer,
  67                                        u32 reg_id, u32 val)
  68 {
  69         writel(val, mixer->regs + reg_id);
  70 }
  71
  72 void sti_mixer_set_background_status(struct sti_mixer *mixer, bool enable)
  73 {
  74         u32 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
  75
  76         val &= ~GAM_CTL_BACK_MASK;
  77         val |= enable;
  78         sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
  79 }
  80
  81 static void sti_mixer_set_background_color(struct sti_mixer *mixer,
  82                                            u8 red, u8 green, u8 blue)
  83 {
  84         u32 val = (red << 16) | (green << 8) | blue;
  85
  86         sti_mixer_reg_write(mixer, GAM_MIXER_BKC, val);
  87 }
  88
  89 static void sti_mixer_set_background_area(struct sti_mixer *mixer,
  90                                           struct drm_display_mode *mode)
  91 {
  92         u32 ydo, xdo, yds, xds;
  93
  94         ydo = sti_vtg_get_line_number(*mode, 0);
  95         yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
  96         xdo = sti_vtg_get_pixel_number(*mode, 0);
  97         xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
  98
  99         sti_mixer_reg_write(mixer, GAM_MIXER_BCO, ydo << 16 | xdo);
 100         sti_mixer_reg_write(mixer, GAM_MIXER_BCS, yds << 16 | xds);
 101 }
 102
 103 int sti_mixer_set_layer_depth(struct sti_mixer *mixer, struct sti_layer *layer)
 104 {
 105         int layer_id = 0, depth = layer->zorder;
 106         u32 mask, val;
 107
 108         if (depth >= GAM_MIXER_NB_DEPTH_LEVEL)
 109                 return 1;
 110
 111         switch (layer->desc) {
 112         case STI_GDP_0:
 113                 layer_id = GAM_DEPTH_GDP0_ID;
 114                 break;
 115         case STI_GDP_1:
 116                 layer_id = GAM_DEPTH_GDP1_ID;
 117                 break;
 118         case STI_GDP_2:
 119                 layer_id = GAM_DEPTH_GDP2_ID;
 120                 break;
 121         case STI_GDP_3:
 122                 layer_id = GAM_DEPTH_GDP3_ID;
 123                 break;
 124         case STI_VID_0:
 125                 layer_id = GAM_DEPTH_VID0_ID;
 126                 break;
 127         case STI_VID_1:
 128                 layer_id = GAM_DEPTH_VID1_ID;
 129                 break;
 130         default:
 131                 DRM_ERROR("Unknown layer %d\n", layer->desc);
 132                 return 1;
 133         }
 134         mask = GAM_DEPTH_MASK_ID << (3 * depth);
 135         layer_id = layer_id << (3 * depth);
 136
 137         DRM_DEBUG_DRIVER("%s %s depth=%d\n", sti_mixer_to_str(mixer),
 138                          sti_layer_to_str(layer), depth);
 139         dev_dbg(mixer->dev, "GAM_MIXER_CRB val 0x%x mask 0x%x\n",
 140                 layer_id, mask);
 141
 142         val = sti_mixer_reg_read(mixer, GAM_MIXER_CRB);
 143         val &= ~mask;
 144         val |= layer_id;
 145         sti_mixer_reg_write(mixer, GAM_MIXER_CRB, val);
 146
 147         dev_dbg(mixer->dev, "Read GAM_MIXER_CRB 0x%x\n",
 148                 sti_mixer_reg_read(mixer, GAM_MIXER_CRB));
 149         return 0;
 150 }
 151
 152 int sti_mixer_active_video_area(struct sti_mixer *mixer,
 153                                 struct drm_display_mode *mode)
 154 {
 155         u32 ydo, xdo, yds, xds;
 156
 157         ydo = sti_vtg_get_line_number(*mode, 0);
 158         yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
 159         xdo = sti_vtg_get_pixel_number(*mode, 0);
 160         xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
 161
 162         DRM_DEBUG_DRIVER("%s active video area xdo:%d ydo:%d xds:%d yds:%d\n",
 163                          sti_mixer_to_str(mixer), xdo, ydo, xds, yds);
 164         sti_mixer_reg_write(mixer, GAM_MIXER_AVO, ydo << 16 | xdo);
 165         sti_mixer_reg_write(mixer, GAM_MIXER_AVS, yds << 16 | xds);
 166
 167         sti_mixer_set_background_color(mixer, 0xFF, 0, 0);
 168
 169         sti_mixer_set_background_area(mixer, mode);
 170         sti_mixer_set_background_status(mixer, true);
 171         return 0;
 172 }
 173
 174 static u32 sti_mixer_get_layer_mask(struct sti_layer *layer)
 175 {
 176         switch (layer->desc) {
 177         case STI_BACK:
 178                 return GAM_CTL_BACK_MASK;
 179         case STI_GDP_0:
 180                 return GAM_CTL_GDP0_MASK;
 181         case STI_GDP_1:
 182                 return GAM_CTL_GDP1_MASK;
 183         case STI_GDP_2:
 184                 return GAM_CTL_GDP2_MASK;
 185         case STI_GDP_3:
 186                 return GAM_CTL_GDP3_MASK;
 187         case STI_VID_0:
 188                 return GAM_CTL_VID0_MASK;
 189         case STI_VID_1:
 190                 return GAM_CTL_VID1_MASK;
 191         default:
 192                 return 0;
 193         }
 194 }
 195
 196 int sti_mixer_set_layer_status(struct sti_mixer *mixer,
 197                                struct sti_layer *layer, bool status)
 198 {
 199         u32 mask, val;
 200
 201         DRM_DEBUG_DRIVER("%s %s %s\n", status ? "enable" : "disable",
 202                          sti_mixer_to_str(mixer), sti_layer_to_str(layer));
 203
 204         mask = sti_mixer_get_layer_mask(layer);
 205         if (!mask) {
 206                 DRM_ERROR("Can not find layer mask\n");
 207                 return -EINVAL;
 208         }
 209
 210         val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
 211         val &= ~mask;
 212         val |= status ? mask : 0;
 213         sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
 214
 215         return 0;
 216 }
 217
 218 void sti_mixer_clear_all_layers(struct sti_mixer *mixer)
 219 {
 220         u32 val;
 221
 222         DRM_DEBUG_DRIVER("%s clear all layer\n", sti_mixer_to_str(mixer));
 223         val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL) & 0xFFFF0000;
 224         sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
 225 }
 226
 227 void sti_mixer_set_matrix(struct sti_mixer *mixer)
 228 {
 229         unsigned int i;
 230
 231         for (i = 0; i < ARRAY_SIZE(mixerColorSpaceMatIdentity); i++)
 232                 sti_mixer_reg_write(mixer, GAM_MIXER_MX0 + (i * 4),
 233                                     mixerColorSpaceMatIdentity[i]);
 234 }
 235
 236 struct sti_mixer *sti_mixer_create(struct device *dev, int id,
 237                                    void __iomem *baseaddr)
 238 {
 239         struct sti_mixer *mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL);
 240         struct device_node *np = dev->of_node;
 241
 242         dev_dbg(dev, "%s\n", __func__);
 243         if (!mixer) {
 244                 DRM_ERROR("Failed to allocated memory for mixer\n");
 245                 return NULL;
 246         }
 247         mixer->regs = baseaddr;
 248         mixer->dev = dev;
 249         mixer->id = id;
 250
 251         if (of_device_is_compatible(np, "st,stih416-compositor"))
 252                 sti_mixer_set_matrix(mixer);
 253
 254         DRM_DEBUG_DRIVER("%s created. Regs=%p\n",
 255                          sti_mixer_to_str(mixer), mixer->regs);
 256
 257         return mixer;
 258 }