drivers/gpu/drm/sti/sti_mixer.c

   1 /*
   2  * Copyright (C) STMicroelectronics SA 2014
   3  * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
   4  *          Fabien Dessenne <fabien.dessenne@st.com>
   5  *          for STMicroelectronics.
   6  * License terms:  GNU General Public License (GPL), version 2
   7  */
   8 #include <linux/seq_file.h>
   9
  10 #include "sti_compositor.h"
  11 #include "sti_mixer.h"
  12 #include "sti_vtg.h"
  13
  14 /* Module parameter to set the background color of the mixer */
  15 static unsigned int bkg_color = 0x000000;
  16 MODULE_PARM_DESC(bkgcolor, "Value of the background color 0xRRGGBB");
  17 module_param_named(bkgcolor, bkg_color, int, 0644);
  18
  19 /* Identity: G=Y , B=Cb , R=Cr */
  20 static const u32 mixerColorSpaceMatIdentity[] = {
  21         0x10000000, 0x00000000, 0x10000000, 0x00001000,
  22         0x00000000, 0x00000000, 0x00000000, 0x00000000
  23 };
  24
  25 /* regs offset */
  26 #define GAM_MIXER_CTL      0x00
  27 #define GAM_MIXER_BKC      0x04
  28 #define GAM_MIXER_BCO      0x0C
  29 #define GAM_MIXER_BCS      0x10
  30 #define GAM_MIXER_AVO      0x28
  31 #define GAM_MIXER_AVS      0x2C
  32 #define GAM_MIXER_CRB      0x34
  33 #define GAM_MIXER_ACT      0x38
  34 #define GAM_MIXER_MBP      0x3C
  35 #define GAM_MIXER_MX0      0x80
  36
  37 /* id for depth of CRB reg */
  38 #define GAM_DEPTH_VID0_ID  1
  39 #define GAM_DEPTH_VID1_ID  2
  40 #define GAM_DEPTH_GDP0_ID  3
  41 #define GAM_DEPTH_GDP1_ID  4
  42 #define GAM_DEPTH_GDP2_ID  5
  43 #define GAM_DEPTH_GDP3_ID  6
  44 #define GAM_DEPTH_MASK_ID  7
  45
  46 /* mask in CTL reg */
  47 #define GAM_CTL_BACK_MASK  BIT(0)
  48 #define GAM_CTL_VID0_MASK  BIT(1)
  49 #define GAM_CTL_VID1_MASK  BIT(2)
  50 #define GAM_CTL_GDP0_MASK  BIT(3)
  51 #define GAM_CTL_GDP1_MASK  BIT(4)
  52 #define GAM_CTL_GDP2_MASK  BIT(5)
  53 #define GAM_CTL_GDP3_MASK  BIT(6)
  54 #define GAM_CTL_CURSOR_MASK BIT(9)
  55
  56 const char *sti_mixer_to_str(struct sti_mixer *mixer)
  57 {
  58         switch (mixer->id) {
  59         case STI_MIXER_MAIN:
  60                 return "MAIN_MIXER";
  61         case STI_MIXER_AUX:
  62                 return "AUX_MIXER";
  63         default:
  64                 return "<UNKNOWN MIXER>";
  65         }
  66 }
  67
  68 static inline u32 sti_mixer_reg_read(struct sti_mixer *mixer, u32 reg_id)
  69 {
  70         return readl(mixer->regs + reg_id);
  71 }
  72
  73 static inline void sti_mixer_reg_write(struct sti_mixer *mixer,
  74                                        u32 reg_id, u32 val)
  75 {
  76         writel(val, mixer->regs + reg_id);
  77 }
  78
  79 #define DBGFS_DUMP(reg) seq_printf(s, "\n  %-25s 0x%08X", #reg, \
  80                                    sti_mixer_reg_read(mixer, reg))
  81
  82 static void mixer_dbg_ctl(struct seq_file *s, int val)
  83 {
  84         unsigned int i;
  85         int count = 0;
  86         char *const disp_layer[] = {"BKG", "VID0", "VID1", "GDP0",
  87                                     "GDP1", "GDP2", "GDP3"};
  88
  89         seq_puts(s, "\tEnabled: ");
  90         for (i = 0; i < 7; i++) {
  91                 if (val & 1) {
  92                         seq_printf(s, "%s ", disp_layer[i]);
  93                         count++;
  94                 }
  95                 val = val >> 1;
  96         }
  97
  98         val = val >> 2;
  99         if (val & 1) {
 100                 seq_puts(s, "CURS ");
 101                 count++;
 102         }
 103         if (!count)
 104                 seq_puts(s, "Nothing");
 105 }
 106
 107 static void mixer_dbg_crb(struct seq_file *s, int val)
 108 {
 109         int i;
 110
 111         seq_puts(s, "\tDepth: ");
 112         for (i = 0; i < GAM_MIXER_NB_DEPTH_LEVEL; i++) {
 113                 switch (val & GAM_DEPTH_MASK_ID) {
 114                 case GAM_DEPTH_VID0_ID:
 115                         seq_puts(s, "VID0");
 116                         break;
 117                 case GAM_DEPTH_VID1_ID:
 118                         seq_puts(s, "VID1");
 119                         break;
 120                 case GAM_DEPTH_GDP0_ID:
 121                         seq_puts(s, "GDP0");
 122                         break;
 123                 case GAM_DEPTH_GDP1_ID:
 124                         seq_puts(s, "GDP1");
 125                         break;
 126                 case GAM_DEPTH_GDP2_ID:
 127                         seq_puts(s, "GDP2");
 128                         break;
 129                 case GAM_DEPTH_GDP3_ID:
 130                         seq_puts(s, "GDP3");
 131                         break;
 132                 default:
 133                         seq_puts(s, "---");
 134                 }
 135
 136                 if (i < GAM_MIXER_NB_DEPTH_LEVEL - 1)
 137                         seq_puts(s, " < ");
 138                 val = val >> 3;
 139         }
 140 }
 141
 142 static void mixer_dbg_mxn(struct seq_file *s, void *addr)
 143 {
 144         int i;
 145
 146         for (i = 1; i < 8; i++)
 147                 seq_printf(s, "-0x%08X", (int)readl(addr + i * 4));
 148 }
 149
 150 static int mixer_dbg_show(struct seq_file *s, void *arg)
 151 {
 152         struct drm_info_node *node = s->private;
 153         struct sti_mixer *mixer = (struct sti_mixer *)node->info_ent->data;
 154         struct drm_device *dev = node->minor->dev;
 155         int ret;
 156
 157         ret = mutex_lock_interruptible(&dev->struct_mutex);
 158         if (ret)
 159                 return ret;
 160
 161         seq_printf(s, "%s: (vaddr = 0x%p)",
 162                    sti_mixer_to_str(mixer), mixer->regs);
 163
 164         DBGFS_DUMP(GAM_MIXER_CTL);
 165         mixer_dbg_ctl(s, sti_mixer_reg_read(mixer, GAM_MIXER_CTL));
 166         DBGFS_DUMP(GAM_MIXER_BKC);
 167         DBGFS_DUMP(GAM_MIXER_BCO);
 168         DBGFS_DUMP(GAM_MIXER_BCS);
 169         DBGFS_DUMP(GAM_MIXER_AVO);
 170         DBGFS_DUMP(GAM_MIXER_AVS);
 171         DBGFS_DUMP(GAM_MIXER_CRB);
 172         mixer_dbg_crb(s, sti_mixer_reg_read(mixer, GAM_MIXER_CRB));
 173         DBGFS_DUMP(GAM_MIXER_ACT);
 174         DBGFS_DUMP(GAM_MIXER_MBP);
 175         DBGFS_DUMP(GAM_MIXER_MX0);
 176         mixer_dbg_mxn(s, mixer->regs + GAM_MIXER_MX0);
 177         seq_puts(s, "\n");
 178
 179         mutex_unlock(&dev->struct_mutex);
 180         return 0;
 181 }
 182
 183 static struct drm_info_list mixer0_debugfs_files[] = {
 184         { "mixer_main", mixer_dbg_show, 0, NULL },
 185 };
 186
 187 static struct drm_info_list mixer1_debugfs_files[] = {
 188         { "mixer_aux", mixer_dbg_show, 0, NULL },
 189 };
 190
 191 static int mixer_debugfs_init(struct sti_mixer *mixer, struct drm_minor *minor)
 192 {
 193         unsigned int i;
 194         struct drm_info_list *mixer_debugfs_files;
 195         int nb_files;
 196
 197         switch (mixer->id) {
 198         case STI_MIXER_MAIN:
 199                 mixer_debugfs_files = mixer0_debugfs_files;
 200                 nb_files = ARRAY_SIZE(mixer0_debugfs_files);
 201                 break;
 202         case STI_MIXER_AUX:
 203                 mixer_debugfs_files = mixer1_debugfs_files;
 204                 nb_files = ARRAY_SIZE(mixer1_debugfs_files);
 205                 break;
 206         default:
 207                 return -EINVAL;
 208         }
 209
 210         for (i = 0; i < nb_files; i++)
 211                 mixer_debugfs_files[i].data = mixer;
 212
 213         return drm_debugfs_create_files(mixer_debugfs_files,
 214                                         nb_files,
 215                                         minor->debugfs_root, minor);
 216 }
 217
 218 void sti_mixer_set_background_status(struct sti_mixer *mixer, bool enable)
 219 {
 220         u32 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
 221
 222         val &= ~GAM_CTL_BACK_MASK;
 223         val |= enable;
 224         sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
 225 }
 226
 227 static void sti_mixer_set_background_color(struct sti_mixer *mixer,
 228                                            unsigned int rgb)
 229 {
 230         sti_mixer_reg_write(mixer, GAM_MIXER_BKC, rgb);
 231 }
 232
 233 static void sti_mixer_set_background_area(struct sti_mixer *mixer,
 234                                           struct drm_display_mode *mode)
 235 {
 236         u32 ydo, xdo, yds, xds;
 237
 238         ydo = sti_vtg_get_line_number(*mode, 0);
 239         yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
 240         xdo = sti_vtg_get_pixel_number(*mode, 0);
 241         xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
 242
 243         sti_mixer_reg_write(mixer, GAM_MIXER_BCO, ydo << 16 | xdo);
 244         sti_mixer_reg_write(mixer, GAM_MIXER_BCS, yds << 16 | xds);
 245 }
 246
 247 int sti_mixer_set_plane_depth(struct sti_mixer *mixer, struct sti_plane *plane)
 248 {
 249         int plane_id, depth = plane->zorder;
 250         unsigned int i;
 251         u32 mask, val;
 252
 253         if ((depth < 1) || (depth > GAM_MIXER_NB_DEPTH_LEVEL))
 254                 return 1;
 255
 256         switch (plane->desc) {
 257         case STI_GDP_0:
 258                 plane_id = GAM_DEPTH_GDP0_ID;
 259                 break;
 260         case STI_GDP_1:
 261                 plane_id = GAM_DEPTH_GDP1_ID;
 262                 break;
 263         case STI_GDP_2:
 264                 plane_id = GAM_DEPTH_GDP2_ID;
 265                 break;
 266         case STI_GDP_3:
 267                 plane_id = GAM_DEPTH_GDP3_ID;
 268                 break;
 269         case STI_HQVDP_0:
 270                 plane_id = GAM_DEPTH_VID0_ID;
 271                 break;
 272         case STI_CURSOR:
 273                 /* no need to set depth for cursor */
 274                 return 0;
 275         default:
 276                 DRM_ERROR("Unknown plane %d\n", plane->desc);
 277                 return 1;
 278         }
 279
 280         /* Search if a previous depth was already assigned to the plane */
 281         val = sti_mixer_reg_read(mixer, GAM_MIXER_CRB);
 282         for (i = 0; i < GAM_MIXER_NB_DEPTH_LEVEL; i++) {
 283                 mask = GAM_DEPTH_MASK_ID << (3 * i);
 284                 if ((val & mask) == plane_id << (3 * i))
 285                         break;
 286         }
 287
 288         mask |= GAM_DEPTH_MASK_ID << (3 * (depth - 1));
 289         plane_id = plane_id << (3 * (depth - 1));
 290
 291         DRM_DEBUG_DRIVER("%s %s depth=%d\n", sti_mixer_to_str(mixer),
 292                          sti_plane_to_str(plane), depth);
 293         dev_dbg(mixer->dev, "GAM_MIXER_CRB val 0x%x mask 0x%x\n",
 294                 plane_id, mask);
 295
 296         val &= ~mask;
 297         val |= plane_id;
 298         sti_mixer_reg_write(mixer, GAM_MIXER_CRB, val);
 299
 300         dev_dbg(mixer->dev, "Read GAM_MIXER_CRB 0x%x\n",
 301                 sti_mixer_reg_read(mixer, GAM_MIXER_CRB));
 302         return 0;
 303 }
 304
 305 int sti_mixer_active_video_area(struct sti_mixer *mixer,
 306                                 struct drm_display_mode *mode)
 307 {
 308         u32 ydo, xdo, yds, xds;
 309
 310         ydo = sti_vtg_get_line_number(*mode, 0);
 311         yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
 312         xdo = sti_vtg_get_pixel_number(*mode, 0);
 313         xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
 314
 315         DRM_DEBUG_DRIVER("%s active video area xdo:%d ydo:%d xds:%d yds:%d\n",
 316                          sti_mixer_to_str(mixer), xdo, ydo, xds, yds);
 317         sti_mixer_reg_write(mixer, GAM_MIXER_AVO, ydo << 16 | xdo);
 318         sti_mixer_reg_write(mixer, GAM_MIXER_AVS, yds << 16 | xds);
 319
 320         sti_mixer_set_background_color(mixer, bkg_color);
 321
 322         sti_mixer_set_background_area(mixer, mode);
 323         sti_mixer_set_background_status(mixer, true);
 324         return 0;
 325 }
 326
 327 static u32 sti_mixer_get_plane_mask(struct sti_plane *plane)
 328 {
 329         switch (plane->desc) {
 330         case STI_BACK:
 331                 return GAM_CTL_BACK_MASK;
 332         case STI_GDP_0:
 333                 return GAM_CTL_GDP0_MASK;
 334         case STI_GDP_1:
 335                 return GAM_CTL_GDP1_MASK;
 336         case STI_GDP_2:
 337                 return GAM_CTL_GDP2_MASK;
 338         case STI_GDP_3:
 339                 return GAM_CTL_GDP3_MASK;
 340         case STI_HQVDP_0:
 341                 return GAM_CTL_VID0_MASK;
 342         case STI_CURSOR:
 343                 return GAM_CTL_CURSOR_MASK;
 344         default:
 345                 return 0;
 346         }
 347 }
 348
 349 int sti_mixer_set_plane_status(struct sti_mixer *mixer,
 350                                struct sti_plane *plane, bool status)
 351 {
 352         u32 mask, val;
 353
 354         DRM_DEBUG_DRIVER("%s %s %s\n", status ? "enable" : "disable",
 355                          sti_mixer_to_str(mixer), sti_plane_to_str(plane));
 356
 357         mask = sti_mixer_get_plane_mask(plane);
 358         if (!mask) {
 359                 DRM_ERROR("Can't find layer mask\n");
 360                 return -EINVAL;
 361         }
 362
 363         val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
 364         val &= ~mask;
 365         val |= status ? mask : 0;
 366         sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
 367
 368         return 0;
 369 }
 370
 371 void sti_mixer_set_matrix(struct sti_mixer *mixer)
 372 {
 373         unsigned int i;
 374
 375         for (i = 0; i < ARRAY_SIZE(mixerColorSpaceMatIdentity); i++)
 376                 sti_mixer_reg_write(mixer, GAM_MIXER_MX0 + (i * 4),
 377                                     mixerColorSpaceMatIdentity[i]);
 378 }
 379
 380 struct sti_mixer *sti_mixer_create(struct device *dev,
 381                                    struct drm_device *drm_dev,
 382                                    int id,
 383                                    void __iomem *baseaddr)
 384 {
 385         struct sti_mixer *mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL);
 386         struct device_node *np = dev->of_node;
 387
 388         dev_dbg(dev, "%s\n", __func__);
 389         if (!mixer) {
 390                 DRM_ERROR("Failed to allocated memory for mixer\n");
 391                 return NULL;
 392         }
 393         mixer->regs = baseaddr;
 394         mixer->dev = dev;
 395         mixer->id = id;
 396
 397         if (of_device_is_compatible(np, "st,stih416-compositor"))
 398                 sti_mixer_set_matrix(mixer);
 399
 400         DRM_DEBUG_DRIVER("%s created. Regs=%p\n",
 401                          sti_mixer_to_str(mixer), mixer->regs);
 402
 403         if (mixer_debugfs_init(mixer, drm_dev->primary))
 404                 DRM_ERROR("MIXER debugfs setup failed\n");
 405
 406         return mixer;
 407 }