2 * Copyright (C) 2016 Free Electrons
3 * Copyright (C) 2016 NextThing Co
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
16 #include "sun4i_tcon.h"
20 struct regmap
*regmap
;
23 static inline struct sun4i_dclk
*hw_to_dclk(struct clk_hw
*hw
)
25 return container_of(hw
, struct sun4i_dclk
, hw
);
28 static void sun4i_dclk_disable(struct clk_hw
*hw
)
30 struct sun4i_dclk
*dclk
= hw_to_dclk(hw
);
32 regmap_update_bits(dclk
->regmap
, SUN4I_TCON0_DCLK_REG
,
33 BIT(SUN4I_TCON0_DCLK_GATE_BIT
), 0);
36 static int sun4i_dclk_enable(struct clk_hw
*hw
)
38 struct sun4i_dclk
*dclk
= hw_to_dclk(hw
);
40 return regmap_update_bits(dclk
->regmap
, SUN4I_TCON0_DCLK_REG
,
41 BIT(SUN4I_TCON0_DCLK_GATE_BIT
),
42 BIT(SUN4I_TCON0_DCLK_GATE_BIT
));
45 static int sun4i_dclk_is_enabled(struct clk_hw
*hw
)
47 struct sun4i_dclk
*dclk
= hw_to_dclk(hw
);
50 regmap_read(dclk
->regmap
, SUN4I_TCON0_DCLK_REG
, &val
);
52 return val
& BIT(SUN4I_TCON0_DCLK_GATE_BIT
);
55 static unsigned long sun4i_dclk_recalc_rate(struct clk_hw
*hw
,
56 unsigned long parent_rate
)
58 struct sun4i_dclk
*dclk
= hw_to_dclk(hw
);
61 regmap_read(dclk
->regmap
, SUN4I_TCON0_DCLK_REG
, &val
);
63 val
>>= SUN4I_TCON0_DCLK_DIV_SHIFT
;
64 val
&= SUN4I_TCON0_DCLK_DIV_WIDTH
;
69 return parent_rate
/ val
;
72 static long sun4i_dclk_round_rate(struct clk_hw
*hw
, unsigned long rate
,
73 unsigned long *parent_rate
)
75 return *parent_rate
/ DIV_ROUND_CLOSEST(*parent_rate
, rate
);
78 static int sun4i_dclk_set_rate(struct clk_hw
*hw
, unsigned long rate
,
79 unsigned long parent_rate
)
81 struct sun4i_dclk
*dclk
= hw_to_dclk(hw
);
82 int div
= DIV_ROUND_CLOSEST(parent_rate
, rate
);
84 return regmap_update_bits(dclk
->regmap
, SUN4I_TCON0_DCLK_REG
,
88 static int sun4i_dclk_get_phase(struct clk_hw
*hw
)
90 struct sun4i_dclk
*dclk
= hw_to_dclk(hw
);
93 regmap_read(dclk
->regmap
, SUN4I_TCON0_IO_POL_REG
, &val
);
101 static int sun4i_dclk_set_phase(struct clk_hw
*hw
, int degrees
)
103 struct sun4i_dclk
*dclk
= hw_to_dclk(hw
);
105 regmap_update_bits(dclk
->regmap
, SUN4I_TCON0_IO_POL_REG
,
112 static const struct clk_ops sun4i_dclk_ops
= {
113 .disable
= sun4i_dclk_disable
,
114 .enable
= sun4i_dclk_enable
,
115 .is_enabled
= sun4i_dclk_is_enabled
,
117 .recalc_rate
= sun4i_dclk_recalc_rate
,
118 .round_rate
= sun4i_dclk_round_rate
,
119 .set_rate
= sun4i_dclk_set_rate
,
121 .get_phase
= sun4i_dclk_get_phase
,
122 .set_phase
= sun4i_dclk_set_phase
,
125 int sun4i_dclk_create(struct device
*dev
, struct sun4i_tcon
*tcon
)
127 const char *clk_name
, *parent_name
;
128 struct clk_init_data init
;
129 struct sun4i_dclk
*dclk
;
131 parent_name
= __clk_get_name(tcon
->sclk0
);
132 of_property_read_string_index(dev
->of_node
, "clock-output-names", 0,
135 dclk
= devm_kzalloc(dev
, sizeof(*dclk
), GFP_KERNEL
);
139 init
.name
= clk_name
;
140 init
.ops
= &sun4i_dclk_ops
;
141 init
.parent_names
= &parent_name
;
142 init
.num_parents
= 1;
144 dclk
->regmap
= tcon
->regs
;
145 dclk
->hw
.init
= &init
;
147 tcon
->dclk
= clk_register(dev
, &dclk
->hw
);
148 if (IS_ERR(tcon
->dclk
))
149 return PTR_ERR(tcon
->dclk
);
153 EXPORT_SYMBOL(sun4i_dclk_create
);
155 int sun4i_dclk_free(struct sun4i_tcon
*tcon
)
157 clk_unregister(tcon
->dclk
);
160 EXPORT_SYMBOL(sun4i_dclk_free
);