2 * Copyright (C) 2015 Free Electrons
3 * Copyright (C) 2015 NextThing Co
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
14 #include <drm/drm_atomic_helper.h>
15 #include <drm/drm_crtc.h>
16 #include <drm/drm_crtc_helper.h>
17 #include <drm/drm_modes.h>
18 #include <drm/drm_panel.h>
20 #include <linux/component.h>
21 #include <linux/ioport.h>
22 #include <linux/of_address.h>
23 #include <linux/of_graph.h>
24 #include <linux/of_irq.h>
25 #include <linux/regmap.h>
26 #include <linux/reset.h>
28 #include "sun4i_crtc.h"
29 #include "sun4i_dotclock.h"
30 #include "sun4i_drv.h"
31 #include "sun4i_rgb.h"
32 #include "sun4i_tcon.h"
34 void sun4i_tcon_disable(struct sun4i_tcon
*tcon
)
36 DRM_DEBUG_DRIVER("Disabling TCON\n");
38 /* Disable the TCON */
39 regmap_update_bits(tcon
->regs
, SUN4I_TCON_GCTL_REG
,
40 SUN4I_TCON_GCTL_TCON_ENABLE
, 0);
42 EXPORT_SYMBOL(sun4i_tcon_disable
);
44 void sun4i_tcon_enable(struct sun4i_tcon
*tcon
)
46 DRM_DEBUG_DRIVER("Enabling TCON\n");
49 regmap_update_bits(tcon
->regs
, SUN4I_TCON_GCTL_REG
,
50 SUN4I_TCON_GCTL_TCON_ENABLE
,
51 SUN4I_TCON_GCTL_TCON_ENABLE
);
53 EXPORT_SYMBOL(sun4i_tcon_enable
);
55 void sun4i_tcon_channel_disable(struct sun4i_tcon
*tcon
, int channel
)
57 /* Disable the TCON's channel */
59 regmap_update_bits(tcon
->regs
, SUN4I_TCON0_CTL_REG
,
60 SUN4I_TCON0_CTL_TCON_ENABLE
, 0);
61 clk_disable_unprepare(tcon
->dclk
);
62 } else if (channel
== 1) {
63 regmap_update_bits(tcon
->regs
, SUN4I_TCON1_CTL_REG
,
64 SUN4I_TCON1_CTL_TCON_ENABLE
, 0);
65 clk_disable_unprepare(tcon
->sclk1
);
68 EXPORT_SYMBOL(sun4i_tcon_channel_disable
);
70 void sun4i_tcon_channel_enable(struct sun4i_tcon
*tcon
, int channel
)
72 /* Enable the TCON's channel */
74 regmap_update_bits(tcon
->regs
, SUN4I_TCON0_CTL_REG
,
75 SUN4I_TCON0_CTL_TCON_ENABLE
,
76 SUN4I_TCON0_CTL_TCON_ENABLE
);
77 clk_prepare_enable(tcon
->dclk
);
78 } else if (channel
== 1) {
79 regmap_update_bits(tcon
->regs
, SUN4I_TCON1_CTL_REG
,
80 SUN4I_TCON1_CTL_TCON_ENABLE
,
81 SUN4I_TCON1_CTL_TCON_ENABLE
);
82 clk_prepare_enable(tcon
->sclk1
);
85 EXPORT_SYMBOL(sun4i_tcon_channel_enable
);
87 void sun4i_tcon_enable_vblank(struct sun4i_tcon
*tcon
, bool enable
)
91 DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable
? "En" : "Dis");
93 mask
= SUN4I_TCON_GINT0_VBLANK_ENABLE(0) |
94 SUN4I_TCON_GINT0_VBLANK_ENABLE(1);
99 regmap_update_bits(tcon
->regs
, SUN4I_TCON_GINT0_REG
, mask
, val
);
101 EXPORT_SYMBOL(sun4i_tcon_enable_vblank
);
103 static int sun4i_tcon_get_clk_delay(struct drm_display_mode
*mode
,
106 int delay
= mode
->vtotal
- mode
->vdisplay
;
108 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
114 delay
= min(delay
, 30);
116 DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel
, delay
);
121 void sun4i_tcon0_mode_set(struct sun4i_tcon
*tcon
,
122 struct drm_display_mode
*mode
)
124 unsigned int bp
, hsync
, vsync
;
128 /* Adjust clock delay */
129 clk_delay
= sun4i_tcon_get_clk_delay(mode
, 0);
130 regmap_update_bits(tcon
->regs
, SUN4I_TCON0_CTL_REG
,
131 SUN4I_TCON0_CTL_CLK_DELAY_MASK
,
132 SUN4I_TCON0_CTL_CLK_DELAY(clk_delay
));
134 /* Set the resolution */
135 regmap_write(tcon
->regs
, SUN4I_TCON0_BASIC0_REG
,
136 SUN4I_TCON0_BASIC0_X(mode
->crtc_hdisplay
) |
137 SUN4I_TCON0_BASIC0_Y(mode
->crtc_vdisplay
));
140 * This is called a backporch in the register documentation,
141 * but it really is the front porch + hsync
143 bp
= mode
->crtc_htotal
- mode
->crtc_hsync_start
;
144 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
145 mode
->crtc_htotal
, bp
);
147 /* Set horizontal display timings */
148 regmap_write(tcon
->regs
, SUN4I_TCON0_BASIC1_REG
,
149 SUN4I_TCON0_BASIC1_H_TOTAL(mode
->crtc_htotal
) |
150 SUN4I_TCON0_BASIC1_H_BACKPORCH(bp
));
153 * This is called a backporch in the register documentation,
154 * but it really is the front porch + hsync
156 bp
= mode
->crtc_vtotal
- mode
->crtc_vsync_start
;
157 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
158 mode
->crtc_vtotal
, bp
);
160 /* Set vertical display timings */
161 regmap_write(tcon
->regs
, SUN4I_TCON0_BASIC2_REG
,
162 SUN4I_TCON0_BASIC2_V_TOTAL(mode
->crtc_vtotal
) |
163 SUN4I_TCON0_BASIC2_V_BACKPORCH(bp
));
165 /* Set Hsync and Vsync length */
166 hsync
= mode
->crtc_hsync_end
- mode
->crtc_hsync_start
;
167 vsync
= mode
->crtc_vsync_end
- mode
->crtc_vsync_start
;
168 DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync
, vsync
);
169 regmap_write(tcon
->regs
, SUN4I_TCON0_BASIC3_REG
,
170 SUN4I_TCON0_BASIC3_V_SYNC(vsync
) |
171 SUN4I_TCON0_BASIC3_H_SYNC(hsync
));
173 /* Setup the polarity of the various signals */
174 if (!(mode
->flags
& DRM_MODE_FLAG_PHSYNC
))
175 val
|= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE
;
177 if (!(mode
->flags
& DRM_MODE_FLAG_PVSYNC
))
178 val
|= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE
;
180 regmap_update_bits(tcon
->regs
, SUN4I_TCON0_IO_POL_REG
,
181 SUN4I_TCON0_IO_POL_HSYNC_POSITIVE
| SUN4I_TCON0_IO_POL_VSYNC_POSITIVE
,
184 /* Map output pins to channel 0 */
185 regmap_update_bits(tcon
->regs
, SUN4I_TCON_GCTL_REG
,
186 SUN4I_TCON_GCTL_IOMAP_MASK
,
187 SUN4I_TCON_GCTL_IOMAP_TCON0
);
189 /* Enable the output on the pins */
190 regmap_write(tcon
->regs
, SUN4I_TCON0_IO_TRI_REG
, 0);
192 EXPORT_SYMBOL(sun4i_tcon0_mode_set
);
194 void sun4i_tcon1_mode_set(struct sun4i_tcon
*tcon
,
195 struct drm_display_mode
*mode
)
197 unsigned int bp
, hsync
, vsync
;
201 /* Adjust clock delay */
202 clk_delay
= sun4i_tcon_get_clk_delay(mode
, 1);
203 regmap_update_bits(tcon
->regs
, SUN4I_TCON1_CTL_REG
,
204 SUN4I_TCON1_CTL_CLK_DELAY_MASK
,
205 SUN4I_TCON1_CTL_CLK_DELAY(clk_delay
));
207 /* Set interlaced mode */
208 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
209 val
= SUN4I_TCON1_CTL_INTERLACE_ENABLE
;
212 regmap_update_bits(tcon
->regs
, SUN4I_TCON1_CTL_REG
,
213 SUN4I_TCON1_CTL_INTERLACE_ENABLE
,
216 /* Set the input resolution */
217 regmap_write(tcon
->regs
, SUN4I_TCON1_BASIC0_REG
,
218 SUN4I_TCON1_BASIC0_X(mode
->crtc_hdisplay
) |
219 SUN4I_TCON1_BASIC0_Y(mode
->crtc_vdisplay
));
221 /* Set the upscaling resolution */
222 regmap_write(tcon
->regs
, SUN4I_TCON1_BASIC1_REG
,
223 SUN4I_TCON1_BASIC1_X(mode
->crtc_hdisplay
) |
224 SUN4I_TCON1_BASIC1_Y(mode
->crtc_vdisplay
));
226 /* Set the output resolution */
227 regmap_write(tcon
->regs
, SUN4I_TCON1_BASIC2_REG
,
228 SUN4I_TCON1_BASIC2_X(mode
->crtc_hdisplay
) |
229 SUN4I_TCON1_BASIC2_Y(mode
->crtc_vdisplay
));
231 /* Set horizontal display timings */
232 bp
= mode
->crtc_htotal
- mode
->crtc_hsync_end
;
233 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
235 regmap_write(tcon
->regs
, SUN4I_TCON1_BASIC3_REG
,
236 SUN4I_TCON1_BASIC3_H_TOTAL(mode
->crtc_htotal
) |
237 SUN4I_TCON1_BASIC3_H_BACKPORCH(bp
));
239 /* Set vertical display timings */
240 bp
= mode
->crtc_vtotal
- mode
->crtc_vsync_end
;
241 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
243 regmap_write(tcon
->regs
, SUN4I_TCON1_BASIC4_REG
,
244 SUN4I_TCON1_BASIC4_V_TOTAL(mode
->vtotal
) |
245 SUN4I_TCON1_BASIC4_V_BACKPORCH(bp
));
247 /* Set Hsync and Vsync length */
248 hsync
= mode
->crtc_hsync_end
- mode
->crtc_hsync_start
;
249 vsync
= mode
->crtc_vsync_end
- mode
->crtc_vsync_start
;
250 DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync
, vsync
);
251 regmap_write(tcon
->regs
, SUN4I_TCON1_BASIC5_REG
,
252 SUN4I_TCON1_BASIC5_V_SYNC(vsync
) |
253 SUN4I_TCON1_BASIC5_H_SYNC(hsync
));
255 /* Map output pins to channel 1 */
256 regmap_update_bits(tcon
->regs
, SUN4I_TCON_GCTL_REG
,
257 SUN4I_TCON_GCTL_IOMAP_MASK
,
258 SUN4I_TCON_GCTL_IOMAP_TCON1
);
261 * FIXME: Undocumented bits
264 regmap_write(tcon
->regs
, SUN4I_TCON_MUX_CTRL_REG
, 1);
266 EXPORT_SYMBOL(sun4i_tcon1_mode_set
);
268 static void sun4i_tcon_finish_page_flip(struct drm_device
*dev
,
269 struct sun4i_crtc
*scrtc
)
273 spin_lock_irqsave(&dev
->event_lock
, flags
);
275 drm_crtc_send_vblank_event(&scrtc
->crtc
, scrtc
->event
);
276 drm_crtc_vblank_put(&scrtc
->crtc
);
279 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
282 static irqreturn_t
sun4i_tcon_handler(int irq
, void *private)
284 struct sun4i_tcon
*tcon
= private;
285 struct drm_device
*drm
= tcon
->drm
;
286 struct sun4i_drv
*drv
= drm
->dev_private
;
287 struct sun4i_crtc
*scrtc
= drv
->crtc
;
290 regmap_read(tcon
->regs
, SUN4I_TCON_GINT0_REG
, &status
);
292 if (!(status
& (SUN4I_TCON_GINT0_VBLANK_INT(0) |
293 SUN4I_TCON_GINT0_VBLANK_INT(1))))
296 drm_crtc_handle_vblank(&scrtc
->crtc
);
297 sun4i_tcon_finish_page_flip(drm
, scrtc
);
299 /* Acknowledge the interrupt */
300 regmap_update_bits(tcon
->regs
, SUN4I_TCON_GINT0_REG
,
301 SUN4I_TCON_GINT0_VBLANK_INT(0) |
302 SUN4I_TCON_GINT0_VBLANK_INT(1),
308 static int sun4i_tcon_init_clocks(struct device
*dev
,
309 struct sun4i_tcon
*tcon
)
311 tcon
->clk
= devm_clk_get(dev
, "ahb");
312 if (IS_ERR(tcon
->clk
)) {
313 dev_err(dev
, "Couldn't get the TCON bus clock\n");
314 return PTR_ERR(tcon
->clk
);
316 clk_prepare_enable(tcon
->clk
);
318 tcon
->sclk0
= devm_clk_get(dev
, "tcon-ch0");
319 if (IS_ERR(tcon
->sclk0
)) {
320 dev_err(dev
, "Couldn't get the TCON channel 0 clock\n");
321 return PTR_ERR(tcon
->sclk0
);
324 tcon
->sclk1
= devm_clk_get(dev
, "tcon-ch1");
325 if (IS_ERR(tcon
->sclk1
)) {
326 dev_err(dev
, "Couldn't get the TCON channel 1 clock\n");
327 return PTR_ERR(tcon
->sclk1
);
330 return sun4i_dclk_create(dev
, tcon
);
333 static void sun4i_tcon_free_clocks(struct sun4i_tcon
*tcon
)
335 sun4i_dclk_free(tcon
);
336 clk_disable_unprepare(tcon
->clk
);
339 static int sun4i_tcon_init_irq(struct device
*dev
,
340 struct sun4i_tcon
*tcon
)
342 struct platform_device
*pdev
= to_platform_device(dev
);
345 irq
= platform_get_irq(pdev
, 0);
347 dev_err(dev
, "Couldn't retrieve the TCON interrupt\n");
351 ret
= devm_request_irq(dev
, irq
, sun4i_tcon_handler
, 0,
352 dev_name(dev
), tcon
);
354 dev_err(dev
, "Couldn't request the IRQ\n");
361 static struct regmap_config sun4i_tcon_regmap_config
= {
365 .max_register
= 0x800,
368 static int sun4i_tcon_init_regmap(struct device
*dev
,
369 struct sun4i_tcon
*tcon
)
371 struct platform_device
*pdev
= to_platform_device(dev
);
372 struct resource
*res
;
375 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
376 regs
= devm_ioremap_resource(dev
, res
);
378 dev_err(dev
, "Couldn't map the TCON registers\n");
379 return PTR_ERR(regs
);
382 tcon
->regs
= devm_regmap_init_mmio(dev
, regs
,
383 &sun4i_tcon_regmap_config
);
384 if (IS_ERR(tcon
->regs
)) {
385 dev_err(dev
, "Couldn't create the TCON regmap\n");
386 return PTR_ERR(tcon
->regs
);
389 /* Make sure the TCON is disabled and all IRQs are off */
390 regmap_write(tcon
->regs
, SUN4I_TCON_GCTL_REG
, 0);
391 regmap_write(tcon
->regs
, SUN4I_TCON_GINT0_REG
, 0);
392 regmap_write(tcon
->regs
, SUN4I_TCON_GINT1_REG
, 0);
394 /* Disable IO lines and set them to tristate */
395 regmap_write(tcon
->regs
, SUN4I_TCON0_IO_TRI_REG
, ~0);
396 regmap_write(tcon
->regs
, SUN4I_TCON1_IO_TRI_REG
, ~0);
401 static struct drm_panel
*sun4i_tcon_find_panel(struct device_node
*node
)
403 struct device_node
*port
, *remote
, *child
;
404 struct device_node
*end_node
= NULL
;
406 /* Inputs are listed first, then outputs */
407 port
= of_graph_get_port_by_id(node
, 1);
410 * Our first output is the RGB interface where the panel will
413 for_each_child_of_node(port
, child
) {
416 of_property_read_u32(child
, "reg", ®
);
422 DRM_DEBUG_DRIVER("Missing panel endpoint\n");
423 return ERR_PTR(-ENODEV
);
426 remote
= of_graph_get_remote_port_parent(end_node
);
428 DRM_DEBUG_DRIVER("Unable to parse remote node\n");
429 return ERR_PTR(-EINVAL
);
432 return of_drm_find_panel(remote
) ?: ERR_PTR(-EPROBE_DEFER
);
435 static int sun4i_tcon_bind(struct device
*dev
, struct device
*master
,
438 struct drm_device
*drm
= data
;
439 struct sun4i_drv
*drv
= drm
->dev_private
;
440 struct sun4i_tcon
*tcon
;
443 tcon
= devm_kzalloc(dev
, sizeof(*tcon
), GFP_KERNEL
);
446 dev_set_drvdata(dev
, tcon
);
450 if (of_device_is_compatible(dev
->of_node
, "allwinner,sun5i-a13-tcon"))
451 tcon
->has_mux
= true;
453 tcon
->lcd_rst
= devm_reset_control_get(dev
, "lcd");
454 if (IS_ERR(tcon
->lcd_rst
)) {
455 dev_err(dev
, "Couldn't get our reset line\n");
456 return PTR_ERR(tcon
->lcd_rst
);
459 /* Make sure our TCON is reset */
460 if (!reset_control_status(tcon
->lcd_rst
))
461 reset_control_assert(tcon
->lcd_rst
);
463 ret
= reset_control_deassert(tcon
->lcd_rst
);
465 dev_err(dev
, "Couldn't deassert our reset line\n");
469 ret
= sun4i_tcon_init_regmap(dev
, tcon
);
471 dev_err(dev
, "Couldn't init our TCON regmap\n");
472 goto err_assert_reset
;
475 ret
= sun4i_tcon_init_clocks(dev
, tcon
);
477 dev_err(dev
, "Couldn't init our TCON clocks\n");
478 goto err_assert_reset
;
481 ret
= sun4i_tcon_init_irq(dev
, tcon
);
483 dev_err(dev
, "Couldn't init our TCON interrupts\n");
484 goto err_free_clocks
;
487 tcon
->panel
= sun4i_tcon_find_panel(dev
->of_node
);
488 if (IS_ERR(tcon
->panel
)) {
489 dev_info(dev
, "No panel found... RGB output disabled\n");
493 ret
= sun4i_rgb_init(drm
);
495 goto err_free_clocks
;
500 sun4i_tcon_free_clocks(tcon
);
502 reset_control_assert(tcon
->lcd_rst
);
506 static void sun4i_tcon_unbind(struct device
*dev
, struct device
*master
,
509 struct sun4i_tcon
*tcon
= dev_get_drvdata(dev
);
511 sun4i_tcon_free_clocks(tcon
);
514 static struct component_ops sun4i_tcon_ops
= {
515 .bind
= sun4i_tcon_bind
,
516 .unbind
= sun4i_tcon_unbind
,
519 static int sun4i_tcon_probe(struct platform_device
*pdev
)
521 struct device_node
*node
= pdev
->dev
.of_node
;
522 struct drm_panel
*panel
;
525 * The panel is not ready.
528 panel
= sun4i_tcon_find_panel(node
);
531 * If we don't have a panel endpoint, just go on
533 if (PTR_ERR(panel
) == -EPROBE_DEFER
) {
534 DRM_DEBUG_DRIVER("Still waiting for our panel. Deferring...\n");
535 return -EPROBE_DEFER
;
538 return component_add(&pdev
->dev
, &sun4i_tcon_ops
);
541 static int sun4i_tcon_remove(struct platform_device
*pdev
)
543 component_del(&pdev
->dev
, &sun4i_tcon_ops
);
548 static const struct of_device_id sun4i_tcon_of_table
[] = {
549 { .compatible
= "allwinner,sun5i-a13-tcon" },
552 MODULE_DEVICE_TABLE(of
, sun4i_tcon_of_table
);
554 static struct platform_driver sun4i_tcon_platform_driver
= {
555 .probe
= sun4i_tcon_probe
,
556 .remove
= sun4i_tcon_remove
,
558 .name
= "sun4i-tcon",
559 .of_match_table
= sun4i_tcon_of_table
,
562 module_platform_driver(sun4i_tcon_platform_driver
);
564 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
565 MODULE_DESCRIPTION("Allwinner A10 Timing Controller Driver");
566 MODULE_LICENSE("GPL");