2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/iommu.h>
13 #include <linux/reset.h>
15 #include <soc/tegra/pmc.h>
21 #include <drm/drm_plane_helper.h>
23 struct tegra_dc_soc_info
{
24 bool supports_border_color
;
25 bool supports_interlacing
;
27 bool supports_block_linear
;
28 unsigned int pitch_align
;
33 struct drm_plane base
;
37 static inline struct tegra_plane
*to_tegra_plane(struct drm_plane
*plane
)
39 return container_of(plane
, struct tegra_plane
, base
);
42 static void tegra_dc_window_commit(struct tegra_dc
*dc
, unsigned int index
)
44 u32 value
= WIN_A_ACT_REQ
<< index
;
46 tegra_dc_writel(dc
, value
<< 8, DC_CMD_STATE_CONTROL
);
47 tegra_dc_writel(dc
, value
, DC_CMD_STATE_CONTROL
);
50 static void tegra_dc_cursor_commit(struct tegra_dc
*dc
)
52 tegra_dc_writel(dc
, CURSOR_ACT_REQ
<< 8, DC_CMD_STATE_CONTROL
);
53 tegra_dc_writel(dc
, CURSOR_ACT_REQ
, DC_CMD_STATE_CONTROL
);
57 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
58 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
59 * Latching happens mmediately if the display controller is in STOP mode or
60 * on the next frame boundary otherwise.
62 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
63 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
64 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
65 * into the ACTIVE copy, either immediately if the display controller is in
66 * STOP mode, or at the next frame boundary otherwise.
68 static void tegra_dc_commit(struct tegra_dc
*dc
)
70 tegra_dc_writel(dc
, GENERAL_ACT_REQ
<< 8, DC_CMD_STATE_CONTROL
);
71 tegra_dc_writel(dc
, GENERAL_ACT_REQ
, DC_CMD_STATE_CONTROL
);
74 static unsigned int tegra_dc_format(uint32_t format
, uint32_t *swap
)
76 /* assume no swapping of fetched data */
78 *swap
= BYTE_SWAP_NOSWAP
;
81 case DRM_FORMAT_XBGR8888
:
82 return WIN_COLOR_DEPTH_R8G8B8A8
;
84 case DRM_FORMAT_XRGB8888
:
85 return WIN_COLOR_DEPTH_B8G8R8A8
;
87 case DRM_FORMAT_RGB565
:
88 return WIN_COLOR_DEPTH_B5G6R5
;
91 return WIN_COLOR_DEPTH_YCbCr422
;
95 *swap
= BYTE_SWAP_SWAP2
;
97 return WIN_COLOR_DEPTH_YCbCr422
;
99 case DRM_FORMAT_YUV420
:
100 return WIN_COLOR_DEPTH_YCbCr420P
;
102 case DRM_FORMAT_YUV422
:
103 return WIN_COLOR_DEPTH_YCbCr422P
;
109 WARN(1, "unsupported pixel format %u, using default\n", format
);
110 return WIN_COLOR_DEPTH_B8G8R8A8
;
113 static bool tegra_dc_format_is_yuv(unsigned int format
, bool *planar
)
116 case WIN_COLOR_DEPTH_YCbCr422
:
117 case WIN_COLOR_DEPTH_YUV422
:
123 case WIN_COLOR_DEPTH_YCbCr420P
:
124 case WIN_COLOR_DEPTH_YUV420P
:
125 case WIN_COLOR_DEPTH_YCbCr422P
:
126 case WIN_COLOR_DEPTH_YUV422P
:
127 case WIN_COLOR_DEPTH_YCbCr422R
:
128 case WIN_COLOR_DEPTH_YUV422R
:
129 case WIN_COLOR_DEPTH_YCbCr422RA
:
130 case WIN_COLOR_DEPTH_YUV422RA
:
140 static inline u32
compute_dda_inc(unsigned int in
, unsigned int out
, bool v
,
143 fixed20_12 outf
= dfixed_init(out
);
144 fixed20_12 inf
= dfixed_init(in
);
165 outf
.full
= max_t(u32
, outf
.full
- dfixed_const(1), dfixed_const(1));
166 inf
.full
-= dfixed_const(1);
168 dda_inc
= dfixed_div(inf
, outf
);
169 dda_inc
= min_t(u32
, dda_inc
, dfixed_const(max
));
174 static inline u32
compute_initial_dda(unsigned int in
)
176 fixed20_12 inf
= dfixed_init(in
);
177 return dfixed_frac(inf
);
180 static int tegra_dc_setup_window(struct tegra_dc
*dc
, unsigned int index
,
181 const struct tegra_dc_window
*window
)
183 unsigned h_offset
, v_offset
, h_size
, v_size
, h_dda
, v_dda
, bpp
;
184 unsigned long value
, flags
;
188 * For YUV planar modes, the number of bytes per pixel takes into
189 * account only the luma component and therefore is 1.
191 yuv
= tegra_dc_format_is_yuv(window
->format
, &planar
);
193 bpp
= window
->bits_per_pixel
/ 8;
195 bpp
= planar
? 1 : 2;
197 spin_lock_irqsave(&dc
->lock
, flags
);
199 value
= WINDOW_A_SELECT
<< index
;
200 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_WINDOW_HEADER
);
202 tegra_dc_writel(dc
, window
->format
, DC_WIN_COLOR_DEPTH
);
203 tegra_dc_writel(dc
, window
->swap
, DC_WIN_BYTE_SWAP
);
205 value
= V_POSITION(window
->dst
.y
) | H_POSITION(window
->dst
.x
);
206 tegra_dc_writel(dc
, value
, DC_WIN_POSITION
);
208 value
= V_SIZE(window
->dst
.h
) | H_SIZE(window
->dst
.w
);
209 tegra_dc_writel(dc
, value
, DC_WIN_SIZE
);
211 h_offset
= window
->src
.x
* bpp
;
212 v_offset
= window
->src
.y
;
213 h_size
= window
->src
.w
* bpp
;
214 v_size
= window
->src
.h
;
216 value
= V_PRESCALED_SIZE(v_size
) | H_PRESCALED_SIZE(h_size
);
217 tegra_dc_writel(dc
, value
, DC_WIN_PRESCALED_SIZE
);
220 * For DDA computations the number of bytes per pixel for YUV planar
221 * modes needs to take into account all Y, U and V components.
226 h_dda
= compute_dda_inc(window
->src
.w
, window
->dst
.w
, false, bpp
);
227 v_dda
= compute_dda_inc(window
->src
.h
, window
->dst
.h
, true, bpp
);
229 value
= V_DDA_INC(v_dda
) | H_DDA_INC(h_dda
);
230 tegra_dc_writel(dc
, value
, DC_WIN_DDA_INC
);
232 h_dda
= compute_initial_dda(window
->src
.x
);
233 v_dda
= compute_initial_dda(window
->src
.y
);
235 tegra_dc_writel(dc
, h_dda
, DC_WIN_H_INITIAL_DDA
);
236 tegra_dc_writel(dc
, v_dda
, DC_WIN_V_INITIAL_DDA
);
238 tegra_dc_writel(dc
, 0, DC_WIN_UV_BUF_STRIDE
);
239 tegra_dc_writel(dc
, 0, DC_WIN_BUF_STRIDE
);
241 tegra_dc_writel(dc
, window
->base
[0], DC_WINBUF_START_ADDR
);
244 tegra_dc_writel(dc
, window
->base
[1], DC_WINBUF_START_ADDR_U
);
245 tegra_dc_writel(dc
, window
->base
[2], DC_WINBUF_START_ADDR_V
);
246 value
= window
->stride
[1] << 16 | window
->stride
[0];
247 tegra_dc_writel(dc
, value
, DC_WIN_LINE_STRIDE
);
249 tegra_dc_writel(dc
, window
->stride
[0], DC_WIN_LINE_STRIDE
);
252 if (window
->bottom_up
)
253 v_offset
+= window
->src
.h
- 1;
255 tegra_dc_writel(dc
, h_offset
, DC_WINBUF_ADDR_H_OFFSET
);
256 tegra_dc_writel(dc
, v_offset
, DC_WINBUF_ADDR_V_OFFSET
);
258 if (dc
->soc
->supports_block_linear
) {
259 unsigned long height
= window
->tiling
.value
;
261 switch (window
->tiling
.mode
) {
262 case TEGRA_BO_TILING_MODE_PITCH
:
263 value
= DC_WINBUF_SURFACE_KIND_PITCH
;
266 case TEGRA_BO_TILING_MODE_TILED
:
267 value
= DC_WINBUF_SURFACE_KIND_TILED
;
270 case TEGRA_BO_TILING_MODE_BLOCK
:
271 value
= DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height
) |
272 DC_WINBUF_SURFACE_KIND_BLOCK
;
276 tegra_dc_writel(dc
, value
, DC_WINBUF_SURFACE_KIND
);
278 switch (window
->tiling
.mode
) {
279 case TEGRA_BO_TILING_MODE_PITCH
:
280 value
= DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV
|
281 DC_WIN_BUFFER_ADDR_MODE_LINEAR
;
284 case TEGRA_BO_TILING_MODE_TILED
:
285 value
= DC_WIN_BUFFER_ADDR_MODE_TILE_UV
|
286 DC_WIN_BUFFER_ADDR_MODE_TILE
;
289 case TEGRA_BO_TILING_MODE_BLOCK
:
290 DRM_ERROR("hardware doesn't support block linear mode\n");
291 spin_unlock_irqrestore(&dc
->lock
, flags
);
295 tegra_dc_writel(dc
, value
, DC_WIN_BUFFER_ADDR_MODE
);
301 /* setup default colorspace conversion coefficients */
302 tegra_dc_writel(dc
, 0x00f0, DC_WIN_CSC_YOF
);
303 tegra_dc_writel(dc
, 0x012a, DC_WIN_CSC_KYRGB
);
304 tegra_dc_writel(dc
, 0x0000, DC_WIN_CSC_KUR
);
305 tegra_dc_writel(dc
, 0x0198, DC_WIN_CSC_KVR
);
306 tegra_dc_writel(dc
, 0x039b, DC_WIN_CSC_KUG
);
307 tegra_dc_writel(dc
, 0x032f, DC_WIN_CSC_KVG
);
308 tegra_dc_writel(dc
, 0x0204, DC_WIN_CSC_KUB
);
309 tegra_dc_writel(dc
, 0x0000, DC_WIN_CSC_KVB
);
312 } else if (window
->bits_per_pixel
< 24) {
313 value
|= COLOR_EXPAND
;
316 if (window
->bottom_up
)
317 value
|= V_DIRECTION
;
319 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
322 * Disable blending and assume Window A is the bottom-most window,
323 * Window C is the top-most window and Window B is in the middle.
325 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_NOKEY
);
326 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_1WIN
);
330 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_2WIN_X
);
331 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_2WIN_Y
);
332 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_3WIN_XY
);
336 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_2WIN_X
);
337 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_2WIN_Y
);
338 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_3WIN_XY
);
342 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_2WIN_X
);
343 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_2WIN_Y
);
344 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_3WIN_XY
);
348 tegra_dc_window_commit(dc
, index
);
350 spin_unlock_irqrestore(&dc
->lock
, flags
);
355 static int tegra_window_plane_disable(struct drm_plane
*plane
)
357 struct tegra_dc
*dc
= to_tegra_dc(plane
->crtc
);
358 struct tegra_plane
*p
= to_tegra_plane(plane
);
365 spin_lock_irqsave(&dc
->lock
, flags
);
367 value
= WINDOW_A_SELECT
<< p
->index
;
368 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_WINDOW_HEADER
);
370 value
= tegra_dc_readl(dc
, DC_WIN_WIN_OPTIONS
);
371 value
&= ~WIN_ENABLE
;
372 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
374 tegra_dc_window_commit(dc
, p
->index
);
376 spin_unlock_irqrestore(&dc
->lock
, flags
);
381 static void tegra_plane_destroy(struct drm_plane
*plane
)
383 struct tegra_plane
*p
= to_tegra_plane(plane
);
385 drm_plane_cleanup(plane
);
389 static const u32 tegra_primary_plane_formats
[] = {
395 static int tegra_primary_plane_update(struct drm_plane
*plane
,
396 struct drm_crtc
*crtc
,
397 struct drm_framebuffer
*fb
, int crtc_x
,
398 int crtc_y
, unsigned int crtc_w
,
399 unsigned int crtc_h
, uint32_t src_x
,
400 uint32_t src_y
, uint32_t src_w
,
403 struct tegra_bo
*bo
= tegra_fb_get_plane(fb
, 0);
404 struct tegra_plane
*p
= to_tegra_plane(plane
);
405 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
406 struct tegra_dc_window window
;
409 memset(&window
, 0, sizeof(window
));
410 window
.src
.x
= src_x
>> 16;
411 window
.src
.y
= src_y
>> 16;
412 window
.src
.w
= src_w
>> 16;
413 window
.src
.h
= src_h
>> 16;
414 window
.dst
.x
= crtc_x
;
415 window
.dst
.y
= crtc_y
;
416 window
.dst
.w
= crtc_w
;
417 window
.dst
.h
= crtc_h
;
418 window
.format
= tegra_dc_format(fb
->pixel_format
, &window
.swap
);
419 window
.bits_per_pixel
= fb
->bits_per_pixel
;
420 window
.bottom_up
= tegra_fb_is_bottom_up(fb
);
422 err
= tegra_fb_get_tiling(fb
, &window
.tiling
);
426 window
.base
[0] = bo
->paddr
+ fb
->offsets
[0];
427 window
.stride
[0] = fb
->pitches
[0];
429 err
= tegra_dc_setup_window(dc
, p
->index
, &window
);
436 static void tegra_primary_plane_destroy(struct drm_plane
*plane
)
438 tegra_window_plane_disable(plane
);
439 tegra_plane_destroy(plane
);
442 static const struct drm_plane_funcs tegra_primary_plane_funcs
= {
443 .update_plane
= tegra_primary_plane_update
,
444 .disable_plane
= tegra_window_plane_disable
,
445 .destroy
= tegra_primary_plane_destroy
,
448 static struct drm_plane
*tegra_dc_primary_plane_create(struct drm_device
*drm
,
452 * Ideally this would use drm_crtc_mask(), but that would require the
453 * CRTC to already be in the mode_config's list of CRTCs. However, it
454 * will only be added to that list in the drm_crtc_init_with_planes()
455 * (in tegra_dc_init()), which in turn requires registration of these
456 * planes. So we have ourselves a nice little chicken and egg problem
459 * We work around this by manually creating the mask from the number
460 * of CRTCs that have been registered, and should therefore always be
461 * the same as drm_crtc_index() after registration.
463 unsigned long possible_crtcs
= 1 << drm
->mode_config
.num_crtc
;
464 struct tegra_plane
*plane
;
465 unsigned int num_formats
;
469 plane
= kzalloc(sizeof(*plane
), GFP_KERNEL
);
471 return ERR_PTR(-ENOMEM
);
473 num_formats
= ARRAY_SIZE(tegra_primary_plane_formats
);
474 formats
= tegra_primary_plane_formats
;
476 err
= drm_universal_plane_init(drm
, &plane
->base
, possible_crtcs
,
477 &tegra_primary_plane_funcs
, formats
,
478 num_formats
, DRM_PLANE_TYPE_PRIMARY
);
487 static const u32 tegra_cursor_plane_formats
[] = {
491 static int tegra_cursor_plane_update(struct drm_plane
*plane
,
492 struct drm_crtc
*crtc
,
493 struct drm_framebuffer
*fb
, int crtc_x
,
494 int crtc_y
, unsigned int crtc_w
,
495 unsigned int crtc_h
, uint32_t src_x
,
496 uint32_t src_y
, uint32_t src_w
,
499 struct tegra_bo
*bo
= tegra_fb_get_plane(fb
, 0);
500 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
501 u32 value
= CURSOR_CLIP_DISPLAY
;
503 /* scaling not supported for cursor */
504 if ((src_w
>> 16 != crtc_w
) || (src_h
>> 16 != crtc_h
))
507 /* only square cursors supported */
513 value
|= CURSOR_SIZE_32x32
;
517 value
|= CURSOR_SIZE_64x64
;
521 value
|= CURSOR_SIZE_128x128
;
525 value
|= CURSOR_SIZE_256x256
;
532 value
|= (bo
->paddr
>> 10) & 0x3fffff;
533 tegra_dc_writel(dc
, value
, DC_DISP_CURSOR_START_ADDR
);
535 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
536 value
= (bo
->paddr
>> 32) & 0x3;
537 tegra_dc_writel(dc
, value
, DC_DISP_CURSOR_START_ADDR_HI
);
540 /* enable cursor and set blend mode */
541 value
= tegra_dc_readl(dc
, DC_DISP_DISP_WIN_OPTIONS
);
542 value
|= CURSOR_ENABLE
;
543 tegra_dc_writel(dc
, value
, DC_DISP_DISP_WIN_OPTIONS
);
545 value
= tegra_dc_readl(dc
, DC_DISP_BLEND_CURSOR_CONTROL
);
546 value
&= ~CURSOR_DST_BLEND_MASK
;
547 value
&= ~CURSOR_SRC_BLEND_MASK
;
548 value
|= CURSOR_MODE_NORMAL
;
549 value
|= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC
;
550 value
|= CURSOR_SRC_BLEND_K1_TIMES_SRC
;
551 value
|= CURSOR_ALPHA
;
552 tegra_dc_writel(dc
, value
, DC_DISP_BLEND_CURSOR_CONTROL
);
554 /* position the cursor */
555 value
= (crtc_y
& 0x3fff) << 16 | (crtc_x
& 0x3fff);
556 tegra_dc_writel(dc
, value
, DC_DISP_CURSOR_POSITION
);
559 tegra_dc_cursor_commit(dc
);
565 static int tegra_cursor_plane_disable(struct drm_plane
*plane
)
567 struct tegra_dc
*dc
= to_tegra_dc(plane
->crtc
);
573 value
= tegra_dc_readl(dc
, DC_DISP_DISP_WIN_OPTIONS
);
574 value
&= ~CURSOR_ENABLE
;
575 tegra_dc_writel(dc
, value
, DC_DISP_DISP_WIN_OPTIONS
);
577 tegra_dc_cursor_commit(dc
);
583 static const struct drm_plane_funcs tegra_cursor_plane_funcs
= {
584 .update_plane
= tegra_cursor_plane_update
,
585 .disable_plane
= tegra_cursor_plane_disable
,
586 .destroy
= tegra_plane_destroy
,
589 static struct drm_plane
*tegra_dc_cursor_plane_create(struct drm_device
*drm
,
592 struct tegra_plane
*plane
;
593 unsigned int num_formats
;
597 plane
= kzalloc(sizeof(*plane
), GFP_KERNEL
);
599 return ERR_PTR(-ENOMEM
);
601 num_formats
= ARRAY_SIZE(tegra_cursor_plane_formats
);
602 formats
= tegra_cursor_plane_formats
;
604 err
= drm_universal_plane_init(drm
, &plane
->base
, 1 << dc
->pipe
,
605 &tegra_cursor_plane_funcs
, formats
,
606 num_formats
, DRM_PLANE_TYPE_CURSOR
);
615 static int tegra_overlay_plane_update(struct drm_plane
*plane
,
616 struct drm_crtc
*crtc
,
617 struct drm_framebuffer
*fb
, int crtc_x
,
618 int crtc_y
, unsigned int crtc_w
,
619 unsigned int crtc_h
, uint32_t src_x
,
620 uint32_t src_y
, uint32_t src_w
,
623 struct tegra_plane
*p
= to_tegra_plane(plane
);
624 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
625 struct tegra_dc_window window
;
629 memset(&window
, 0, sizeof(window
));
630 window
.src
.x
= src_x
>> 16;
631 window
.src
.y
= src_y
>> 16;
632 window
.src
.w
= src_w
>> 16;
633 window
.src
.h
= src_h
>> 16;
634 window
.dst
.x
= crtc_x
;
635 window
.dst
.y
= crtc_y
;
636 window
.dst
.w
= crtc_w
;
637 window
.dst
.h
= crtc_h
;
638 window
.format
= tegra_dc_format(fb
->pixel_format
, &window
.swap
);
639 window
.bits_per_pixel
= fb
->bits_per_pixel
;
640 window
.bottom_up
= tegra_fb_is_bottom_up(fb
);
642 err
= tegra_fb_get_tiling(fb
, &window
.tiling
);
646 for (i
= 0; i
< drm_format_num_planes(fb
->pixel_format
); i
++) {
647 struct tegra_bo
*bo
= tegra_fb_get_plane(fb
, i
);
649 window
.base
[i
] = bo
->paddr
+ fb
->offsets
[i
];
652 * Tegra doesn't support different strides for U and V planes
653 * so we display a warning if the user tries to display a
654 * framebuffer with such a configuration.
657 if (fb
->pitches
[i
] != window
.stride
[1])
658 DRM_ERROR("unsupported UV-plane configuration\n");
660 window
.stride
[i
] = fb
->pitches
[i
];
664 return tegra_dc_setup_window(dc
, p
->index
, &window
);
667 static void tegra_overlay_plane_destroy(struct drm_plane
*plane
)
669 tegra_window_plane_disable(plane
);
670 tegra_plane_destroy(plane
);
673 static const struct drm_plane_funcs tegra_overlay_plane_funcs
= {
674 .update_plane
= tegra_overlay_plane_update
,
675 .disable_plane
= tegra_window_plane_disable
,
676 .destroy
= tegra_overlay_plane_destroy
,
679 static const uint32_t tegra_overlay_plane_formats
[] = {
689 static struct drm_plane
*tegra_dc_overlay_plane_create(struct drm_device
*drm
,
693 struct tegra_plane
*plane
;
694 unsigned int num_formats
;
698 plane
= kzalloc(sizeof(*plane
), GFP_KERNEL
);
700 return ERR_PTR(-ENOMEM
);
702 plane
->index
= index
;
704 num_formats
= ARRAY_SIZE(tegra_overlay_plane_formats
);
705 formats
= tegra_overlay_plane_formats
;
707 err
= drm_universal_plane_init(drm
, &plane
->base
, 1 << dc
->pipe
,
708 &tegra_overlay_plane_funcs
, formats
,
709 num_formats
, DRM_PLANE_TYPE_OVERLAY
);
718 static int tegra_dc_add_planes(struct drm_device
*drm
, struct tegra_dc
*dc
)
720 struct drm_plane
*plane
;
723 for (i
= 0; i
< 2; i
++) {
724 plane
= tegra_dc_overlay_plane_create(drm
, dc
, 1 + i
);
726 return PTR_ERR(plane
);
732 static int tegra_dc_set_base(struct tegra_dc
*dc
, int x
, int y
,
733 struct drm_framebuffer
*fb
)
735 struct tegra_bo
*bo
= tegra_fb_get_plane(fb
, 0);
736 unsigned int h_offset
= 0, v_offset
= 0;
737 struct tegra_bo_tiling tiling
;
738 unsigned long value
, flags
;
739 unsigned int format
, swap
;
742 err
= tegra_fb_get_tiling(fb
, &tiling
);
746 spin_lock_irqsave(&dc
->lock
, flags
);
748 tegra_dc_writel(dc
, WINDOW_A_SELECT
, DC_CMD_DISPLAY_WINDOW_HEADER
);
750 value
= fb
->offsets
[0] + y
* fb
->pitches
[0] +
751 x
* fb
->bits_per_pixel
/ 8;
753 tegra_dc_writel(dc
, bo
->paddr
+ value
, DC_WINBUF_START_ADDR
);
754 tegra_dc_writel(dc
, fb
->pitches
[0], DC_WIN_LINE_STRIDE
);
756 format
= tegra_dc_format(fb
->pixel_format
, &swap
);
757 tegra_dc_writel(dc
, format
, DC_WIN_COLOR_DEPTH
);
758 tegra_dc_writel(dc
, swap
, DC_WIN_BYTE_SWAP
);
760 if (dc
->soc
->supports_block_linear
) {
761 unsigned long height
= tiling
.value
;
763 switch (tiling
.mode
) {
764 case TEGRA_BO_TILING_MODE_PITCH
:
765 value
= DC_WINBUF_SURFACE_KIND_PITCH
;
768 case TEGRA_BO_TILING_MODE_TILED
:
769 value
= DC_WINBUF_SURFACE_KIND_TILED
;
772 case TEGRA_BO_TILING_MODE_BLOCK
:
773 value
= DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height
) |
774 DC_WINBUF_SURFACE_KIND_BLOCK
;
778 tegra_dc_writel(dc
, value
, DC_WINBUF_SURFACE_KIND
);
780 switch (tiling
.mode
) {
781 case TEGRA_BO_TILING_MODE_PITCH
:
782 value
= DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV
|
783 DC_WIN_BUFFER_ADDR_MODE_LINEAR
;
786 case TEGRA_BO_TILING_MODE_TILED
:
787 value
= DC_WIN_BUFFER_ADDR_MODE_TILE_UV
|
788 DC_WIN_BUFFER_ADDR_MODE_TILE
;
791 case TEGRA_BO_TILING_MODE_BLOCK
:
792 DRM_ERROR("hardware doesn't support block linear mode\n");
793 spin_unlock_irqrestore(&dc
->lock
, flags
);
797 tegra_dc_writel(dc
, value
, DC_WIN_BUFFER_ADDR_MODE
);
800 /* make sure bottom-up buffers are properly displayed */
801 if (tegra_fb_is_bottom_up(fb
)) {
802 value
= tegra_dc_readl(dc
, DC_WIN_WIN_OPTIONS
);
803 value
|= V_DIRECTION
;
804 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
806 v_offset
+= fb
->height
- 1;
808 value
= tegra_dc_readl(dc
, DC_WIN_WIN_OPTIONS
);
809 value
&= ~V_DIRECTION
;
810 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
813 tegra_dc_writel(dc
, h_offset
, DC_WINBUF_ADDR_H_OFFSET
);
814 tegra_dc_writel(dc
, v_offset
, DC_WINBUF_ADDR_V_OFFSET
);
816 value
= GENERAL_ACT_REQ
| WIN_A_ACT_REQ
;
817 tegra_dc_writel(dc
, value
<< 8, DC_CMD_STATE_CONTROL
);
818 tegra_dc_writel(dc
, value
, DC_CMD_STATE_CONTROL
);
820 spin_unlock_irqrestore(&dc
->lock
, flags
);
825 void tegra_dc_enable_vblank(struct tegra_dc
*dc
)
827 unsigned long value
, flags
;
829 spin_lock_irqsave(&dc
->lock
, flags
);
831 value
= tegra_dc_readl(dc
, DC_CMD_INT_MASK
);
833 tegra_dc_writel(dc
, value
, DC_CMD_INT_MASK
);
835 spin_unlock_irqrestore(&dc
->lock
, flags
);
838 void tegra_dc_disable_vblank(struct tegra_dc
*dc
)
840 unsigned long value
, flags
;
842 spin_lock_irqsave(&dc
->lock
, flags
);
844 value
= tegra_dc_readl(dc
, DC_CMD_INT_MASK
);
845 value
&= ~VBLANK_INT
;
846 tegra_dc_writel(dc
, value
, DC_CMD_INT_MASK
);
848 spin_unlock_irqrestore(&dc
->lock
, flags
);
851 static void tegra_dc_finish_page_flip(struct tegra_dc
*dc
)
853 struct drm_device
*drm
= dc
->base
.dev
;
854 struct drm_crtc
*crtc
= &dc
->base
;
855 unsigned long flags
, base
;
858 spin_lock_irqsave(&drm
->event_lock
, flags
);
861 spin_unlock_irqrestore(&drm
->event_lock
, flags
);
865 bo
= tegra_fb_get_plane(crtc
->primary
->fb
, 0);
867 spin_lock_irqsave(&dc
->lock
, flags
);
869 /* check if new start address has been latched */
870 tegra_dc_writel(dc
, WINDOW_A_SELECT
, DC_CMD_DISPLAY_WINDOW_HEADER
);
871 tegra_dc_writel(dc
, READ_MUX
, DC_CMD_STATE_ACCESS
);
872 base
= tegra_dc_readl(dc
, DC_WINBUF_START_ADDR
);
873 tegra_dc_writel(dc
, 0, DC_CMD_STATE_ACCESS
);
875 spin_unlock_irqrestore(&dc
->lock
, flags
);
877 if (base
== bo
->paddr
+ crtc
->primary
->fb
->offsets
[0]) {
878 drm_crtc_send_vblank_event(crtc
, dc
->event
);
879 drm_crtc_vblank_put(crtc
);
883 spin_unlock_irqrestore(&drm
->event_lock
, flags
);
886 void tegra_dc_cancel_page_flip(struct drm_crtc
*crtc
, struct drm_file
*file
)
888 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
889 struct drm_device
*drm
= crtc
->dev
;
892 spin_lock_irqsave(&drm
->event_lock
, flags
);
894 if (dc
->event
&& dc
->event
->base
.file_priv
== file
) {
895 dc
->event
->base
.destroy(&dc
->event
->base
);
896 drm_crtc_vblank_put(crtc
);
900 spin_unlock_irqrestore(&drm
->event_lock
, flags
);
903 static int tegra_dc_page_flip(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
904 struct drm_pending_vblank_event
*event
, uint32_t page_flip_flags
)
906 unsigned int pipe
= drm_crtc_index(crtc
);
907 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
915 drm_crtc_vblank_get(crtc
);
918 tegra_dc_set_base(dc
, 0, 0, fb
);
919 crtc
->primary
->fb
= fb
;
924 static void tegra_dc_destroy(struct drm_crtc
*crtc
)
926 drm_crtc_cleanup(crtc
);
929 static const struct drm_crtc_funcs tegra_crtc_funcs
= {
930 .page_flip
= tegra_dc_page_flip
,
931 .set_config
= drm_crtc_helper_set_config
,
932 .destroy
= tegra_dc_destroy
,
935 static void tegra_crtc_disable(struct drm_crtc
*crtc
)
937 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
938 struct drm_device
*drm
= crtc
->dev
;
939 struct drm_plane
*plane
;
941 drm_for_each_legacy_plane(plane
, &drm
->mode_config
.plane_list
) {
942 if (plane
->crtc
== crtc
) {
943 tegra_window_plane_disable(plane
);
947 drm_framebuffer_unreference(plane
->fb
);
953 drm_crtc_vblank_off(crtc
);
957 static bool tegra_crtc_mode_fixup(struct drm_crtc
*crtc
,
958 const struct drm_display_mode
*mode
,
959 struct drm_display_mode
*adjusted
)
964 static int tegra_dc_set_timings(struct tegra_dc
*dc
,
965 struct drm_display_mode
*mode
)
967 unsigned int h_ref_to_sync
= 1;
968 unsigned int v_ref_to_sync
= 1;
971 tegra_dc_writel(dc
, 0x0, DC_DISP_DISP_TIMING_OPTIONS
);
973 value
= (v_ref_to_sync
<< 16) | h_ref_to_sync
;
974 tegra_dc_writel(dc
, value
, DC_DISP_REF_TO_SYNC
);
976 value
= ((mode
->vsync_end
- mode
->vsync_start
) << 16) |
977 ((mode
->hsync_end
- mode
->hsync_start
) << 0);
978 tegra_dc_writel(dc
, value
, DC_DISP_SYNC_WIDTH
);
980 value
= ((mode
->vtotal
- mode
->vsync_end
) << 16) |
981 ((mode
->htotal
- mode
->hsync_end
) << 0);
982 tegra_dc_writel(dc
, value
, DC_DISP_BACK_PORCH
);
984 value
= ((mode
->vsync_start
- mode
->vdisplay
) << 16) |
985 ((mode
->hsync_start
- mode
->hdisplay
) << 0);
986 tegra_dc_writel(dc
, value
, DC_DISP_FRONT_PORCH
);
988 value
= (mode
->vdisplay
<< 16) | mode
->hdisplay
;
989 tegra_dc_writel(dc
, value
, DC_DISP_ACTIVE
);
994 static int tegra_crtc_setup_clk(struct drm_crtc
*crtc
,
995 struct drm_display_mode
*mode
)
997 unsigned long pclk
= mode
->clock
* 1000;
998 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
999 struct tegra_output
*output
= NULL
;
1000 struct drm_encoder
*encoder
;
1005 list_for_each_entry(encoder
, &crtc
->dev
->mode_config
.encoder_list
, head
)
1006 if (encoder
->crtc
== crtc
) {
1007 output
= encoder_to_output(encoder
);
1015 * This assumes that the parent clock is pll_d_out0 or pll_d2_out
1016 * respectively, each of which divides the base pll_d by 2.
1018 err
= tegra_output_setup_clock(output
, dc
->clk
, pclk
, &div
);
1020 dev_err(dc
->dev
, "failed to setup clock: %ld\n", err
);
1024 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc
->clk
), div
);
1026 value
= SHIFT_CLK_DIVIDER(div
) | PIXEL_CLK_DIVIDER_PCD1
;
1027 tegra_dc_writel(dc
, value
, DC_DISP_DISP_CLOCK_CONTROL
);
1032 static int tegra_crtc_mode_set(struct drm_crtc
*crtc
,
1033 struct drm_display_mode
*mode
,
1034 struct drm_display_mode
*adjusted
,
1035 int x
, int y
, struct drm_framebuffer
*old_fb
)
1037 struct tegra_bo
*bo
= tegra_fb_get_plane(crtc
->primary
->fb
, 0);
1038 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
1039 struct tegra_dc_window window
;
1043 err
= tegra_crtc_setup_clk(crtc
, mode
);
1045 dev_err(dc
->dev
, "failed to setup clock for CRTC: %d\n", err
);
1049 /* program display mode */
1050 tegra_dc_set_timings(dc
, mode
);
1052 if (dc
->soc
->supports_border_color
)
1053 tegra_dc_writel(dc
, 0, DC_DISP_BORDER_COLOR
);
1055 /* interlacing isn't supported yet, so disable it */
1056 if (dc
->soc
->supports_interlacing
) {
1057 value
= tegra_dc_readl(dc
, DC_DISP_INTERLACE_CONTROL
);
1058 value
&= ~INTERLACE_ENABLE
;
1059 tegra_dc_writel(dc
, value
, DC_DISP_INTERLACE_CONTROL
);
1062 /* setup window parameters */
1063 memset(&window
, 0, sizeof(window
));
1066 window
.src
.w
= mode
->hdisplay
;
1067 window
.src
.h
= mode
->vdisplay
;
1070 window
.dst
.w
= mode
->hdisplay
;
1071 window
.dst
.h
= mode
->vdisplay
;
1072 window
.format
= tegra_dc_format(crtc
->primary
->fb
->pixel_format
,
1074 window
.bits_per_pixel
= crtc
->primary
->fb
->bits_per_pixel
;
1075 window
.stride
[0] = crtc
->primary
->fb
->pitches
[0];
1076 window
.base
[0] = bo
->paddr
;
1078 err
= tegra_dc_setup_window(dc
, 0, &window
);
1080 dev_err(dc
->dev
, "failed to enable root plane\n");
1085 static int tegra_crtc_mode_set_base(struct drm_crtc
*crtc
, int x
, int y
,
1086 struct drm_framebuffer
*old_fb
)
1088 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
1090 return tegra_dc_set_base(dc
, x
, y
, crtc
->primary
->fb
);
1093 static void tegra_crtc_prepare(struct drm_crtc
*crtc
)
1095 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
1096 unsigned int syncpt
;
1097 unsigned long value
;
1099 drm_crtc_vblank_off(crtc
);
1101 /* hardware initialization */
1102 reset_control_deassert(dc
->rst
);
1103 usleep_range(10000, 20000);
1106 syncpt
= SYNCPT_VBLANK1
;
1108 syncpt
= SYNCPT_VBLANK0
;
1110 /* initialize display controller */
1111 tegra_dc_writel(dc
, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL
);
1112 tegra_dc_writel(dc
, 0x100 | syncpt
, DC_CMD_CONT_SYNCPT_VSYNC
);
1114 value
= WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
| WIN_A_OF_INT
;
1115 tegra_dc_writel(dc
, value
, DC_CMD_INT_TYPE
);
1117 value
= WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
|
1118 WIN_A_OF_INT
| WIN_B_OF_INT
| WIN_C_OF_INT
;
1119 tegra_dc_writel(dc
, value
, DC_CMD_INT_POLARITY
);
1121 /* initialize timer */
1122 value
= CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1123 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1124 tegra_dc_writel(dc
, value
, DC_DISP_DISP_MEM_HIGH_PRIORITY
);
1126 value
= CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1127 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1128 tegra_dc_writel(dc
, value
, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER
);
1130 value
= VBLANK_INT
| WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
;
1131 tegra_dc_writel(dc
, value
, DC_CMD_INT_ENABLE
);
1133 value
= WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
;
1134 tegra_dc_writel(dc
, value
, DC_CMD_INT_MASK
);
1137 static void tegra_crtc_commit(struct drm_crtc
*crtc
)
1139 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
1141 drm_crtc_vblank_on(crtc
);
1142 tegra_dc_commit(dc
);
1145 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs
= {
1146 .disable
= tegra_crtc_disable
,
1147 .mode_fixup
= tegra_crtc_mode_fixup
,
1148 .mode_set
= tegra_crtc_mode_set
,
1149 .mode_set_base
= tegra_crtc_mode_set_base
,
1150 .prepare
= tegra_crtc_prepare
,
1151 .commit
= tegra_crtc_commit
,
1154 static irqreturn_t
tegra_dc_irq(int irq
, void *data
)
1156 struct tegra_dc
*dc
= data
;
1157 unsigned long status
;
1159 status
= tegra_dc_readl(dc
, DC_CMD_INT_STATUS
);
1160 tegra_dc_writel(dc
, status
, DC_CMD_INT_STATUS
);
1162 if (status
& FRAME_END_INT
) {
1164 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1168 if (status
& VBLANK_INT
) {
1170 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1172 drm_crtc_handle_vblank(&dc
->base
);
1173 tegra_dc_finish_page_flip(dc
);
1176 if (status
& (WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
)) {
1178 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1185 static int tegra_dc_show_regs(struct seq_file
*s
, void *data
)
1187 struct drm_info_node
*node
= s
->private;
1188 struct tegra_dc
*dc
= node
->info_ent
->data
;
1190 #define DUMP_REG(name) \
1191 seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
1192 tegra_dc_readl(dc, name))
1194 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT
);
1195 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL
);
1196 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR
);
1197 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT
);
1198 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL
);
1199 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR
);
1200 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT
);
1201 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL
);
1202 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR
);
1203 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT
);
1204 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL
);
1205 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR
);
1206 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC
);
1207 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0
);
1208 DUMP_REG(DC_CMD_DISPLAY_COMMAND
);
1209 DUMP_REG(DC_CMD_SIGNAL_RAISE
);
1210 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL
);
1211 DUMP_REG(DC_CMD_INT_STATUS
);
1212 DUMP_REG(DC_CMD_INT_MASK
);
1213 DUMP_REG(DC_CMD_INT_ENABLE
);
1214 DUMP_REG(DC_CMD_INT_TYPE
);
1215 DUMP_REG(DC_CMD_INT_POLARITY
);
1216 DUMP_REG(DC_CMD_SIGNAL_RAISE1
);
1217 DUMP_REG(DC_CMD_SIGNAL_RAISE2
);
1218 DUMP_REG(DC_CMD_SIGNAL_RAISE3
);
1219 DUMP_REG(DC_CMD_STATE_ACCESS
);
1220 DUMP_REG(DC_CMD_STATE_CONTROL
);
1221 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER
);
1222 DUMP_REG(DC_CMD_REG_ACT_CONTROL
);
1223 DUMP_REG(DC_COM_CRC_CONTROL
);
1224 DUMP_REG(DC_COM_CRC_CHECKSUM
);
1225 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1226 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1227 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1228 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1229 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1230 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1231 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1232 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1233 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1234 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1235 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1236 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1237 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1238 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1239 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1240 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1241 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1242 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1243 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1244 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1245 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1246 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1247 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1248 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1249 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1250 DUMP_REG(DC_COM_PIN_MISC_CONTROL
);
1251 DUMP_REG(DC_COM_PIN_PM0_CONTROL
);
1252 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE
);
1253 DUMP_REG(DC_COM_PIN_PM1_CONTROL
);
1254 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE
);
1255 DUMP_REG(DC_COM_SPI_CONTROL
);
1256 DUMP_REG(DC_COM_SPI_START_BYTE
);
1257 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB
);
1258 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD
);
1259 DUMP_REG(DC_COM_HSPI_CS_DC
);
1260 DUMP_REG(DC_COM_SCRATCH_REGISTER_A
);
1261 DUMP_REG(DC_COM_SCRATCH_REGISTER_B
);
1262 DUMP_REG(DC_COM_GPIO_CTRL
);
1263 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER
);
1264 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED
);
1265 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0
);
1266 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1
);
1267 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS
);
1268 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY
);
1269 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER
);
1270 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS
);
1271 DUMP_REG(DC_DISP_REF_TO_SYNC
);
1272 DUMP_REG(DC_DISP_SYNC_WIDTH
);
1273 DUMP_REG(DC_DISP_BACK_PORCH
);
1274 DUMP_REG(DC_DISP_ACTIVE
);
1275 DUMP_REG(DC_DISP_FRONT_PORCH
);
1276 DUMP_REG(DC_DISP_H_PULSE0_CONTROL
);
1277 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A
);
1278 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B
);
1279 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C
);
1280 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D
);
1281 DUMP_REG(DC_DISP_H_PULSE1_CONTROL
);
1282 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A
);
1283 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B
);
1284 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C
);
1285 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D
);
1286 DUMP_REG(DC_DISP_H_PULSE2_CONTROL
);
1287 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A
);
1288 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B
);
1289 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C
);
1290 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D
);
1291 DUMP_REG(DC_DISP_V_PULSE0_CONTROL
);
1292 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A
);
1293 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B
);
1294 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C
);
1295 DUMP_REG(DC_DISP_V_PULSE1_CONTROL
);
1296 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A
);
1297 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B
);
1298 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C
);
1299 DUMP_REG(DC_DISP_V_PULSE2_CONTROL
);
1300 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A
);
1301 DUMP_REG(DC_DISP_V_PULSE3_CONTROL
);
1302 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A
);
1303 DUMP_REG(DC_DISP_M0_CONTROL
);
1304 DUMP_REG(DC_DISP_M1_CONTROL
);
1305 DUMP_REG(DC_DISP_DI_CONTROL
);
1306 DUMP_REG(DC_DISP_PP_CONTROL
);
1307 DUMP_REG(DC_DISP_PP_SELECT_A
);
1308 DUMP_REG(DC_DISP_PP_SELECT_B
);
1309 DUMP_REG(DC_DISP_PP_SELECT_C
);
1310 DUMP_REG(DC_DISP_PP_SELECT_D
);
1311 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL
);
1312 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL
);
1313 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL
);
1314 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS
);
1315 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS
);
1316 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS
);
1317 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS
);
1318 DUMP_REG(DC_DISP_BORDER_COLOR
);
1319 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER
);
1320 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER
);
1321 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER
);
1322 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER
);
1323 DUMP_REG(DC_DISP_CURSOR_FOREGROUND
);
1324 DUMP_REG(DC_DISP_CURSOR_BACKGROUND
);
1325 DUMP_REG(DC_DISP_CURSOR_START_ADDR
);
1326 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS
);
1327 DUMP_REG(DC_DISP_CURSOR_POSITION
);
1328 DUMP_REG(DC_DISP_CURSOR_POSITION_NS
);
1329 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL
);
1330 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A
);
1331 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B
);
1332 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C
);
1333 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D
);
1334 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL
);
1335 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST
);
1336 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST
);
1337 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST
);
1338 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST
);
1339 DUMP_REG(DC_DISP_DAC_CRT_CTRL
);
1340 DUMP_REG(DC_DISP_DISP_MISC_CONTROL
);
1341 DUMP_REG(DC_DISP_SD_CONTROL
);
1342 DUMP_REG(DC_DISP_SD_CSC_COEFF
);
1343 DUMP_REG(DC_DISP_SD_LUT(0));
1344 DUMP_REG(DC_DISP_SD_LUT(1));
1345 DUMP_REG(DC_DISP_SD_LUT(2));
1346 DUMP_REG(DC_DISP_SD_LUT(3));
1347 DUMP_REG(DC_DISP_SD_LUT(4));
1348 DUMP_REG(DC_DISP_SD_LUT(5));
1349 DUMP_REG(DC_DISP_SD_LUT(6));
1350 DUMP_REG(DC_DISP_SD_LUT(7));
1351 DUMP_REG(DC_DISP_SD_LUT(8));
1352 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL
);
1353 DUMP_REG(DC_DISP_DC_PIXEL_COUNT
);
1354 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1355 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1356 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1357 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1358 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1359 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1360 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1361 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1362 DUMP_REG(DC_DISP_SD_BL_TF(0));
1363 DUMP_REG(DC_DISP_SD_BL_TF(1));
1364 DUMP_REG(DC_DISP_SD_BL_TF(2));
1365 DUMP_REG(DC_DISP_SD_BL_TF(3));
1366 DUMP_REG(DC_DISP_SD_BL_CONTROL
);
1367 DUMP_REG(DC_DISP_SD_HW_K_VALUES
);
1368 DUMP_REG(DC_DISP_SD_MAN_K_VALUES
);
1369 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI
);
1370 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL
);
1371 DUMP_REG(DC_WIN_WIN_OPTIONS
);
1372 DUMP_REG(DC_WIN_BYTE_SWAP
);
1373 DUMP_REG(DC_WIN_BUFFER_CONTROL
);
1374 DUMP_REG(DC_WIN_COLOR_DEPTH
);
1375 DUMP_REG(DC_WIN_POSITION
);
1376 DUMP_REG(DC_WIN_SIZE
);
1377 DUMP_REG(DC_WIN_PRESCALED_SIZE
);
1378 DUMP_REG(DC_WIN_H_INITIAL_DDA
);
1379 DUMP_REG(DC_WIN_V_INITIAL_DDA
);
1380 DUMP_REG(DC_WIN_DDA_INC
);
1381 DUMP_REG(DC_WIN_LINE_STRIDE
);
1382 DUMP_REG(DC_WIN_BUF_STRIDE
);
1383 DUMP_REG(DC_WIN_UV_BUF_STRIDE
);
1384 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE
);
1385 DUMP_REG(DC_WIN_DV_CONTROL
);
1386 DUMP_REG(DC_WIN_BLEND_NOKEY
);
1387 DUMP_REG(DC_WIN_BLEND_1WIN
);
1388 DUMP_REG(DC_WIN_BLEND_2WIN_X
);
1389 DUMP_REG(DC_WIN_BLEND_2WIN_Y
);
1390 DUMP_REG(DC_WIN_BLEND_3WIN_XY
);
1391 DUMP_REG(DC_WIN_HP_FETCH_CONTROL
);
1392 DUMP_REG(DC_WINBUF_START_ADDR
);
1393 DUMP_REG(DC_WINBUF_START_ADDR_NS
);
1394 DUMP_REG(DC_WINBUF_START_ADDR_U
);
1395 DUMP_REG(DC_WINBUF_START_ADDR_U_NS
);
1396 DUMP_REG(DC_WINBUF_START_ADDR_V
);
1397 DUMP_REG(DC_WINBUF_START_ADDR_V_NS
);
1398 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET
);
1399 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS
);
1400 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET
);
1401 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS
);
1402 DUMP_REG(DC_WINBUF_UFLOW_STATUS
);
1403 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS
);
1404 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS
);
1405 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS
);
1412 static struct drm_info_list debugfs_files
[] = {
1413 { "regs", tegra_dc_show_regs
, 0, NULL
},
1416 static int tegra_dc_debugfs_init(struct tegra_dc
*dc
, struct drm_minor
*minor
)
1422 name
= kasprintf(GFP_KERNEL
, "dc.%d", dc
->pipe
);
1423 dc
->debugfs
= debugfs_create_dir(name
, minor
->debugfs_root
);
1429 dc
->debugfs_files
= kmemdup(debugfs_files
, sizeof(debugfs_files
),
1431 if (!dc
->debugfs_files
) {
1436 for (i
= 0; i
< ARRAY_SIZE(debugfs_files
); i
++)
1437 dc
->debugfs_files
[i
].data
= dc
;
1439 err
= drm_debugfs_create_files(dc
->debugfs_files
,
1440 ARRAY_SIZE(debugfs_files
),
1441 dc
->debugfs
, minor
);
1450 kfree(dc
->debugfs_files
);
1451 dc
->debugfs_files
= NULL
;
1453 debugfs_remove(dc
->debugfs
);
1459 static int tegra_dc_debugfs_exit(struct tegra_dc
*dc
)
1461 drm_debugfs_remove_files(dc
->debugfs_files
, ARRAY_SIZE(debugfs_files
),
1465 kfree(dc
->debugfs_files
);
1466 dc
->debugfs_files
= NULL
;
1468 debugfs_remove(dc
->debugfs
);
1474 static int tegra_dc_init(struct host1x_client
*client
)
1476 struct drm_device
*drm
= dev_get_drvdata(client
->parent
);
1477 struct tegra_dc
*dc
= host1x_client_to_dc(client
);
1478 struct tegra_drm
*tegra
= drm
->dev_private
;
1479 struct drm_plane
*primary
= NULL
;
1480 struct drm_plane
*cursor
= NULL
;
1483 if (tegra
->domain
) {
1484 err
= iommu_attach_device(tegra
->domain
, dc
->dev
);
1486 dev_err(dc
->dev
, "failed to attach to domain: %d\n",
1491 dc
->domain
= tegra
->domain
;
1494 primary
= tegra_dc_primary_plane_create(drm
, dc
);
1495 if (IS_ERR(primary
)) {
1496 err
= PTR_ERR(primary
);
1500 if (dc
->soc
->supports_cursor
) {
1501 cursor
= tegra_dc_cursor_plane_create(drm
, dc
);
1502 if (IS_ERR(cursor
)) {
1503 err
= PTR_ERR(cursor
);
1508 err
= drm_crtc_init_with_planes(drm
, &dc
->base
, primary
, cursor
,
1513 drm_mode_crtc_set_gamma_size(&dc
->base
, 256);
1514 drm_crtc_helper_add(&dc
->base
, &tegra_crtc_helper_funcs
);
1517 * Keep track of the minimum pitch alignment across all display
1520 if (dc
->soc
->pitch_align
> tegra
->pitch_align
)
1521 tegra
->pitch_align
= dc
->soc
->pitch_align
;
1523 err
= tegra_dc_rgb_init(drm
, dc
);
1524 if (err
< 0 && err
!= -ENODEV
) {
1525 dev_err(dc
->dev
, "failed to initialize RGB output: %d\n", err
);
1529 err
= tegra_dc_add_planes(drm
, dc
);
1533 if (IS_ENABLED(CONFIG_DEBUG_FS
)) {
1534 err
= tegra_dc_debugfs_init(dc
, drm
->primary
);
1536 dev_err(dc
->dev
, "debugfs setup failed: %d\n", err
);
1539 err
= devm_request_irq(dc
->dev
, dc
->irq
, tegra_dc_irq
, 0,
1540 dev_name(dc
->dev
), dc
);
1542 dev_err(dc
->dev
, "failed to request IRQ#%u: %d\n", dc
->irq
,
1551 drm_plane_cleanup(cursor
);
1554 drm_plane_cleanup(primary
);
1556 if (tegra
->domain
) {
1557 iommu_detach_device(tegra
->domain
, dc
->dev
);
1564 static int tegra_dc_exit(struct host1x_client
*client
)
1566 struct tegra_dc
*dc
= host1x_client_to_dc(client
);
1569 devm_free_irq(dc
->dev
, dc
->irq
, dc
);
1571 if (IS_ENABLED(CONFIG_DEBUG_FS
)) {
1572 err
= tegra_dc_debugfs_exit(dc
);
1574 dev_err(dc
->dev
, "debugfs cleanup failed: %d\n", err
);
1577 err
= tegra_dc_rgb_exit(dc
);
1579 dev_err(dc
->dev
, "failed to shutdown RGB output: %d\n", err
);
1584 iommu_detach_device(dc
->domain
, dc
->dev
);
1591 static const struct host1x_client_ops dc_client_ops
= {
1592 .init
= tegra_dc_init
,
1593 .exit
= tegra_dc_exit
,
1596 static const struct tegra_dc_soc_info tegra20_dc_soc_info
= {
1597 .supports_border_color
= true,
1598 .supports_interlacing
= false,
1599 .supports_cursor
= false,
1600 .supports_block_linear
= false,
1602 .has_powergate
= false,
1605 static const struct tegra_dc_soc_info tegra30_dc_soc_info
= {
1606 .supports_border_color
= true,
1607 .supports_interlacing
= false,
1608 .supports_cursor
= false,
1609 .supports_block_linear
= false,
1611 .has_powergate
= false,
1614 static const struct tegra_dc_soc_info tegra114_dc_soc_info
= {
1615 .supports_border_color
= true,
1616 .supports_interlacing
= false,
1617 .supports_cursor
= false,
1618 .supports_block_linear
= false,
1620 .has_powergate
= true,
1623 static const struct tegra_dc_soc_info tegra124_dc_soc_info
= {
1624 .supports_border_color
= false,
1625 .supports_interlacing
= true,
1626 .supports_cursor
= true,
1627 .supports_block_linear
= true,
1629 .has_powergate
= true,
1632 static const struct of_device_id tegra_dc_of_match
[] = {
1634 .compatible
= "nvidia,tegra124-dc",
1635 .data
= &tegra124_dc_soc_info
,
1637 .compatible
= "nvidia,tegra114-dc",
1638 .data
= &tegra114_dc_soc_info
,
1640 .compatible
= "nvidia,tegra30-dc",
1641 .data
= &tegra30_dc_soc_info
,
1643 .compatible
= "nvidia,tegra20-dc",
1644 .data
= &tegra20_dc_soc_info
,
1649 MODULE_DEVICE_TABLE(of
, tegra_dc_of_match
);
1651 static int tegra_dc_parse_dt(struct tegra_dc
*dc
)
1653 struct device_node
*np
;
1657 err
= of_property_read_u32(dc
->dev
->of_node
, "nvidia,head", &value
);
1659 dev_err(dc
->dev
, "missing \"nvidia,head\" property\n");
1662 * If the nvidia,head property isn't present, try to find the
1663 * correct head number by looking up the position of this
1664 * display controller's node within the device tree. Assuming
1665 * that the nodes are ordered properly in the DTS file and
1666 * that the translation into a flattened device tree blob
1667 * preserves that ordering this will actually yield the right
1670 * If those assumptions don't hold, this will still work for
1671 * cases where only a single display controller is used.
1673 for_each_matching_node(np
, tegra_dc_of_match
) {
1674 if (np
== dc
->dev
->of_node
)
1686 static int tegra_dc_probe(struct platform_device
*pdev
)
1688 const struct of_device_id
*id
;
1689 struct resource
*regs
;
1690 struct tegra_dc
*dc
;
1693 dc
= devm_kzalloc(&pdev
->dev
, sizeof(*dc
), GFP_KERNEL
);
1697 id
= of_match_node(tegra_dc_of_match
, pdev
->dev
.of_node
);
1701 spin_lock_init(&dc
->lock
);
1702 INIT_LIST_HEAD(&dc
->list
);
1703 dc
->dev
= &pdev
->dev
;
1706 err
= tegra_dc_parse_dt(dc
);
1710 dc
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1711 if (IS_ERR(dc
->clk
)) {
1712 dev_err(&pdev
->dev
, "failed to get clock\n");
1713 return PTR_ERR(dc
->clk
);
1716 dc
->rst
= devm_reset_control_get(&pdev
->dev
, "dc");
1717 if (IS_ERR(dc
->rst
)) {
1718 dev_err(&pdev
->dev
, "failed to get reset\n");
1719 return PTR_ERR(dc
->rst
);
1722 if (dc
->soc
->has_powergate
) {
1724 dc
->powergate
= TEGRA_POWERGATE_DIS
;
1726 dc
->powergate
= TEGRA_POWERGATE_DISB
;
1728 err
= tegra_powergate_sequence_power_up(dc
->powergate
, dc
->clk
,
1731 dev_err(&pdev
->dev
, "failed to power partition: %d\n",
1736 err
= clk_prepare_enable(dc
->clk
);
1738 dev_err(&pdev
->dev
, "failed to enable clock: %d\n",
1743 err
= reset_control_deassert(dc
->rst
);
1745 dev_err(&pdev
->dev
, "failed to deassert reset: %d\n",
1751 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1752 dc
->regs
= devm_ioremap_resource(&pdev
->dev
, regs
);
1753 if (IS_ERR(dc
->regs
))
1754 return PTR_ERR(dc
->regs
);
1756 dc
->irq
= platform_get_irq(pdev
, 0);
1758 dev_err(&pdev
->dev
, "failed to get IRQ\n");
1762 INIT_LIST_HEAD(&dc
->client
.list
);
1763 dc
->client
.ops
= &dc_client_ops
;
1764 dc
->client
.dev
= &pdev
->dev
;
1766 err
= tegra_dc_rgb_probe(dc
);
1767 if (err
< 0 && err
!= -ENODEV
) {
1768 dev_err(&pdev
->dev
, "failed to probe RGB output: %d\n", err
);
1772 err
= host1x_client_register(&dc
->client
);
1774 dev_err(&pdev
->dev
, "failed to register host1x client: %d\n",
1779 platform_set_drvdata(pdev
, dc
);
1784 static int tegra_dc_remove(struct platform_device
*pdev
)
1786 struct tegra_dc
*dc
= platform_get_drvdata(pdev
);
1789 err
= host1x_client_unregister(&dc
->client
);
1791 dev_err(&pdev
->dev
, "failed to unregister host1x client: %d\n",
1796 err
= tegra_dc_rgb_remove(dc
);
1798 dev_err(&pdev
->dev
, "failed to remove RGB output: %d\n", err
);
1802 reset_control_assert(dc
->rst
);
1804 if (dc
->soc
->has_powergate
)
1805 tegra_powergate_power_off(dc
->powergate
);
1807 clk_disable_unprepare(dc
->clk
);
1812 struct platform_driver tegra_dc_driver
= {
1815 .owner
= THIS_MODULE
,
1816 .of_match_table
= tegra_dc_of_match
,
1818 .probe
= tegra_dc_probe
,
1819 .remove
= tegra_dc_remove
,