2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/iommu.h>
13 #include <linux/reset.h>
15 #include <soc/tegra/pmc.h>
21 #include <drm/drm_plane_helper.h>
23 struct tegra_dc_soc_info
{
24 bool supports_border_color
;
25 bool supports_interlacing
;
27 bool supports_block_linear
;
28 unsigned int pitch_align
;
33 struct drm_plane base
;
37 static inline struct tegra_plane
*to_tegra_plane(struct drm_plane
*plane
)
39 return container_of(plane
, struct tegra_plane
, base
);
42 static void tegra_dc_window_commit(struct tegra_dc
*dc
, unsigned int index
)
44 u32 value
= WIN_A_ACT_REQ
<< index
;
46 tegra_dc_writel(dc
, value
<< 8, DC_CMD_STATE_CONTROL
);
47 tegra_dc_writel(dc
, value
, DC_CMD_STATE_CONTROL
);
50 static void tegra_dc_cursor_commit(struct tegra_dc
*dc
)
52 tegra_dc_writel(dc
, CURSOR_ACT_REQ
<< 8, DC_CMD_STATE_CONTROL
);
53 tegra_dc_writel(dc
, CURSOR_ACT_REQ
, DC_CMD_STATE_CONTROL
);
57 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
58 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
59 * Latching happens mmediately if the display controller is in STOP mode or
60 * on the next frame boundary otherwise.
62 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
63 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
64 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
65 * into the ACTIVE copy, either immediately if the display controller is in
66 * STOP mode, or at the next frame boundary otherwise.
68 static void tegra_dc_commit(struct tegra_dc
*dc
)
70 tegra_dc_writel(dc
, GENERAL_ACT_REQ
<< 8, DC_CMD_STATE_CONTROL
);
71 tegra_dc_writel(dc
, GENERAL_ACT_REQ
, DC_CMD_STATE_CONTROL
);
74 static unsigned int tegra_dc_format(uint32_t format
, uint32_t *swap
)
76 /* assume no swapping of fetched data */
78 *swap
= BYTE_SWAP_NOSWAP
;
81 case DRM_FORMAT_XBGR8888
:
82 return WIN_COLOR_DEPTH_R8G8B8A8
;
84 case DRM_FORMAT_XRGB8888
:
85 return WIN_COLOR_DEPTH_B8G8R8A8
;
87 case DRM_FORMAT_RGB565
:
88 return WIN_COLOR_DEPTH_B5G6R5
;
91 return WIN_COLOR_DEPTH_YCbCr422
;
95 *swap
= BYTE_SWAP_SWAP2
;
97 return WIN_COLOR_DEPTH_YCbCr422
;
99 case DRM_FORMAT_YUV420
:
100 return WIN_COLOR_DEPTH_YCbCr420P
;
102 case DRM_FORMAT_YUV422
:
103 return WIN_COLOR_DEPTH_YCbCr422P
;
109 WARN(1, "unsupported pixel format %u, using default\n", format
);
110 return WIN_COLOR_DEPTH_B8G8R8A8
;
113 static bool tegra_dc_format_is_yuv(unsigned int format
, bool *planar
)
116 case WIN_COLOR_DEPTH_YCbCr422
:
117 case WIN_COLOR_DEPTH_YUV422
:
123 case WIN_COLOR_DEPTH_YCbCr420P
:
124 case WIN_COLOR_DEPTH_YUV420P
:
125 case WIN_COLOR_DEPTH_YCbCr422P
:
126 case WIN_COLOR_DEPTH_YUV422P
:
127 case WIN_COLOR_DEPTH_YCbCr422R
:
128 case WIN_COLOR_DEPTH_YUV422R
:
129 case WIN_COLOR_DEPTH_YCbCr422RA
:
130 case WIN_COLOR_DEPTH_YUV422RA
:
143 static inline u32
compute_dda_inc(unsigned int in
, unsigned int out
, bool v
,
146 fixed20_12 outf
= dfixed_init(out
);
147 fixed20_12 inf
= dfixed_init(in
);
168 outf
.full
= max_t(u32
, outf
.full
- dfixed_const(1), dfixed_const(1));
169 inf
.full
-= dfixed_const(1);
171 dda_inc
= dfixed_div(inf
, outf
);
172 dda_inc
= min_t(u32
, dda_inc
, dfixed_const(max
));
177 static inline u32
compute_initial_dda(unsigned int in
)
179 fixed20_12 inf
= dfixed_init(in
);
180 return dfixed_frac(inf
);
183 static int tegra_dc_setup_window(struct tegra_dc
*dc
, unsigned int index
,
184 const struct tegra_dc_window
*window
)
186 unsigned h_offset
, v_offset
, h_size
, v_size
, h_dda
, v_dda
, bpp
;
187 unsigned long value
, flags
;
191 * For YUV planar modes, the number of bytes per pixel takes into
192 * account only the luma component and therefore is 1.
194 yuv
= tegra_dc_format_is_yuv(window
->format
, &planar
);
196 bpp
= window
->bits_per_pixel
/ 8;
198 bpp
= planar
? 1 : 2;
200 spin_lock_irqsave(&dc
->lock
, flags
);
202 value
= WINDOW_A_SELECT
<< index
;
203 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_WINDOW_HEADER
);
205 tegra_dc_writel(dc
, window
->format
, DC_WIN_COLOR_DEPTH
);
206 tegra_dc_writel(dc
, window
->swap
, DC_WIN_BYTE_SWAP
);
208 value
= V_POSITION(window
->dst
.y
) | H_POSITION(window
->dst
.x
);
209 tegra_dc_writel(dc
, value
, DC_WIN_POSITION
);
211 value
= V_SIZE(window
->dst
.h
) | H_SIZE(window
->dst
.w
);
212 tegra_dc_writel(dc
, value
, DC_WIN_SIZE
);
214 h_offset
= window
->src
.x
* bpp
;
215 v_offset
= window
->src
.y
;
216 h_size
= window
->src
.w
* bpp
;
217 v_size
= window
->src
.h
;
219 value
= V_PRESCALED_SIZE(v_size
) | H_PRESCALED_SIZE(h_size
);
220 tegra_dc_writel(dc
, value
, DC_WIN_PRESCALED_SIZE
);
223 * For DDA computations the number of bytes per pixel for YUV planar
224 * modes needs to take into account all Y, U and V components.
229 h_dda
= compute_dda_inc(window
->src
.w
, window
->dst
.w
, false, bpp
);
230 v_dda
= compute_dda_inc(window
->src
.h
, window
->dst
.h
, true, bpp
);
232 value
= V_DDA_INC(v_dda
) | H_DDA_INC(h_dda
);
233 tegra_dc_writel(dc
, value
, DC_WIN_DDA_INC
);
235 h_dda
= compute_initial_dda(window
->src
.x
);
236 v_dda
= compute_initial_dda(window
->src
.y
);
238 tegra_dc_writel(dc
, h_dda
, DC_WIN_H_INITIAL_DDA
);
239 tegra_dc_writel(dc
, v_dda
, DC_WIN_V_INITIAL_DDA
);
241 tegra_dc_writel(dc
, 0, DC_WIN_UV_BUF_STRIDE
);
242 tegra_dc_writel(dc
, 0, DC_WIN_BUF_STRIDE
);
244 tegra_dc_writel(dc
, window
->base
[0], DC_WINBUF_START_ADDR
);
247 tegra_dc_writel(dc
, window
->base
[1], DC_WINBUF_START_ADDR_U
);
248 tegra_dc_writel(dc
, window
->base
[2], DC_WINBUF_START_ADDR_V
);
249 value
= window
->stride
[1] << 16 | window
->stride
[0];
250 tegra_dc_writel(dc
, value
, DC_WIN_LINE_STRIDE
);
252 tegra_dc_writel(dc
, window
->stride
[0], DC_WIN_LINE_STRIDE
);
255 if (window
->bottom_up
)
256 v_offset
+= window
->src
.h
- 1;
258 tegra_dc_writel(dc
, h_offset
, DC_WINBUF_ADDR_H_OFFSET
);
259 tegra_dc_writel(dc
, v_offset
, DC_WINBUF_ADDR_V_OFFSET
);
261 if (dc
->soc
->supports_block_linear
) {
262 unsigned long height
= window
->tiling
.value
;
264 switch (window
->tiling
.mode
) {
265 case TEGRA_BO_TILING_MODE_PITCH
:
266 value
= DC_WINBUF_SURFACE_KIND_PITCH
;
269 case TEGRA_BO_TILING_MODE_TILED
:
270 value
= DC_WINBUF_SURFACE_KIND_TILED
;
273 case TEGRA_BO_TILING_MODE_BLOCK
:
274 value
= DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height
) |
275 DC_WINBUF_SURFACE_KIND_BLOCK
;
279 tegra_dc_writel(dc
, value
, DC_WINBUF_SURFACE_KIND
);
281 switch (window
->tiling
.mode
) {
282 case TEGRA_BO_TILING_MODE_PITCH
:
283 value
= DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV
|
284 DC_WIN_BUFFER_ADDR_MODE_LINEAR
;
287 case TEGRA_BO_TILING_MODE_TILED
:
288 value
= DC_WIN_BUFFER_ADDR_MODE_TILE_UV
|
289 DC_WIN_BUFFER_ADDR_MODE_TILE
;
292 case TEGRA_BO_TILING_MODE_BLOCK
:
293 DRM_ERROR("hardware doesn't support block linear mode\n");
294 spin_unlock_irqrestore(&dc
->lock
, flags
);
298 tegra_dc_writel(dc
, value
, DC_WIN_BUFFER_ADDR_MODE
);
304 /* setup default colorspace conversion coefficients */
305 tegra_dc_writel(dc
, 0x00f0, DC_WIN_CSC_YOF
);
306 tegra_dc_writel(dc
, 0x012a, DC_WIN_CSC_KYRGB
);
307 tegra_dc_writel(dc
, 0x0000, DC_WIN_CSC_KUR
);
308 tegra_dc_writel(dc
, 0x0198, DC_WIN_CSC_KVR
);
309 tegra_dc_writel(dc
, 0x039b, DC_WIN_CSC_KUG
);
310 tegra_dc_writel(dc
, 0x032f, DC_WIN_CSC_KVG
);
311 tegra_dc_writel(dc
, 0x0204, DC_WIN_CSC_KUB
);
312 tegra_dc_writel(dc
, 0x0000, DC_WIN_CSC_KVB
);
315 } else if (window
->bits_per_pixel
< 24) {
316 value
|= COLOR_EXPAND
;
319 if (window
->bottom_up
)
320 value
|= V_DIRECTION
;
322 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
325 * Disable blending and assume Window A is the bottom-most window,
326 * Window C is the top-most window and Window B is in the middle.
328 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_NOKEY
);
329 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_1WIN
);
333 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_2WIN_X
);
334 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_2WIN_Y
);
335 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_3WIN_XY
);
339 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_2WIN_X
);
340 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_2WIN_Y
);
341 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_3WIN_XY
);
345 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_2WIN_X
);
346 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_2WIN_Y
);
347 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_3WIN_XY
);
351 tegra_dc_window_commit(dc
, index
);
353 spin_unlock_irqrestore(&dc
->lock
, flags
);
358 static int tegra_window_plane_disable(struct drm_plane
*plane
)
360 struct tegra_dc
*dc
= to_tegra_dc(plane
->crtc
);
361 struct tegra_plane
*p
= to_tegra_plane(plane
);
368 spin_lock_irqsave(&dc
->lock
, flags
);
370 value
= WINDOW_A_SELECT
<< p
->index
;
371 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_WINDOW_HEADER
);
373 value
= tegra_dc_readl(dc
, DC_WIN_WIN_OPTIONS
);
374 value
&= ~WIN_ENABLE
;
375 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
377 tegra_dc_window_commit(dc
, p
->index
);
379 spin_unlock_irqrestore(&dc
->lock
, flags
);
384 static void tegra_plane_destroy(struct drm_plane
*plane
)
386 struct tegra_plane
*p
= to_tegra_plane(plane
);
388 drm_plane_cleanup(plane
);
392 static const u32 tegra_primary_plane_formats
[] = {
398 static int tegra_primary_plane_update(struct drm_plane
*plane
,
399 struct drm_crtc
*crtc
,
400 struct drm_framebuffer
*fb
, int crtc_x
,
401 int crtc_y
, unsigned int crtc_w
,
402 unsigned int crtc_h
, uint32_t src_x
,
403 uint32_t src_y
, uint32_t src_w
,
406 struct tegra_bo
*bo
= tegra_fb_get_plane(fb
, 0);
407 struct tegra_plane
*p
= to_tegra_plane(plane
);
408 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
409 struct tegra_dc_window window
;
412 memset(&window
, 0, sizeof(window
));
413 window
.src
.x
= src_x
>> 16;
414 window
.src
.y
= src_y
>> 16;
415 window
.src
.w
= src_w
>> 16;
416 window
.src
.h
= src_h
>> 16;
417 window
.dst
.x
= crtc_x
;
418 window
.dst
.y
= crtc_y
;
419 window
.dst
.w
= crtc_w
;
420 window
.dst
.h
= crtc_h
;
421 window
.format
= tegra_dc_format(fb
->pixel_format
, &window
.swap
);
422 window
.bits_per_pixel
= fb
->bits_per_pixel
;
423 window
.bottom_up
= tegra_fb_is_bottom_up(fb
);
425 err
= tegra_fb_get_tiling(fb
, &window
.tiling
);
429 window
.base
[0] = bo
->paddr
+ fb
->offsets
[0];
430 window
.stride
[0] = fb
->pitches
[0];
432 err
= tegra_dc_setup_window(dc
, p
->index
, &window
);
439 static void tegra_primary_plane_destroy(struct drm_plane
*plane
)
441 tegra_window_plane_disable(plane
);
442 tegra_plane_destroy(plane
);
445 static const struct drm_plane_funcs tegra_primary_plane_funcs
= {
446 .update_plane
= tegra_primary_plane_update
,
447 .disable_plane
= tegra_window_plane_disable
,
448 .destroy
= tegra_primary_plane_destroy
,
451 static struct drm_plane
*tegra_dc_primary_plane_create(struct drm_device
*drm
,
455 * Ideally this would use drm_crtc_mask(), but that would require the
456 * CRTC to already be in the mode_config's list of CRTCs. However, it
457 * will only be added to that list in the drm_crtc_init_with_planes()
458 * (in tegra_dc_init()), which in turn requires registration of these
459 * planes. So we have ourselves a nice little chicken and egg problem
462 * We work around this by manually creating the mask from the number
463 * of CRTCs that have been registered, and should therefore always be
464 * the same as drm_crtc_index() after registration.
466 unsigned long possible_crtcs
= 1 << drm
->mode_config
.num_crtc
;
467 struct tegra_plane
*plane
;
468 unsigned int num_formats
;
472 plane
= kzalloc(sizeof(*plane
), GFP_KERNEL
);
474 return ERR_PTR(-ENOMEM
);
476 num_formats
= ARRAY_SIZE(tegra_primary_plane_formats
);
477 formats
= tegra_primary_plane_formats
;
479 err
= drm_universal_plane_init(drm
, &plane
->base
, possible_crtcs
,
480 &tegra_primary_plane_funcs
, formats
,
481 num_formats
, DRM_PLANE_TYPE_PRIMARY
);
490 static const u32 tegra_cursor_plane_formats
[] = {
494 static int tegra_cursor_plane_update(struct drm_plane
*plane
,
495 struct drm_crtc
*crtc
,
496 struct drm_framebuffer
*fb
, int crtc_x
,
497 int crtc_y
, unsigned int crtc_w
,
498 unsigned int crtc_h
, uint32_t src_x
,
499 uint32_t src_y
, uint32_t src_w
,
502 struct tegra_bo
*bo
= tegra_fb_get_plane(fb
, 0);
503 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
504 u32 value
= CURSOR_CLIP_DISPLAY
;
506 /* scaling not supported for cursor */
507 if ((src_w
>> 16 != crtc_w
) || (src_h
>> 16 != crtc_h
))
510 /* only square cursors supported */
516 value
|= CURSOR_SIZE_32x32
;
520 value
|= CURSOR_SIZE_64x64
;
524 value
|= CURSOR_SIZE_128x128
;
528 value
|= CURSOR_SIZE_256x256
;
535 value
|= (bo
->paddr
>> 10) & 0x3fffff;
536 tegra_dc_writel(dc
, value
, DC_DISP_CURSOR_START_ADDR
);
538 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
539 value
= (bo
->paddr
>> 32) & 0x3;
540 tegra_dc_writel(dc
, value
, DC_DISP_CURSOR_START_ADDR_HI
);
543 /* enable cursor and set blend mode */
544 value
= tegra_dc_readl(dc
, DC_DISP_DISP_WIN_OPTIONS
);
545 value
|= CURSOR_ENABLE
;
546 tegra_dc_writel(dc
, value
, DC_DISP_DISP_WIN_OPTIONS
);
548 value
= tegra_dc_readl(dc
, DC_DISP_BLEND_CURSOR_CONTROL
);
549 value
&= ~CURSOR_DST_BLEND_MASK
;
550 value
&= ~CURSOR_SRC_BLEND_MASK
;
551 value
|= CURSOR_MODE_NORMAL
;
552 value
|= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC
;
553 value
|= CURSOR_SRC_BLEND_K1_TIMES_SRC
;
554 value
|= CURSOR_ALPHA
;
555 tegra_dc_writel(dc
, value
, DC_DISP_BLEND_CURSOR_CONTROL
);
557 /* position the cursor */
558 value
= (crtc_y
& 0x3fff) << 16 | (crtc_x
& 0x3fff);
559 tegra_dc_writel(dc
, value
, DC_DISP_CURSOR_POSITION
);
562 tegra_dc_cursor_commit(dc
);
568 static int tegra_cursor_plane_disable(struct drm_plane
*plane
)
570 struct tegra_dc
*dc
= to_tegra_dc(plane
->crtc
);
576 value
= tegra_dc_readl(dc
, DC_DISP_DISP_WIN_OPTIONS
);
577 value
&= ~CURSOR_ENABLE
;
578 tegra_dc_writel(dc
, value
, DC_DISP_DISP_WIN_OPTIONS
);
580 tegra_dc_cursor_commit(dc
);
586 static const struct drm_plane_funcs tegra_cursor_plane_funcs
= {
587 .update_plane
= tegra_cursor_plane_update
,
588 .disable_plane
= tegra_cursor_plane_disable
,
589 .destroy
= tegra_plane_destroy
,
592 static struct drm_plane
*tegra_dc_cursor_plane_create(struct drm_device
*drm
,
595 struct tegra_plane
*plane
;
596 unsigned int num_formats
;
600 plane
= kzalloc(sizeof(*plane
), GFP_KERNEL
);
602 return ERR_PTR(-ENOMEM
);
604 num_formats
= ARRAY_SIZE(tegra_cursor_plane_formats
);
605 formats
= tegra_cursor_plane_formats
;
607 err
= drm_universal_plane_init(drm
, &plane
->base
, 1 << dc
->pipe
,
608 &tegra_cursor_plane_funcs
, formats
,
609 num_formats
, DRM_PLANE_TYPE_CURSOR
);
618 static int tegra_overlay_plane_update(struct drm_plane
*plane
,
619 struct drm_crtc
*crtc
,
620 struct drm_framebuffer
*fb
, int crtc_x
,
621 int crtc_y
, unsigned int crtc_w
,
622 unsigned int crtc_h
, uint32_t src_x
,
623 uint32_t src_y
, uint32_t src_w
,
626 struct tegra_plane
*p
= to_tegra_plane(plane
);
627 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
628 struct tegra_dc_window window
;
632 memset(&window
, 0, sizeof(window
));
633 window
.src
.x
= src_x
>> 16;
634 window
.src
.y
= src_y
>> 16;
635 window
.src
.w
= src_w
>> 16;
636 window
.src
.h
= src_h
>> 16;
637 window
.dst
.x
= crtc_x
;
638 window
.dst
.y
= crtc_y
;
639 window
.dst
.w
= crtc_w
;
640 window
.dst
.h
= crtc_h
;
641 window
.format
= tegra_dc_format(fb
->pixel_format
, &window
.swap
);
642 window
.bits_per_pixel
= fb
->bits_per_pixel
;
643 window
.bottom_up
= tegra_fb_is_bottom_up(fb
);
645 err
= tegra_fb_get_tiling(fb
, &window
.tiling
);
649 for (i
= 0; i
< drm_format_num_planes(fb
->pixel_format
); i
++) {
650 struct tegra_bo
*bo
= tegra_fb_get_plane(fb
, i
);
652 window
.base
[i
] = bo
->paddr
+ fb
->offsets
[i
];
655 * Tegra doesn't support different strides for U and V planes
656 * so we display a warning if the user tries to display a
657 * framebuffer with such a configuration.
660 if (fb
->pitches
[i
] != window
.stride
[1])
661 DRM_ERROR("unsupported UV-plane configuration\n");
663 window
.stride
[i
] = fb
->pitches
[i
];
667 return tegra_dc_setup_window(dc
, p
->index
, &window
);
670 static void tegra_overlay_plane_destroy(struct drm_plane
*plane
)
672 tegra_window_plane_disable(plane
);
673 tegra_plane_destroy(plane
);
676 static const struct drm_plane_funcs tegra_overlay_plane_funcs
= {
677 .update_plane
= tegra_overlay_plane_update
,
678 .disable_plane
= tegra_window_plane_disable
,
679 .destroy
= tegra_overlay_plane_destroy
,
682 static const uint32_t tegra_overlay_plane_formats
[] = {
692 static struct drm_plane
*tegra_dc_overlay_plane_create(struct drm_device
*drm
,
696 struct tegra_plane
*plane
;
697 unsigned int num_formats
;
701 plane
= kzalloc(sizeof(*plane
), GFP_KERNEL
);
703 return ERR_PTR(-ENOMEM
);
705 plane
->index
= index
;
707 num_formats
= ARRAY_SIZE(tegra_overlay_plane_formats
);
708 formats
= tegra_overlay_plane_formats
;
710 err
= drm_universal_plane_init(drm
, &plane
->base
, 1 << dc
->pipe
,
711 &tegra_overlay_plane_funcs
, formats
,
712 num_formats
, DRM_PLANE_TYPE_OVERLAY
);
721 static int tegra_dc_add_planes(struct drm_device
*drm
, struct tegra_dc
*dc
)
723 struct drm_plane
*plane
;
726 for (i
= 0; i
< 2; i
++) {
727 plane
= tegra_dc_overlay_plane_create(drm
, dc
, 1 + i
);
729 return PTR_ERR(plane
);
735 static int tegra_dc_set_base(struct tegra_dc
*dc
, int x
, int y
,
736 struct drm_framebuffer
*fb
)
738 struct tegra_bo
*bo
= tegra_fb_get_plane(fb
, 0);
739 unsigned int h_offset
= 0, v_offset
= 0;
740 struct tegra_bo_tiling tiling
;
741 unsigned long value
, flags
;
742 unsigned int format
, swap
;
745 err
= tegra_fb_get_tiling(fb
, &tiling
);
749 spin_lock_irqsave(&dc
->lock
, flags
);
751 tegra_dc_writel(dc
, WINDOW_A_SELECT
, DC_CMD_DISPLAY_WINDOW_HEADER
);
753 value
= fb
->offsets
[0] + y
* fb
->pitches
[0] +
754 x
* fb
->bits_per_pixel
/ 8;
756 tegra_dc_writel(dc
, bo
->paddr
+ value
, DC_WINBUF_START_ADDR
);
757 tegra_dc_writel(dc
, fb
->pitches
[0], DC_WIN_LINE_STRIDE
);
759 format
= tegra_dc_format(fb
->pixel_format
, &swap
);
760 tegra_dc_writel(dc
, format
, DC_WIN_COLOR_DEPTH
);
761 tegra_dc_writel(dc
, swap
, DC_WIN_BYTE_SWAP
);
763 if (dc
->soc
->supports_block_linear
) {
764 unsigned long height
= tiling
.value
;
766 switch (tiling
.mode
) {
767 case TEGRA_BO_TILING_MODE_PITCH
:
768 value
= DC_WINBUF_SURFACE_KIND_PITCH
;
771 case TEGRA_BO_TILING_MODE_TILED
:
772 value
= DC_WINBUF_SURFACE_KIND_TILED
;
775 case TEGRA_BO_TILING_MODE_BLOCK
:
776 value
= DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height
) |
777 DC_WINBUF_SURFACE_KIND_BLOCK
;
781 tegra_dc_writel(dc
, value
, DC_WINBUF_SURFACE_KIND
);
783 switch (tiling
.mode
) {
784 case TEGRA_BO_TILING_MODE_PITCH
:
785 value
= DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV
|
786 DC_WIN_BUFFER_ADDR_MODE_LINEAR
;
789 case TEGRA_BO_TILING_MODE_TILED
:
790 value
= DC_WIN_BUFFER_ADDR_MODE_TILE_UV
|
791 DC_WIN_BUFFER_ADDR_MODE_TILE
;
794 case TEGRA_BO_TILING_MODE_BLOCK
:
795 DRM_ERROR("hardware doesn't support block linear mode\n");
796 spin_unlock_irqrestore(&dc
->lock
, flags
);
800 tegra_dc_writel(dc
, value
, DC_WIN_BUFFER_ADDR_MODE
);
803 /* make sure bottom-up buffers are properly displayed */
804 if (tegra_fb_is_bottom_up(fb
)) {
805 value
= tegra_dc_readl(dc
, DC_WIN_WIN_OPTIONS
);
806 value
|= V_DIRECTION
;
807 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
809 v_offset
+= fb
->height
- 1;
811 value
= tegra_dc_readl(dc
, DC_WIN_WIN_OPTIONS
);
812 value
&= ~V_DIRECTION
;
813 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
816 tegra_dc_writel(dc
, h_offset
, DC_WINBUF_ADDR_H_OFFSET
);
817 tegra_dc_writel(dc
, v_offset
, DC_WINBUF_ADDR_V_OFFSET
);
819 value
= GENERAL_ACT_REQ
| WIN_A_ACT_REQ
;
820 tegra_dc_writel(dc
, value
<< 8, DC_CMD_STATE_CONTROL
);
821 tegra_dc_writel(dc
, value
, DC_CMD_STATE_CONTROL
);
823 spin_unlock_irqrestore(&dc
->lock
, flags
);
828 void tegra_dc_enable_vblank(struct tegra_dc
*dc
)
830 unsigned long value
, flags
;
832 spin_lock_irqsave(&dc
->lock
, flags
);
834 value
= tegra_dc_readl(dc
, DC_CMD_INT_MASK
);
836 tegra_dc_writel(dc
, value
, DC_CMD_INT_MASK
);
838 spin_unlock_irqrestore(&dc
->lock
, flags
);
841 void tegra_dc_disable_vblank(struct tegra_dc
*dc
)
843 unsigned long value
, flags
;
845 spin_lock_irqsave(&dc
->lock
, flags
);
847 value
= tegra_dc_readl(dc
, DC_CMD_INT_MASK
);
848 value
&= ~VBLANK_INT
;
849 tegra_dc_writel(dc
, value
, DC_CMD_INT_MASK
);
851 spin_unlock_irqrestore(&dc
->lock
, flags
);
854 static void tegra_dc_finish_page_flip(struct tegra_dc
*dc
)
856 struct drm_device
*drm
= dc
->base
.dev
;
857 struct drm_crtc
*crtc
= &dc
->base
;
858 unsigned long flags
, base
;
861 spin_lock_irqsave(&drm
->event_lock
, flags
);
864 spin_unlock_irqrestore(&drm
->event_lock
, flags
);
868 bo
= tegra_fb_get_plane(crtc
->primary
->fb
, 0);
870 spin_lock_irqsave(&dc
->lock
, flags
);
872 /* check if new start address has been latched */
873 tegra_dc_writel(dc
, WINDOW_A_SELECT
, DC_CMD_DISPLAY_WINDOW_HEADER
);
874 tegra_dc_writel(dc
, READ_MUX
, DC_CMD_STATE_ACCESS
);
875 base
= tegra_dc_readl(dc
, DC_WINBUF_START_ADDR
);
876 tegra_dc_writel(dc
, 0, DC_CMD_STATE_ACCESS
);
878 spin_unlock_irqrestore(&dc
->lock
, flags
);
880 if (base
== bo
->paddr
+ crtc
->primary
->fb
->offsets
[0]) {
881 drm_crtc_send_vblank_event(crtc
, dc
->event
);
882 drm_crtc_vblank_put(crtc
);
886 spin_unlock_irqrestore(&drm
->event_lock
, flags
);
889 void tegra_dc_cancel_page_flip(struct drm_crtc
*crtc
, struct drm_file
*file
)
891 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
892 struct drm_device
*drm
= crtc
->dev
;
895 spin_lock_irqsave(&drm
->event_lock
, flags
);
897 if (dc
->event
&& dc
->event
->base
.file_priv
== file
) {
898 dc
->event
->base
.destroy(&dc
->event
->base
);
899 drm_crtc_vblank_put(crtc
);
903 spin_unlock_irqrestore(&drm
->event_lock
, flags
);
906 static int tegra_dc_page_flip(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
907 struct drm_pending_vblank_event
*event
, uint32_t page_flip_flags
)
909 unsigned int pipe
= drm_crtc_index(crtc
);
910 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
918 drm_crtc_vblank_get(crtc
);
921 tegra_dc_set_base(dc
, 0, 0, fb
);
922 crtc
->primary
->fb
= fb
;
927 static void tegra_dc_destroy(struct drm_crtc
*crtc
)
929 drm_crtc_cleanup(crtc
);
932 static const struct drm_crtc_funcs tegra_crtc_funcs
= {
933 .page_flip
= tegra_dc_page_flip
,
934 .set_config
= drm_crtc_helper_set_config
,
935 .destroy
= tegra_dc_destroy
,
938 static void tegra_crtc_disable(struct drm_crtc
*crtc
)
940 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
941 struct drm_device
*drm
= crtc
->dev
;
942 struct drm_plane
*plane
;
944 drm_for_each_legacy_plane(plane
, &drm
->mode_config
.plane_list
) {
945 if (plane
->crtc
== crtc
) {
946 tegra_window_plane_disable(plane
);
950 drm_framebuffer_unreference(plane
->fb
);
956 drm_crtc_vblank_off(crtc
);
960 static bool tegra_crtc_mode_fixup(struct drm_crtc
*crtc
,
961 const struct drm_display_mode
*mode
,
962 struct drm_display_mode
*adjusted
)
967 static int tegra_dc_set_timings(struct tegra_dc
*dc
,
968 struct drm_display_mode
*mode
)
970 unsigned int h_ref_to_sync
= 1;
971 unsigned int v_ref_to_sync
= 1;
974 tegra_dc_writel(dc
, 0x0, DC_DISP_DISP_TIMING_OPTIONS
);
976 value
= (v_ref_to_sync
<< 16) | h_ref_to_sync
;
977 tegra_dc_writel(dc
, value
, DC_DISP_REF_TO_SYNC
);
979 value
= ((mode
->vsync_end
- mode
->vsync_start
) << 16) |
980 ((mode
->hsync_end
- mode
->hsync_start
) << 0);
981 tegra_dc_writel(dc
, value
, DC_DISP_SYNC_WIDTH
);
983 value
= ((mode
->vtotal
- mode
->vsync_end
) << 16) |
984 ((mode
->htotal
- mode
->hsync_end
) << 0);
985 tegra_dc_writel(dc
, value
, DC_DISP_BACK_PORCH
);
987 value
= ((mode
->vsync_start
- mode
->vdisplay
) << 16) |
988 ((mode
->hsync_start
- mode
->hdisplay
) << 0);
989 tegra_dc_writel(dc
, value
, DC_DISP_FRONT_PORCH
);
991 value
= (mode
->vdisplay
<< 16) | mode
->hdisplay
;
992 tegra_dc_writel(dc
, value
, DC_DISP_ACTIVE
);
997 static int tegra_crtc_setup_clk(struct drm_crtc
*crtc
,
998 struct drm_display_mode
*mode
)
1000 unsigned long pclk
= mode
->clock
* 1000;
1001 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
1002 struct tegra_output
*output
= NULL
;
1003 struct drm_encoder
*encoder
;
1008 list_for_each_entry(encoder
, &crtc
->dev
->mode_config
.encoder_list
, head
)
1009 if (encoder
->crtc
== crtc
) {
1010 output
= encoder_to_output(encoder
);
1018 * This assumes that the parent clock is pll_d_out0 or pll_d2_out
1019 * respectively, each of which divides the base pll_d by 2.
1021 err
= tegra_output_setup_clock(output
, dc
->clk
, pclk
, &div
);
1023 dev_err(dc
->dev
, "failed to setup clock: %ld\n", err
);
1027 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc
->clk
), div
);
1029 value
= SHIFT_CLK_DIVIDER(div
) | PIXEL_CLK_DIVIDER_PCD1
;
1030 tegra_dc_writel(dc
, value
, DC_DISP_DISP_CLOCK_CONTROL
);
1035 static int tegra_crtc_mode_set(struct drm_crtc
*crtc
,
1036 struct drm_display_mode
*mode
,
1037 struct drm_display_mode
*adjusted
,
1038 int x
, int y
, struct drm_framebuffer
*old_fb
)
1040 struct tegra_bo
*bo
= tegra_fb_get_plane(crtc
->primary
->fb
, 0);
1041 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
1042 struct tegra_dc_window window
;
1046 err
= tegra_crtc_setup_clk(crtc
, mode
);
1048 dev_err(dc
->dev
, "failed to setup clock for CRTC: %d\n", err
);
1052 /* program display mode */
1053 tegra_dc_set_timings(dc
, mode
);
1055 if (dc
->soc
->supports_border_color
)
1056 tegra_dc_writel(dc
, 0, DC_DISP_BORDER_COLOR
);
1058 /* interlacing isn't supported yet, so disable it */
1059 if (dc
->soc
->supports_interlacing
) {
1060 value
= tegra_dc_readl(dc
, DC_DISP_INTERLACE_CONTROL
);
1061 value
&= ~INTERLACE_ENABLE
;
1062 tegra_dc_writel(dc
, value
, DC_DISP_INTERLACE_CONTROL
);
1065 /* setup window parameters */
1066 memset(&window
, 0, sizeof(window
));
1069 window
.src
.w
= mode
->hdisplay
;
1070 window
.src
.h
= mode
->vdisplay
;
1073 window
.dst
.w
= mode
->hdisplay
;
1074 window
.dst
.h
= mode
->vdisplay
;
1075 window
.format
= tegra_dc_format(crtc
->primary
->fb
->pixel_format
,
1077 window
.bits_per_pixel
= crtc
->primary
->fb
->bits_per_pixel
;
1078 window
.stride
[0] = crtc
->primary
->fb
->pitches
[0];
1079 window
.base
[0] = bo
->paddr
;
1081 err
= tegra_dc_setup_window(dc
, 0, &window
);
1083 dev_err(dc
->dev
, "failed to enable root plane\n");
1088 static int tegra_crtc_mode_set_base(struct drm_crtc
*crtc
, int x
, int y
,
1089 struct drm_framebuffer
*old_fb
)
1091 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
1093 return tegra_dc_set_base(dc
, x
, y
, crtc
->primary
->fb
);
1096 static void tegra_crtc_prepare(struct drm_crtc
*crtc
)
1098 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
1099 unsigned int syncpt
;
1100 unsigned long value
;
1102 drm_crtc_vblank_off(crtc
);
1104 /* hardware initialization */
1105 reset_control_deassert(dc
->rst
);
1106 usleep_range(10000, 20000);
1109 syncpt
= SYNCPT_VBLANK1
;
1111 syncpt
= SYNCPT_VBLANK0
;
1113 /* initialize display controller */
1114 tegra_dc_writel(dc
, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL
);
1115 tegra_dc_writel(dc
, 0x100 | syncpt
, DC_CMD_CONT_SYNCPT_VSYNC
);
1117 value
= WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
| WIN_A_OF_INT
;
1118 tegra_dc_writel(dc
, value
, DC_CMD_INT_TYPE
);
1120 value
= WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
|
1121 WIN_A_OF_INT
| WIN_B_OF_INT
| WIN_C_OF_INT
;
1122 tegra_dc_writel(dc
, value
, DC_CMD_INT_POLARITY
);
1124 /* initialize timer */
1125 value
= CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1126 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1127 tegra_dc_writel(dc
, value
, DC_DISP_DISP_MEM_HIGH_PRIORITY
);
1129 value
= CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1130 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1131 tegra_dc_writel(dc
, value
, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER
);
1133 value
= VBLANK_INT
| WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
;
1134 tegra_dc_writel(dc
, value
, DC_CMD_INT_ENABLE
);
1136 value
= WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
;
1137 tegra_dc_writel(dc
, value
, DC_CMD_INT_MASK
);
1140 static void tegra_crtc_commit(struct drm_crtc
*crtc
)
1142 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
1144 drm_crtc_vblank_on(crtc
);
1145 tegra_dc_commit(dc
);
1148 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs
= {
1149 .disable
= tegra_crtc_disable
,
1150 .mode_fixup
= tegra_crtc_mode_fixup
,
1151 .mode_set
= tegra_crtc_mode_set
,
1152 .mode_set_base
= tegra_crtc_mode_set_base
,
1153 .prepare
= tegra_crtc_prepare
,
1154 .commit
= tegra_crtc_commit
,
1157 static irqreturn_t
tegra_dc_irq(int irq
, void *data
)
1159 struct tegra_dc
*dc
= data
;
1160 unsigned long status
;
1162 status
= tegra_dc_readl(dc
, DC_CMD_INT_STATUS
);
1163 tegra_dc_writel(dc
, status
, DC_CMD_INT_STATUS
);
1165 if (status
& FRAME_END_INT
) {
1167 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1171 if (status
& VBLANK_INT
) {
1173 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1175 drm_crtc_handle_vblank(&dc
->base
);
1176 tegra_dc_finish_page_flip(dc
);
1179 if (status
& (WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
)) {
1181 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1188 static int tegra_dc_show_regs(struct seq_file
*s
, void *data
)
1190 struct drm_info_node
*node
= s
->private;
1191 struct tegra_dc
*dc
= node
->info_ent
->data
;
1193 #define DUMP_REG(name) \
1194 seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
1195 tegra_dc_readl(dc, name))
1197 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT
);
1198 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL
);
1199 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR
);
1200 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT
);
1201 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL
);
1202 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR
);
1203 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT
);
1204 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL
);
1205 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR
);
1206 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT
);
1207 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL
);
1208 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR
);
1209 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC
);
1210 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0
);
1211 DUMP_REG(DC_CMD_DISPLAY_COMMAND
);
1212 DUMP_REG(DC_CMD_SIGNAL_RAISE
);
1213 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL
);
1214 DUMP_REG(DC_CMD_INT_STATUS
);
1215 DUMP_REG(DC_CMD_INT_MASK
);
1216 DUMP_REG(DC_CMD_INT_ENABLE
);
1217 DUMP_REG(DC_CMD_INT_TYPE
);
1218 DUMP_REG(DC_CMD_INT_POLARITY
);
1219 DUMP_REG(DC_CMD_SIGNAL_RAISE1
);
1220 DUMP_REG(DC_CMD_SIGNAL_RAISE2
);
1221 DUMP_REG(DC_CMD_SIGNAL_RAISE3
);
1222 DUMP_REG(DC_CMD_STATE_ACCESS
);
1223 DUMP_REG(DC_CMD_STATE_CONTROL
);
1224 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER
);
1225 DUMP_REG(DC_CMD_REG_ACT_CONTROL
);
1226 DUMP_REG(DC_COM_CRC_CONTROL
);
1227 DUMP_REG(DC_COM_CRC_CHECKSUM
);
1228 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1229 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1230 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1231 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1232 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1233 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1234 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1235 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1236 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1237 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1238 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1239 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1240 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1241 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1242 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1243 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1244 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1245 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1246 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1247 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1248 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1249 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1250 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1251 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1252 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1253 DUMP_REG(DC_COM_PIN_MISC_CONTROL
);
1254 DUMP_REG(DC_COM_PIN_PM0_CONTROL
);
1255 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE
);
1256 DUMP_REG(DC_COM_PIN_PM1_CONTROL
);
1257 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE
);
1258 DUMP_REG(DC_COM_SPI_CONTROL
);
1259 DUMP_REG(DC_COM_SPI_START_BYTE
);
1260 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB
);
1261 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD
);
1262 DUMP_REG(DC_COM_HSPI_CS_DC
);
1263 DUMP_REG(DC_COM_SCRATCH_REGISTER_A
);
1264 DUMP_REG(DC_COM_SCRATCH_REGISTER_B
);
1265 DUMP_REG(DC_COM_GPIO_CTRL
);
1266 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER
);
1267 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED
);
1268 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0
);
1269 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1
);
1270 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS
);
1271 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY
);
1272 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER
);
1273 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS
);
1274 DUMP_REG(DC_DISP_REF_TO_SYNC
);
1275 DUMP_REG(DC_DISP_SYNC_WIDTH
);
1276 DUMP_REG(DC_DISP_BACK_PORCH
);
1277 DUMP_REG(DC_DISP_ACTIVE
);
1278 DUMP_REG(DC_DISP_FRONT_PORCH
);
1279 DUMP_REG(DC_DISP_H_PULSE0_CONTROL
);
1280 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A
);
1281 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B
);
1282 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C
);
1283 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D
);
1284 DUMP_REG(DC_DISP_H_PULSE1_CONTROL
);
1285 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A
);
1286 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B
);
1287 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C
);
1288 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D
);
1289 DUMP_REG(DC_DISP_H_PULSE2_CONTROL
);
1290 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A
);
1291 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B
);
1292 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C
);
1293 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D
);
1294 DUMP_REG(DC_DISP_V_PULSE0_CONTROL
);
1295 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A
);
1296 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B
);
1297 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C
);
1298 DUMP_REG(DC_DISP_V_PULSE1_CONTROL
);
1299 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A
);
1300 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B
);
1301 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C
);
1302 DUMP_REG(DC_DISP_V_PULSE2_CONTROL
);
1303 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A
);
1304 DUMP_REG(DC_DISP_V_PULSE3_CONTROL
);
1305 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A
);
1306 DUMP_REG(DC_DISP_M0_CONTROL
);
1307 DUMP_REG(DC_DISP_M1_CONTROL
);
1308 DUMP_REG(DC_DISP_DI_CONTROL
);
1309 DUMP_REG(DC_DISP_PP_CONTROL
);
1310 DUMP_REG(DC_DISP_PP_SELECT_A
);
1311 DUMP_REG(DC_DISP_PP_SELECT_B
);
1312 DUMP_REG(DC_DISP_PP_SELECT_C
);
1313 DUMP_REG(DC_DISP_PP_SELECT_D
);
1314 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL
);
1315 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL
);
1316 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL
);
1317 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS
);
1318 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS
);
1319 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS
);
1320 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS
);
1321 DUMP_REG(DC_DISP_BORDER_COLOR
);
1322 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER
);
1323 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER
);
1324 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER
);
1325 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER
);
1326 DUMP_REG(DC_DISP_CURSOR_FOREGROUND
);
1327 DUMP_REG(DC_DISP_CURSOR_BACKGROUND
);
1328 DUMP_REG(DC_DISP_CURSOR_START_ADDR
);
1329 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS
);
1330 DUMP_REG(DC_DISP_CURSOR_POSITION
);
1331 DUMP_REG(DC_DISP_CURSOR_POSITION_NS
);
1332 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL
);
1333 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A
);
1334 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B
);
1335 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C
);
1336 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D
);
1337 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL
);
1338 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST
);
1339 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST
);
1340 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST
);
1341 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST
);
1342 DUMP_REG(DC_DISP_DAC_CRT_CTRL
);
1343 DUMP_REG(DC_DISP_DISP_MISC_CONTROL
);
1344 DUMP_REG(DC_DISP_SD_CONTROL
);
1345 DUMP_REG(DC_DISP_SD_CSC_COEFF
);
1346 DUMP_REG(DC_DISP_SD_LUT(0));
1347 DUMP_REG(DC_DISP_SD_LUT(1));
1348 DUMP_REG(DC_DISP_SD_LUT(2));
1349 DUMP_REG(DC_DISP_SD_LUT(3));
1350 DUMP_REG(DC_DISP_SD_LUT(4));
1351 DUMP_REG(DC_DISP_SD_LUT(5));
1352 DUMP_REG(DC_DISP_SD_LUT(6));
1353 DUMP_REG(DC_DISP_SD_LUT(7));
1354 DUMP_REG(DC_DISP_SD_LUT(8));
1355 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL
);
1356 DUMP_REG(DC_DISP_DC_PIXEL_COUNT
);
1357 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1358 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1359 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1360 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1361 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1362 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1363 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1364 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1365 DUMP_REG(DC_DISP_SD_BL_TF(0));
1366 DUMP_REG(DC_DISP_SD_BL_TF(1));
1367 DUMP_REG(DC_DISP_SD_BL_TF(2));
1368 DUMP_REG(DC_DISP_SD_BL_TF(3));
1369 DUMP_REG(DC_DISP_SD_BL_CONTROL
);
1370 DUMP_REG(DC_DISP_SD_HW_K_VALUES
);
1371 DUMP_REG(DC_DISP_SD_MAN_K_VALUES
);
1372 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI
);
1373 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL
);
1374 DUMP_REG(DC_WIN_WIN_OPTIONS
);
1375 DUMP_REG(DC_WIN_BYTE_SWAP
);
1376 DUMP_REG(DC_WIN_BUFFER_CONTROL
);
1377 DUMP_REG(DC_WIN_COLOR_DEPTH
);
1378 DUMP_REG(DC_WIN_POSITION
);
1379 DUMP_REG(DC_WIN_SIZE
);
1380 DUMP_REG(DC_WIN_PRESCALED_SIZE
);
1381 DUMP_REG(DC_WIN_H_INITIAL_DDA
);
1382 DUMP_REG(DC_WIN_V_INITIAL_DDA
);
1383 DUMP_REG(DC_WIN_DDA_INC
);
1384 DUMP_REG(DC_WIN_LINE_STRIDE
);
1385 DUMP_REG(DC_WIN_BUF_STRIDE
);
1386 DUMP_REG(DC_WIN_UV_BUF_STRIDE
);
1387 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE
);
1388 DUMP_REG(DC_WIN_DV_CONTROL
);
1389 DUMP_REG(DC_WIN_BLEND_NOKEY
);
1390 DUMP_REG(DC_WIN_BLEND_1WIN
);
1391 DUMP_REG(DC_WIN_BLEND_2WIN_X
);
1392 DUMP_REG(DC_WIN_BLEND_2WIN_Y
);
1393 DUMP_REG(DC_WIN_BLEND_3WIN_XY
);
1394 DUMP_REG(DC_WIN_HP_FETCH_CONTROL
);
1395 DUMP_REG(DC_WINBUF_START_ADDR
);
1396 DUMP_REG(DC_WINBUF_START_ADDR_NS
);
1397 DUMP_REG(DC_WINBUF_START_ADDR_U
);
1398 DUMP_REG(DC_WINBUF_START_ADDR_U_NS
);
1399 DUMP_REG(DC_WINBUF_START_ADDR_V
);
1400 DUMP_REG(DC_WINBUF_START_ADDR_V_NS
);
1401 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET
);
1402 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS
);
1403 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET
);
1404 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS
);
1405 DUMP_REG(DC_WINBUF_UFLOW_STATUS
);
1406 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS
);
1407 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS
);
1408 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS
);
1415 static struct drm_info_list debugfs_files
[] = {
1416 { "regs", tegra_dc_show_regs
, 0, NULL
},
1419 static int tegra_dc_debugfs_init(struct tegra_dc
*dc
, struct drm_minor
*minor
)
1425 name
= kasprintf(GFP_KERNEL
, "dc.%d", dc
->pipe
);
1426 dc
->debugfs
= debugfs_create_dir(name
, minor
->debugfs_root
);
1432 dc
->debugfs_files
= kmemdup(debugfs_files
, sizeof(debugfs_files
),
1434 if (!dc
->debugfs_files
) {
1439 for (i
= 0; i
< ARRAY_SIZE(debugfs_files
); i
++)
1440 dc
->debugfs_files
[i
].data
= dc
;
1442 err
= drm_debugfs_create_files(dc
->debugfs_files
,
1443 ARRAY_SIZE(debugfs_files
),
1444 dc
->debugfs
, minor
);
1453 kfree(dc
->debugfs_files
);
1454 dc
->debugfs_files
= NULL
;
1456 debugfs_remove(dc
->debugfs
);
1462 static int tegra_dc_debugfs_exit(struct tegra_dc
*dc
)
1464 drm_debugfs_remove_files(dc
->debugfs_files
, ARRAY_SIZE(debugfs_files
),
1468 kfree(dc
->debugfs_files
);
1469 dc
->debugfs_files
= NULL
;
1471 debugfs_remove(dc
->debugfs
);
1477 static int tegra_dc_init(struct host1x_client
*client
)
1479 struct drm_device
*drm
= dev_get_drvdata(client
->parent
);
1480 struct tegra_dc
*dc
= host1x_client_to_dc(client
);
1481 struct tegra_drm
*tegra
= drm
->dev_private
;
1482 struct drm_plane
*primary
= NULL
;
1483 struct drm_plane
*cursor
= NULL
;
1486 if (tegra
->domain
) {
1487 err
= iommu_attach_device(tegra
->domain
, dc
->dev
);
1489 dev_err(dc
->dev
, "failed to attach to domain: %d\n",
1494 dc
->domain
= tegra
->domain
;
1497 primary
= tegra_dc_primary_plane_create(drm
, dc
);
1498 if (IS_ERR(primary
)) {
1499 err
= PTR_ERR(primary
);
1503 if (dc
->soc
->supports_cursor
) {
1504 cursor
= tegra_dc_cursor_plane_create(drm
, dc
);
1505 if (IS_ERR(cursor
)) {
1506 err
= PTR_ERR(cursor
);
1511 err
= drm_crtc_init_with_planes(drm
, &dc
->base
, primary
, cursor
,
1516 drm_mode_crtc_set_gamma_size(&dc
->base
, 256);
1517 drm_crtc_helper_add(&dc
->base
, &tegra_crtc_helper_funcs
);
1520 * Keep track of the minimum pitch alignment across all display
1523 if (dc
->soc
->pitch_align
> tegra
->pitch_align
)
1524 tegra
->pitch_align
= dc
->soc
->pitch_align
;
1526 err
= tegra_dc_rgb_init(drm
, dc
);
1527 if (err
< 0 && err
!= -ENODEV
) {
1528 dev_err(dc
->dev
, "failed to initialize RGB output: %d\n", err
);
1532 err
= tegra_dc_add_planes(drm
, dc
);
1536 if (IS_ENABLED(CONFIG_DEBUG_FS
)) {
1537 err
= tegra_dc_debugfs_init(dc
, drm
->primary
);
1539 dev_err(dc
->dev
, "debugfs setup failed: %d\n", err
);
1542 err
= devm_request_irq(dc
->dev
, dc
->irq
, tegra_dc_irq
, 0,
1543 dev_name(dc
->dev
), dc
);
1545 dev_err(dc
->dev
, "failed to request IRQ#%u: %d\n", dc
->irq
,
1554 drm_plane_cleanup(cursor
);
1557 drm_plane_cleanup(primary
);
1559 if (tegra
->domain
) {
1560 iommu_detach_device(tegra
->domain
, dc
->dev
);
1567 static int tegra_dc_exit(struct host1x_client
*client
)
1569 struct tegra_dc
*dc
= host1x_client_to_dc(client
);
1572 devm_free_irq(dc
->dev
, dc
->irq
, dc
);
1574 if (IS_ENABLED(CONFIG_DEBUG_FS
)) {
1575 err
= tegra_dc_debugfs_exit(dc
);
1577 dev_err(dc
->dev
, "debugfs cleanup failed: %d\n", err
);
1580 err
= tegra_dc_rgb_exit(dc
);
1582 dev_err(dc
->dev
, "failed to shutdown RGB output: %d\n", err
);
1587 iommu_detach_device(dc
->domain
, dc
->dev
);
1594 static const struct host1x_client_ops dc_client_ops
= {
1595 .init
= tegra_dc_init
,
1596 .exit
= tegra_dc_exit
,
1599 static const struct tegra_dc_soc_info tegra20_dc_soc_info
= {
1600 .supports_border_color
= true,
1601 .supports_interlacing
= false,
1602 .supports_cursor
= false,
1603 .supports_block_linear
= false,
1605 .has_powergate
= false,
1608 static const struct tegra_dc_soc_info tegra30_dc_soc_info
= {
1609 .supports_border_color
= true,
1610 .supports_interlacing
= false,
1611 .supports_cursor
= false,
1612 .supports_block_linear
= false,
1614 .has_powergate
= false,
1617 static const struct tegra_dc_soc_info tegra114_dc_soc_info
= {
1618 .supports_border_color
= true,
1619 .supports_interlacing
= false,
1620 .supports_cursor
= false,
1621 .supports_block_linear
= false,
1623 .has_powergate
= true,
1626 static const struct tegra_dc_soc_info tegra124_dc_soc_info
= {
1627 .supports_border_color
= false,
1628 .supports_interlacing
= true,
1629 .supports_cursor
= true,
1630 .supports_block_linear
= true,
1632 .has_powergate
= true,
1635 static const struct of_device_id tegra_dc_of_match
[] = {
1637 .compatible
= "nvidia,tegra124-dc",
1638 .data
= &tegra124_dc_soc_info
,
1640 .compatible
= "nvidia,tegra114-dc",
1641 .data
= &tegra114_dc_soc_info
,
1643 .compatible
= "nvidia,tegra30-dc",
1644 .data
= &tegra30_dc_soc_info
,
1646 .compatible
= "nvidia,tegra20-dc",
1647 .data
= &tegra20_dc_soc_info
,
1652 MODULE_DEVICE_TABLE(of
, tegra_dc_of_match
);
1654 static int tegra_dc_parse_dt(struct tegra_dc
*dc
)
1656 struct device_node
*np
;
1660 err
= of_property_read_u32(dc
->dev
->of_node
, "nvidia,head", &value
);
1662 dev_err(dc
->dev
, "missing \"nvidia,head\" property\n");
1665 * If the nvidia,head property isn't present, try to find the
1666 * correct head number by looking up the position of this
1667 * display controller's node within the device tree. Assuming
1668 * that the nodes are ordered properly in the DTS file and
1669 * that the translation into a flattened device tree blob
1670 * preserves that ordering this will actually yield the right
1673 * If those assumptions don't hold, this will still work for
1674 * cases where only a single display controller is used.
1676 for_each_matching_node(np
, tegra_dc_of_match
) {
1677 if (np
== dc
->dev
->of_node
)
1689 static int tegra_dc_probe(struct platform_device
*pdev
)
1691 const struct of_device_id
*id
;
1692 struct resource
*regs
;
1693 struct tegra_dc
*dc
;
1696 dc
= devm_kzalloc(&pdev
->dev
, sizeof(*dc
), GFP_KERNEL
);
1700 id
= of_match_node(tegra_dc_of_match
, pdev
->dev
.of_node
);
1704 spin_lock_init(&dc
->lock
);
1705 INIT_LIST_HEAD(&dc
->list
);
1706 dc
->dev
= &pdev
->dev
;
1709 err
= tegra_dc_parse_dt(dc
);
1713 dc
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1714 if (IS_ERR(dc
->clk
)) {
1715 dev_err(&pdev
->dev
, "failed to get clock\n");
1716 return PTR_ERR(dc
->clk
);
1719 dc
->rst
= devm_reset_control_get(&pdev
->dev
, "dc");
1720 if (IS_ERR(dc
->rst
)) {
1721 dev_err(&pdev
->dev
, "failed to get reset\n");
1722 return PTR_ERR(dc
->rst
);
1725 if (dc
->soc
->has_powergate
) {
1727 dc
->powergate
= TEGRA_POWERGATE_DIS
;
1729 dc
->powergate
= TEGRA_POWERGATE_DISB
;
1731 err
= tegra_powergate_sequence_power_up(dc
->powergate
, dc
->clk
,
1734 dev_err(&pdev
->dev
, "failed to power partition: %d\n",
1739 err
= clk_prepare_enable(dc
->clk
);
1741 dev_err(&pdev
->dev
, "failed to enable clock: %d\n",
1746 err
= reset_control_deassert(dc
->rst
);
1748 dev_err(&pdev
->dev
, "failed to deassert reset: %d\n",
1754 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1755 dc
->regs
= devm_ioremap_resource(&pdev
->dev
, regs
);
1756 if (IS_ERR(dc
->regs
))
1757 return PTR_ERR(dc
->regs
);
1759 dc
->irq
= platform_get_irq(pdev
, 0);
1761 dev_err(&pdev
->dev
, "failed to get IRQ\n");
1765 INIT_LIST_HEAD(&dc
->client
.list
);
1766 dc
->client
.ops
= &dc_client_ops
;
1767 dc
->client
.dev
= &pdev
->dev
;
1769 err
= tegra_dc_rgb_probe(dc
);
1770 if (err
< 0 && err
!= -ENODEV
) {
1771 dev_err(&pdev
->dev
, "failed to probe RGB output: %d\n", err
);
1775 err
= host1x_client_register(&dc
->client
);
1777 dev_err(&pdev
->dev
, "failed to register host1x client: %d\n",
1782 platform_set_drvdata(pdev
, dc
);
1787 static int tegra_dc_remove(struct platform_device
*pdev
)
1789 struct tegra_dc
*dc
= platform_get_drvdata(pdev
);
1792 err
= host1x_client_unregister(&dc
->client
);
1794 dev_err(&pdev
->dev
, "failed to unregister host1x client: %d\n",
1799 err
= tegra_dc_rgb_remove(dc
);
1801 dev_err(&pdev
->dev
, "failed to remove RGB output: %d\n", err
);
1805 reset_control_assert(dc
->rst
);
1807 if (dc
->soc
->has_powergate
)
1808 tegra_powergate_power_off(dc
->powergate
);
1810 clk_disable_unprepare(dc
->clk
);
1815 struct platform_driver tegra_dc_driver
= {
1818 .owner
= THIS_MODULE
,
1819 .of_match_table
= tegra_dc_of_match
,
1821 .probe
= tegra_dc_probe
,
1822 .remove
= tegra_dc_remove
,