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[deliverable/linux.git] / drivers / gpu / drm / tegra / dc.c
1 /*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/iommu.h>
13 #include <linux/reset.h>
14
15 #include <soc/tegra/pmc.h>
16
17 #include "dc.h"
18 #include "drm.h"
19 #include "gem.h"
20
21 #include <drm/drm_plane_helper.h>
22
23 struct tegra_dc_soc_info {
24 bool supports_border_color;
25 bool supports_interlacing;
26 bool supports_cursor;
27 bool supports_block_linear;
28 unsigned int pitch_align;
29 bool has_powergate;
30 };
31
32 struct tegra_plane {
33 struct drm_plane base;
34 unsigned int index;
35 };
36
37 static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
38 {
39 return container_of(plane, struct tegra_plane, base);
40 }
41
42 static void tegra_dc_window_commit(struct tegra_dc *dc, unsigned int index)
43 {
44 u32 value = WIN_A_ACT_REQ << index;
45
46 tegra_dc_writel(dc, value << 8, DC_CMD_STATE_CONTROL);
47 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
48 }
49
50 static void tegra_dc_cursor_commit(struct tegra_dc *dc)
51 {
52 tegra_dc_writel(dc, CURSOR_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
53 tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL);
54 }
55
56 static void tegra_dc_commit(struct tegra_dc *dc)
57 {
58 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
59 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
60 }
61
62 static unsigned int tegra_dc_format(uint32_t format, uint32_t *swap)
63 {
64 /* assume no swapping of fetched data */
65 if (swap)
66 *swap = BYTE_SWAP_NOSWAP;
67
68 switch (format) {
69 case DRM_FORMAT_XBGR8888:
70 return WIN_COLOR_DEPTH_R8G8B8A8;
71
72 case DRM_FORMAT_XRGB8888:
73 return WIN_COLOR_DEPTH_B8G8R8A8;
74
75 case DRM_FORMAT_RGB565:
76 return WIN_COLOR_DEPTH_B5G6R5;
77
78 case DRM_FORMAT_UYVY:
79 return WIN_COLOR_DEPTH_YCbCr422;
80
81 case DRM_FORMAT_YUYV:
82 if (swap)
83 *swap = BYTE_SWAP_SWAP2;
84
85 return WIN_COLOR_DEPTH_YCbCr422;
86
87 case DRM_FORMAT_YUV420:
88 return WIN_COLOR_DEPTH_YCbCr420P;
89
90 case DRM_FORMAT_YUV422:
91 return WIN_COLOR_DEPTH_YCbCr422P;
92
93 default:
94 break;
95 }
96
97 WARN(1, "unsupported pixel format %u, using default\n", format);
98 return WIN_COLOR_DEPTH_B8G8R8A8;
99 }
100
101 static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
102 {
103 switch (format) {
104 case WIN_COLOR_DEPTH_YCbCr422:
105 case WIN_COLOR_DEPTH_YUV422:
106 if (planar)
107 *planar = false;
108
109 return true;
110
111 case WIN_COLOR_DEPTH_YCbCr420P:
112 case WIN_COLOR_DEPTH_YUV420P:
113 case WIN_COLOR_DEPTH_YCbCr422P:
114 case WIN_COLOR_DEPTH_YUV422P:
115 case WIN_COLOR_DEPTH_YCbCr422R:
116 case WIN_COLOR_DEPTH_YUV422R:
117 case WIN_COLOR_DEPTH_YCbCr422RA:
118 case WIN_COLOR_DEPTH_YUV422RA:
119 if (planar)
120 *planar = true;
121
122 return true;
123 }
124
125 return false;
126 }
127
128 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
129 unsigned int bpp)
130 {
131 fixed20_12 outf = dfixed_init(out);
132 fixed20_12 inf = dfixed_init(in);
133 u32 dda_inc;
134 int max;
135
136 if (v)
137 max = 15;
138 else {
139 switch (bpp) {
140 case 2:
141 max = 8;
142 break;
143
144 default:
145 WARN_ON_ONCE(1);
146 /* fallthrough */
147 case 4:
148 max = 4;
149 break;
150 }
151 }
152
153 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
154 inf.full -= dfixed_const(1);
155
156 dda_inc = dfixed_div(inf, outf);
157 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
158
159 return dda_inc;
160 }
161
162 static inline u32 compute_initial_dda(unsigned int in)
163 {
164 fixed20_12 inf = dfixed_init(in);
165 return dfixed_frac(inf);
166 }
167
168 static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
169 const struct tegra_dc_window *window)
170 {
171 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
172 unsigned long value, flags;
173 bool yuv, planar;
174
175 /*
176 * For YUV planar modes, the number of bytes per pixel takes into
177 * account only the luma component and therefore is 1.
178 */
179 yuv = tegra_dc_format_is_yuv(window->format, &planar);
180 if (!yuv)
181 bpp = window->bits_per_pixel / 8;
182 else
183 bpp = planar ? 1 : 2;
184
185 spin_lock_irqsave(&dc->lock, flags);
186
187 value = WINDOW_A_SELECT << index;
188 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
189
190 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
191 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
192
193 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
194 tegra_dc_writel(dc, value, DC_WIN_POSITION);
195
196 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
197 tegra_dc_writel(dc, value, DC_WIN_SIZE);
198
199 h_offset = window->src.x * bpp;
200 v_offset = window->src.y;
201 h_size = window->src.w * bpp;
202 v_size = window->src.h;
203
204 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
205 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
206
207 /*
208 * For DDA computations the number of bytes per pixel for YUV planar
209 * modes needs to take into account all Y, U and V components.
210 */
211 if (yuv && planar)
212 bpp = 2;
213
214 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
215 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
216
217 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
218 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
219
220 h_dda = compute_initial_dda(window->src.x);
221 v_dda = compute_initial_dda(window->src.y);
222
223 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
224 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
225
226 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
227 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
228
229 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
230
231 if (yuv && planar) {
232 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
233 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
234 value = window->stride[1] << 16 | window->stride[0];
235 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
236 } else {
237 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
238 }
239
240 if (window->bottom_up)
241 v_offset += window->src.h - 1;
242
243 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
244 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
245
246 if (dc->soc->supports_block_linear) {
247 unsigned long height = window->tiling.value;
248
249 switch (window->tiling.mode) {
250 case TEGRA_BO_TILING_MODE_PITCH:
251 value = DC_WINBUF_SURFACE_KIND_PITCH;
252 break;
253
254 case TEGRA_BO_TILING_MODE_TILED:
255 value = DC_WINBUF_SURFACE_KIND_TILED;
256 break;
257
258 case TEGRA_BO_TILING_MODE_BLOCK:
259 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
260 DC_WINBUF_SURFACE_KIND_BLOCK;
261 break;
262 }
263
264 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
265 } else {
266 switch (window->tiling.mode) {
267 case TEGRA_BO_TILING_MODE_PITCH:
268 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
269 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
270 break;
271
272 case TEGRA_BO_TILING_MODE_TILED:
273 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
274 DC_WIN_BUFFER_ADDR_MODE_TILE;
275 break;
276
277 case TEGRA_BO_TILING_MODE_BLOCK:
278 DRM_ERROR("hardware doesn't support block linear mode\n");
279 spin_unlock_irqrestore(&dc->lock, flags);
280 return -EINVAL;
281 }
282
283 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
284 }
285
286 value = WIN_ENABLE;
287
288 if (yuv) {
289 /* setup default colorspace conversion coefficients */
290 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
291 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
292 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
293 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
294 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
295 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
296 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
297 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
298
299 value |= CSC_ENABLE;
300 } else if (window->bits_per_pixel < 24) {
301 value |= COLOR_EXPAND;
302 }
303
304 if (window->bottom_up)
305 value |= V_DIRECTION;
306
307 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
308
309 /*
310 * Disable blending and assume Window A is the bottom-most window,
311 * Window C is the top-most window and Window B is in the middle.
312 */
313 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
314 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
315
316 switch (index) {
317 case 0:
318 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
319 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
320 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
321 break;
322
323 case 1:
324 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
325 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
326 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
327 break;
328
329 case 2:
330 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
331 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
332 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
333 break;
334 }
335
336 tegra_dc_window_commit(dc, index);
337
338 spin_unlock_irqrestore(&dc->lock, flags);
339
340 return 0;
341 }
342
343 static int tegra_window_plane_disable(struct drm_plane *plane)
344 {
345 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
346 struct tegra_plane *p = to_tegra_plane(plane);
347 unsigned long flags;
348 u32 value;
349
350 if (!plane->crtc)
351 return 0;
352
353 spin_lock_irqsave(&dc->lock, flags);
354
355 value = WINDOW_A_SELECT << p->index;
356 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
357
358 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
359 value &= ~WIN_ENABLE;
360 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
361
362 tegra_dc_window_commit(dc, p->index);
363
364 spin_unlock_irqrestore(&dc->lock, flags);
365
366 return 0;
367 }
368
369 static void tegra_plane_destroy(struct drm_plane *plane)
370 {
371 struct tegra_plane *p = to_tegra_plane(plane);
372
373 drm_plane_cleanup(plane);
374 kfree(p);
375 }
376
377 static const u32 tegra_primary_plane_formats[] = {
378 DRM_FORMAT_XBGR8888,
379 DRM_FORMAT_XRGB8888,
380 DRM_FORMAT_RGB565,
381 };
382
383 static int tegra_primary_plane_update(struct drm_plane *plane,
384 struct drm_crtc *crtc,
385 struct drm_framebuffer *fb, int crtc_x,
386 int crtc_y, unsigned int crtc_w,
387 unsigned int crtc_h, uint32_t src_x,
388 uint32_t src_y, uint32_t src_w,
389 uint32_t src_h)
390 {
391 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
392 struct tegra_plane *p = to_tegra_plane(plane);
393 struct tegra_dc *dc = to_tegra_dc(crtc);
394 struct tegra_dc_window window;
395 int err;
396
397 memset(&window, 0, sizeof(window));
398 window.src.x = src_x >> 16;
399 window.src.y = src_y >> 16;
400 window.src.w = src_w >> 16;
401 window.src.h = src_h >> 16;
402 window.dst.x = crtc_x;
403 window.dst.y = crtc_y;
404 window.dst.w = crtc_w;
405 window.dst.h = crtc_h;
406 window.format = tegra_dc_format(fb->pixel_format, &window.swap);
407 window.bits_per_pixel = fb->bits_per_pixel;
408 window.bottom_up = tegra_fb_is_bottom_up(fb);
409
410 err = tegra_fb_get_tiling(fb, &window.tiling);
411 if (err < 0)
412 return err;
413
414 window.base[0] = bo->paddr + fb->offsets[0];
415 window.stride[0] = fb->pitches[0];
416
417 err = tegra_dc_setup_window(dc, p->index, &window);
418 if (err < 0)
419 return err;
420
421 return 0;
422 }
423
424 static void tegra_primary_plane_destroy(struct drm_plane *plane)
425 {
426 tegra_window_plane_disable(plane);
427 tegra_plane_destroy(plane);
428 }
429
430 static const struct drm_plane_funcs tegra_primary_plane_funcs = {
431 .update_plane = tegra_primary_plane_update,
432 .disable_plane = tegra_window_plane_disable,
433 .destroy = tegra_primary_plane_destroy,
434 };
435
436 static struct drm_plane *tegra_dc_primary_plane_create(struct drm_device *drm,
437 struct tegra_dc *dc)
438 {
439 /*
440 * Ideally this would use drm_crtc_mask(), but that would require the
441 * CRTC to already be in the mode_config's list of CRTCs. However, it
442 * will only be added to that list in the drm_crtc_init_with_planes()
443 * (in tegra_dc_init()), which in turn requires registration of these
444 * planes. So we have ourselves a nice little chicken and egg problem
445 * here.
446 *
447 * We work around this by manually creating the mask from the number
448 * of CRTCs that have been registered, and should therefore always be
449 * the same as drm_crtc_index() after registration.
450 */
451 unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
452 struct tegra_plane *plane;
453 unsigned int num_formats;
454 const u32 *formats;
455 int err;
456
457 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
458 if (!plane)
459 return ERR_PTR(-ENOMEM);
460
461 num_formats = ARRAY_SIZE(tegra_primary_plane_formats);
462 formats = tegra_primary_plane_formats;
463
464 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
465 &tegra_primary_plane_funcs, formats,
466 num_formats, DRM_PLANE_TYPE_PRIMARY);
467 if (err < 0) {
468 kfree(plane);
469 return ERR_PTR(err);
470 }
471
472 return &plane->base;
473 }
474
475 static const u32 tegra_cursor_plane_formats[] = {
476 DRM_FORMAT_RGBA8888,
477 };
478
479 static int tegra_cursor_plane_update(struct drm_plane *plane,
480 struct drm_crtc *crtc,
481 struct drm_framebuffer *fb, int crtc_x,
482 int crtc_y, unsigned int crtc_w,
483 unsigned int crtc_h, uint32_t src_x,
484 uint32_t src_y, uint32_t src_w,
485 uint32_t src_h)
486 {
487 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
488 struct tegra_dc *dc = to_tegra_dc(crtc);
489 u32 value = CURSOR_CLIP_DISPLAY;
490
491 /* scaling not supported for cursor */
492 if ((src_w >> 16 != crtc_w) || (src_h >> 16 != crtc_h))
493 return -EINVAL;
494
495 /* only square cursors supported */
496 if (src_w != src_h)
497 return -EINVAL;
498
499 switch (crtc_w) {
500 case 32:
501 value |= CURSOR_SIZE_32x32;
502 break;
503
504 case 64:
505 value |= CURSOR_SIZE_64x64;
506 break;
507
508 case 128:
509 value |= CURSOR_SIZE_128x128;
510 break;
511
512 case 256:
513 value |= CURSOR_SIZE_256x256;
514 break;
515
516 default:
517 return -EINVAL;
518 }
519
520 value |= (bo->paddr >> 10) & 0x3fffff;
521 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
522
523 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
524 value = (bo->paddr >> 32) & 0x3;
525 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
526 #endif
527
528 /* enable cursor and set blend mode */
529 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
530 value |= CURSOR_ENABLE;
531 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
532
533 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
534 value &= ~CURSOR_DST_BLEND_MASK;
535 value &= ~CURSOR_SRC_BLEND_MASK;
536 value |= CURSOR_MODE_NORMAL;
537 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
538 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
539 value |= CURSOR_ALPHA;
540 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
541
542 /* position the cursor */
543 value = (crtc_y & 0x3fff) << 16 | (crtc_x & 0x3fff);
544 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
545
546 /* apply changes */
547 tegra_dc_cursor_commit(dc);
548 tegra_dc_commit(dc);
549
550 return 0;
551 }
552
553 static int tegra_cursor_plane_disable(struct drm_plane *plane)
554 {
555 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
556 u32 value;
557
558 if (!plane->crtc)
559 return 0;
560
561 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
562 value &= ~CURSOR_ENABLE;
563 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
564
565 tegra_dc_cursor_commit(dc);
566 tegra_dc_commit(dc);
567
568 return 0;
569 }
570
571 static const struct drm_plane_funcs tegra_cursor_plane_funcs = {
572 .update_plane = tegra_cursor_plane_update,
573 .disable_plane = tegra_cursor_plane_disable,
574 .destroy = tegra_plane_destroy,
575 };
576
577 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
578 struct tegra_dc *dc)
579 {
580 struct tegra_plane *plane;
581 unsigned int num_formats;
582 const u32 *formats;
583 int err;
584
585 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
586 if (!plane)
587 return ERR_PTR(-ENOMEM);
588
589 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
590 formats = tegra_cursor_plane_formats;
591
592 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
593 &tegra_cursor_plane_funcs, formats,
594 num_formats, DRM_PLANE_TYPE_CURSOR);
595 if (err < 0) {
596 kfree(plane);
597 return ERR_PTR(err);
598 }
599
600 return &plane->base;
601 }
602
603 static int tegra_overlay_plane_update(struct drm_plane *plane,
604 struct drm_crtc *crtc,
605 struct drm_framebuffer *fb, int crtc_x,
606 int crtc_y, unsigned int crtc_w,
607 unsigned int crtc_h, uint32_t src_x,
608 uint32_t src_y, uint32_t src_w,
609 uint32_t src_h)
610 {
611 struct tegra_plane *p = to_tegra_plane(plane);
612 struct tegra_dc *dc = to_tegra_dc(crtc);
613 struct tegra_dc_window window;
614 unsigned int i;
615 int err;
616
617 memset(&window, 0, sizeof(window));
618 window.src.x = src_x >> 16;
619 window.src.y = src_y >> 16;
620 window.src.w = src_w >> 16;
621 window.src.h = src_h >> 16;
622 window.dst.x = crtc_x;
623 window.dst.y = crtc_y;
624 window.dst.w = crtc_w;
625 window.dst.h = crtc_h;
626 window.format = tegra_dc_format(fb->pixel_format, &window.swap);
627 window.bits_per_pixel = fb->bits_per_pixel;
628 window.bottom_up = tegra_fb_is_bottom_up(fb);
629
630 err = tegra_fb_get_tiling(fb, &window.tiling);
631 if (err < 0)
632 return err;
633
634 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
635 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
636
637 window.base[i] = bo->paddr + fb->offsets[i];
638
639 /*
640 * Tegra doesn't support different strides for U and V planes
641 * so we display a warning if the user tries to display a
642 * framebuffer with such a configuration.
643 */
644 if (i >= 2) {
645 if (fb->pitches[i] != window.stride[1])
646 DRM_ERROR("unsupported UV-plane configuration\n");
647 } else {
648 window.stride[i] = fb->pitches[i];
649 }
650 }
651
652 return tegra_dc_setup_window(dc, p->index, &window);
653 }
654
655 static void tegra_overlay_plane_destroy(struct drm_plane *plane)
656 {
657 tegra_window_plane_disable(plane);
658 tegra_plane_destroy(plane);
659 }
660
661 static const struct drm_plane_funcs tegra_overlay_plane_funcs = {
662 .update_plane = tegra_overlay_plane_update,
663 .disable_plane = tegra_window_plane_disable,
664 .destroy = tegra_overlay_plane_destroy,
665 };
666
667 static const uint32_t tegra_overlay_plane_formats[] = {
668 DRM_FORMAT_XBGR8888,
669 DRM_FORMAT_XRGB8888,
670 DRM_FORMAT_RGB565,
671 DRM_FORMAT_UYVY,
672 DRM_FORMAT_YUYV,
673 DRM_FORMAT_YUV420,
674 DRM_FORMAT_YUV422,
675 };
676
677 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
678 struct tegra_dc *dc,
679 unsigned int index)
680 {
681 struct tegra_plane *plane;
682 unsigned int num_formats;
683 const u32 *formats;
684 int err;
685
686 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
687 if (!plane)
688 return ERR_PTR(-ENOMEM);
689
690 plane->index = index;
691
692 num_formats = ARRAY_SIZE(tegra_overlay_plane_formats);
693 formats = tegra_overlay_plane_formats;
694
695 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
696 &tegra_overlay_plane_funcs, formats,
697 num_formats, DRM_PLANE_TYPE_OVERLAY);
698 if (err < 0) {
699 kfree(plane);
700 return ERR_PTR(err);
701 }
702
703 return &plane->base;
704 }
705
706 static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
707 {
708 struct drm_plane *plane;
709 unsigned int i;
710
711 for (i = 0; i < 2; i++) {
712 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
713 if (IS_ERR(plane))
714 return PTR_ERR(plane);
715 }
716
717 return 0;
718 }
719
720 static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
721 struct drm_framebuffer *fb)
722 {
723 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
724 unsigned int h_offset = 0, v_offset = 0;
725 struct tegra_bo_tiling tiling;
726 unsigned long value, flags;
727 unsigned int format, swap;
728 int err;
729
730 err = tegra_fb_get_tiling(fb, &tiling);
731 if (err < 0)
732 return err;
733
734 spin_lock_irqsave(&dc->lock, flags);
735
736 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
737
738 value = fb->offsets[0] + y * fb->pitches[0] +
739 x * fb->bits_per_pixel / 8;
740
741 tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR);
742 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
743
744 format = tegra_dc_format(fb->pixel_format, &swap);
745 tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH);
746 tegra_dc_writel(dc, swap, DC_WIN_BYTE_SWAP);
747
748 if (dc->soc->supports_block_linear) {
749 unsigned long height = tiling.value;
750
751 switch (tiling.mode) {
752 case TEGRA_BO_TILING_MODE_PITCH:
753 value = DC_WINBUF_SURFACE_KIND_PITCH;
754 break;
755
756 case TEGRA_BO_TILING_MODE_TILED:
757 value = DC_WINBUF_SURFACE_KIND_TILED;
758 break;
759
760 case TEGRA_BO_TILING_MODE_BLOCK:
761 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
762 DC_WINBUF_SURFACE_KIND_BLOCK;
763 break;
764 }
765
766 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
767 } else {
768 switch (tiling.mode) {
769 case TEGRA_BO_TILING_MODE_PITCH:
770 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
771 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
772 break;
773
774 case TEGRA_BO_TILING_MODE_TILED:
775 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
776 DC_WIN_BUFFER_ADDR_MODE_TILE;
777 break;
778
779 case TEGRA_BO_TILING_MODE_BLOCK:
780 DRM_ERROR("hardware doesn't support block linear mode\n");
781 spin_unlock_irqrestore(&dc->lock, flags);
782 return -EINVAL;
783 }
784
785 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
786 }
787
788 /* make sure bottom-up buffers are properly displayed */
789 if (tegra_fb_is_bottom_up(fb)) {
790 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
791 value |= V_DIRECTION;
792 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
793
794 v_offset += fb->height - 1;
795 } else {
796 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
797 value &= ~V_DIRECTION;
798 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
799 }
800
801 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
802 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
803
804 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
805 tegra_dc_writel(dc, value << 8, DC_CMD_STATE_CONTROL);
806 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
807
808 spin_unlock_irqrestore(&dc->lock, flags);
809
810 return 0;
811 }
812
813 void tegra_dc_enable_vblank(struct tegra_dc *dc)
814 {
815 unsigned long value, flags;
816
817 spin_lock_irqsave(&dc->lock, flags);
818
819 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
820 value |= VBLANK_INT;
821 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
822
823 spin_unlock_irqrestore(&dc->lock, flags);
824 }
825
826 void tegra_dc_disable_vblank(struct tegra_dc *dc)
827 {
828 unsigned long value, flags;
829
830 spin_lock_irqsave(&dc->lock, flags);
831
832 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
833 value &= ~VBLANK_INT;
834 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
835
836 spin_unlock_irqrestore(&dc->lock, flags);
837 }
838
839 static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
840 {
841 struct drm_device *drm = dc->base.dev;
842 struct drm_crtc *crtc = &dc->base;
843 unsigned long flags, base;
844 struct tegra_bo *bo;
845
846 spin_lock_irqsave(&drm->event_lock, flags);
847
848 if (!dc->event) {
849 spin_unlock_irqrestore(&drm->event_lock, flags);
850 return;
851 }
852
853 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
854
855 spin_lock_irqsave(&dc->lock, flags);
856
857 /* check if new start address has been latched */
858 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
859 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
860 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
861 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
862
863 spin_unlock_irqrestore(&dc->lock, flags);
864
865 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
866 drm_crtc_send_vblank_event(crtc, dc->event);
867 drm_crtc_vblank_put(crtc);
868 dc->event = NULL;
869 }
870
871 spin_unlock_irqrestore(&drm->event_lock, flags);
872 }
873
874 void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
875 {
876 struct tegra_dc *dc = to_tegra_dc(crtc);
877 struct drm_device *drm = crtc->dev;
878 unsigned long flags;
879
880 spin_lock_irqsave(&drm->event_lock, flags);
881
882 if (dc->event && dc->event->base.file_priv == file) {
883 dc->event->base.destroy(&dc->event->base);
884 drm_crtc_vblank_put(crtc);
885 dc->event = NULL;
886 }
887
888 spin_unlock_irqrestore(&drm->event_lock, flags);
889 }
890
891 static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
892 struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
893 {
894 unsigned int pipe = drm_crtc_index(crtc);
895 struct tegra_dc *dc = to_tegra_dc(crtc);
896
897 if (dc->event)
898 return -EBUSY;
899
900 if (event) {
901 event->pipe = pipe;
902 dc->event = event;
903 drm_crtc_vblank_get(crtc);
904 }
905
906 tegra_dc_set_base(dc, 0, 0, fb);
907 crtc->primary->fb = fb;
908
909 return 0;
910 }
911
912 static void tegra_dc_destroy(struct drm_crtc *crtc)
913 {
914 drm_crtc_cleanup(crtc);
915 }
916
917 static const struct drm_crtc_funcs tegra_crtc_funcs = {
918 .page_flip = tegra_dc_page_flip,
919 .set_config = drm_crtc_helper_set_config,
920 .destroy = tegra_dc_destroy,
921 };
922
923 static void tegra_crtc_disable(struct drm_crtc *crtc)
924 {
925 struct tegra_dc *dc = to_tegra_dc(crtc);
926 struct drm_device *drm = crtc->dev;
927 struct drm_plane *plane;
928
929 drm_for_each_legacy_plane(plane, &drm->mode_config.plane_list) {
930 if (plane->crtc == crtc) {
931 tegra_window_plane_disable(plane);
932 plane->crtc = NULL;
933
934 if (plane->fb) {
935 drm_framebuffer_unreference(plane->fb);
936 plane->fb = NULL;
937 }
938 }
939 }
940
941 drm_crtc_vblank_off(crtc);
942 tegra_dc_commit(dc);
943 }
944
945 static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
946 const struct drm_display_mode *mode,
947 struct drm_display_mode *adjusted)
948 {
949 return true;
950 }
951
952 static int tegra_dc_set_timings(struct tegra_dc *dc,
953 struct drm_display_mode *mode)
954 {
955 unsigned int h_ref_to_sync = 1;
956 unsigned int v_ref_to_sync = 1;
957 unsigned long value;
958
959 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
960
961 value = (v_ref_to_sync << 16) | h_ref_to_sync;
962 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
963
964 value = ((mode->vsync_end - mode->vsync_start) << 16) |
965 ((mode->hsync_end - mode->hsync_start) << 0);
966 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
967
968 value = ((mode->vtotal - mode->vsync_end) << 16) |
969 ((mode->htotal - mode->hsync_end) << 0);
970 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
971
972 value = ((mode->vsync_start - mode->vdisplay) << 16) |
973 ((mode->hsync_start - mode->hdisplay) << 0);
974 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
975
976 value = (mode->vdisplay << 16) | mode->hdisplay;
977 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
978
979 return 0;
980 }
981
982 static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
983 struct drm_display_mode *mode)
984 {
985 unsigned long pclk = mode->clock * 1000;
986 struct tegra_dc *dc = to_tegra_dc(crtc);
987 struct tegra_output *output = NULL;
988 struct drm_encoder *encoder;
989 unsigned int div;
990 u32 value;
991 long err;
992
993 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
994 if (encoder->crtc == crtc) {
995 output = encoder_to_output(encoder);
996 break;
997 }
998
999 if (!output)
1000 return -ENODEV;
1001
1002 /*
1003 * This assumes that the parent clock is pll_d_out0 or pll_d2_out
1004 * respectively, each of which divides the base pll_d by 2.
1005 */
1006 err = tegra_output_setup_clock(output, dc->clk, pclk, &div);
1007 if (err < 0) {
1008 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
1009 return err;
1010 }
1011
1012 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div);
1013
1014 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
1015 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1016
1017 return 0;
1018 }
1019
1020 static int tegra_crtc_mode_set(struct drm_crtc *crtc,
1021 struct drm_display_mode *mode,
1022 struct drm_display_mode *adjusted,
1023 int x, int y, struct drm_framebuffer *old_fb)
1024 {
1025 struct tegra_bo *bo = tegra_fb_get_plane(crtc->primary->fb, 0);
1026 struct tegra_dc *dc = to_tegra_dc(crtc);
1027 struct tegra_dc_window window;
1028 u32 value;
1029 int err;
1030
1031 err = tegra_crtc_setup_clk(crtc, mode);
1032 if (err) {
1033 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
1034 return err;
1035 }
1036
1037 /* program display mode */
1038 tegra_dc_set_timings(dc, mode);
1039
1040 if (dc->soc->supports_border_color)
1041 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1042
1043 /* interlacing isn't supported yet, so disable it */
1044 if (dc->soc->supports_interlacing) {
1045 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1046 value &= ~INTERLACE_ENABLE;
1047 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1048 }
1049
1050 /* setup window parameters */
1051 memset(&window, 0, sizeof(window));
1052 window.src.x = 0;
1053 window.src.y = 0;
1054 window.src.w = mode->hdisplay;
1055 window.src.h = mode->vdisplay;
1056 window.dst.x = 0;
1057 window.dst.y = 0;
1058 window.dst.w = mode->hdisplay;
1059 window.dst.h = mode->vdisplay;
1060 window.format = tegra_dc_format(crtc->primary->fb->pixel_format,
1061 &window.swap);
1062 window.bits_per_pixel = crtc->primary->fb->bits_per_pixel;
1063 window.stride[0] = crtc->primary->fb->pitches[0];
1064 window.base[0] = bo->paddr;
1065
1066 err = tegra_dc_setup_window(dc, 0, &window);
1067 if (err < 0)
1068 dev_err(dc->dev, "failed to enable root plane\n");
1069
1070 return 0;
1071 }
1072
1073 static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1074 struct drm_framebuffer *old_fb)
1075 {
1076 struct tegra_dc *dc = to_tegra_dc(crtc);
1077
1078 return tegra_dc_set_base(dc, x, y, crtc->primary->fb);
1079 }
1080
1081 static void tegra_crtc_prepare(struct drm_crtc *crtc)
1082 {
1083 struct tegra_dc *dc = to_tegra_dc(crtc);
1084 unsigned int syncpt;
1085 unsigned long value;
1086
1087 drm_crtc_vblank_off(crtc);
1088
1089 /* hardware initialization */
1090 reset_control_deassert(dc->rst);
1091 usleep_range(10000, 20000);
1092
1093 if (dc->pipe)
1094 syncpt = SYNCPT_VBLANK1;
1095 else
1096 syncpt = SYNCPT_VBLANK0;
1097
1098 /* initialize display controller */
1099 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1100 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
1101
1102 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
1103 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1104
1105 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1106 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1107 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1108
1109 /* initialize timer */
1110 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1111 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1112 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1113
1114 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1115 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1116 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1117
1118 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1119 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1120
1121 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1122 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1123 }
1124
1125 static void tegra_crtc_commit(struct drm_crtc *crtc)
1126 {
1127 struct tegra_dc *dc = to_tegra_dc(crtc);
1128
1129 drm_crtc_vblank_on(crtc);
1130 tegra_dc_commit(dc);
1131 }
1132
1133 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1134 .disable = tegra_crtc_disable,
1135 .mode_fixup = tegra_crtc_mode_fixup,
1136 .mode_set = tegra_crtc_mode_set,
1137 .mode_set_base = tegra_crtc_mode_set_base,
1138 .prepare = tegra_crtc_prepare,
1139 .commit = tegra_crtc_commit,
1140 };
1141
1142 static irqreturn_t tegra_dc_irq(int irq, void *data)
1143 {
1144 struct tegra_dc *dc = data;
1145 unsigned long status;
1146
1147 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1148 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1149
1150 if (status & FRAME_END_INT) {
1151 /*
1152 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1153 */
1154 }
1155
1156 if (status & VBLANK_INT) {
1157 /*
1158 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1159 */
1160 drm_crtc_handle_vblank(&dc->base);
1161 tegra_dc_finish_page_flip(dc);
1162 }
1163
1164 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1165 /*
1166 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1167 */
1168 }
1169
1170 return IRQ_HANDLED;
1171 }
1172
1173 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1174 {
1175 struct drm_info_node *node = s->private;
1176 struct tegra_dc *dc = node->info_ent->data;
1177
1178 #define DUMP_REG(name) \
1179 seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
1180 tegra_dc_readl(dc, name))
1181
1182 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1183 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1184 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1185 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1186 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1187 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1188 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1189 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1190 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1191 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1192 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1193 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1194 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1195 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1196 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1197 DUMP_REG(DC_CMD_SIGNAL_RAISE);
1198 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1199 DUMP_REG(DC_CMD_INT_STATUS);
1200 DUMP_REG(DC_CMD_INT_MASK);
1201 DUMP_REG(DC_CMD_INT_ENABLE);
1202 DUMP_REG(DC_CMD_INT_TYPE);
1203 DUMP_REG(DC_CMD_INT_POLARITY);
1204 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1205 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1206 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1207 DUMP_REG(DC_CMD_STATE_ACCESS);
1208 DUMP_REG(DC_CMD_STATE_CONTROL);
1209 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1210 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1211 DUMP_REG(DC_COM_CRC_CONTROL);
1212 DUMP_REG(DC_COM_CRC_CHECKSUM);
1213 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1214 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1215 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1216 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1217 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1218 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1219 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1220 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1221 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1222 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1223 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1224 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1225 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1226 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1227 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1228 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1229 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1230 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1231 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1232 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1233 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1234 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1235 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1236 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1237 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1238 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1239 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1240 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1241 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1242 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1243 DUMP_REG(DC_COM_SPI_CONTROL);
1244 DUMP_REG(DC_COM_SPI_START_BYTE);
1245 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1246 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1247 DUMP_REG(DC_COM_HSPI_CS_DC);
1248 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1249 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1250 DUMP_REG(DC_COM_GPIO_CTRL);
1251 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1252 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1253 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1254 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1255 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1256 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1257 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1258 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1259 DUMP_REG(DC_DISP_REF_TO_SYNC);
1260 DUMP_REG(DC_DISP_SYNC_WIDTH);
1261 DUMP_REG(DC_DISP_BACK_PORCH);
1262 DUMP_REG(DC_DISP_ACTIVE);
1263 DUMP_REG(DC_DISP_FRONT_PORCH);
1264 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1265 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1266 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1267 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1268 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1269 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1270 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1271 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1272 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1273 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1274 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1275 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1276 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1277 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1278 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1279 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1280 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1281 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1282 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1283 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1284 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1285 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1286 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1287 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1288 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1289 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1290 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1291 DUMP_REG(DC_DISP_M0_CONTROL);
1292 DUMP_REG(DC_DISP_M1_CONTROL);
1293 DUMP_REG(DC_DISP_DI_CONTROL);
1294 DUMP_REG(DC_DISP_PP_CONTROL);
1295 DUMP_REG(DC_DISP_PP_SELECT_A);
1296 DUMP_REG(DC_DISP_PP_SELECT_B);
1297 DUMP_REG(DC_DISP_PP_SELECT_C);
1298 DUMP_REG(DC_DISP_PP_SELECT_D);
1299 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1300 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1301 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1302 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1303 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1304 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1305 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1306 DUMP_REG(DC_DISP_BORDER_COLOR);
1307 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1308 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1309 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1310 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1311 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1312 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1313 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1314 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1315 DUMP_REG(DC_DISP_CURSOR_POSITION);
1316 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1317 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1318 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1319 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1320 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1321 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1322 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1323 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1324 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1325 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1326 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1327 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1328 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1329 DUMP_REG(DC_DISP_SD_CONTROL);
1330 DUMP_REG(DC_DISP_SD_CSC_COEFF);
1331 DUMP_REG(DC_DISP_SD_LUT(0));
1332 DUMP_REG(DC_DISP_SD_LUT(1));
1333 DUMP_REG(DC_DISP_SD_LUT(2));
1334 DUMP_REG(DC_DISP_SD_LUT(3));
1335 DUMP_REG(DC_DISP_SD_LUT(4));
1336 DUMP_REG(DC_DISP_SD_LUT(5));
1337 DUMP_REG(DC_DISP_SD_LUT(6));
1338 DUMP_REG(DC_DISP_SD_LUT(7));
1339 DUMP_REG(DC_DISP_SD_LUT(8));
1340 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1341 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1342 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1343 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1344 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1345 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1346 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1347 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1348 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1349 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1350 DUMP_REG(DC_DISP_SD_BL_TF(0));
1351 DUMP_REG(DC_DISP_SD_BL_TF(1));
1352 DUMP_REG(DC_DISP_SD_BL_TF(2));
1353 DUMP_REG(DC_DISP_SD_BL_TF(3));
1354 DUMP_REG(DC_DISP_SD_BL_CONTROL);
1355 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1356 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
1357 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1358 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
1359 DUMP_REG(DC_WIN_WIN_OPTIONS);
1360 DUMP_REG(DC_WIN_BYTE_SWAP);
1361 DUMP_REG(DC_WIN_BUFFER_CONTROL);
1362 DUMP_REG(DC_WIN_COLOR_DEPTH);
1363 DUMP_REG(DC_WIN_POSITION);
1364 DUMP_REG(DC_WIN_SIZE);
1365 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1366 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1367 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1368 DUMP_REG(DC_WIN_DDA_INC);
1369 DUMP_REG(DC_WIN_LINE_STRIDE);
1370 DUMP_REG(DC_WIN_BUF_STRIDE);
1371 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1372 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1373 DUMP_REG(DC_WIN_DV_CONTROL);
1374 DUMP_REG(DC_WIN_BLEND_NOKEY);
1375 DUMP_REG(DC_WIN_BLEND_1WIN);
1376 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1377 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
1378 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
1379 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1380 DUMP_REG(DC_WINBUF_START_ADDR);
1381 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1382 DUMP_REG(DC_WINBUF_START_ADDR_U);
1383 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1384 DUMP_REG(DC_WINBUF_START_ADDR_V);
1385 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1386 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1387 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1388 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1389 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1390 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1391 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1392 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1393 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1394
1395 #undef DUMP_REG
1396
1397 return 0;
1398 }
1399
1400 static struct drm_info_list debugfs_files[] = {
1401 { "regs", tegra_dc_show_regs, 0, NULL },
1402 };
1403
1404 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1405 {
1406 unsigned int i;
1407 char *name;
1408 int err;
1409
1410 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1411 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1412 kfree(name);
1413
1414 if (!dc->debugfs)
1415 return -ENOMEM;
1416
1417 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1418 GFP_KERNEL);
1419 if (!dc->debugfs_files) {
1420 err = -ENOMEM;
1421 goto remove;
1422 }
1423
1424 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1425 dc->debugfs_files[i].data = dc;
1426
1427 err = drm_debugfs_create_files(dc->debugfs_files,
1428 ARRAY_SIZE(debugfs_files),
1429 dc->debugfs, minor);
1430 if (err < 0)
1431 goto free;
1432
1433 dc->minor = minor;
1434
1435 return 0;
1436
1437 free:
1438 kfree(dc->debugfs_files);
1439 dc->debugfs_files = NULL;
1440 remove:
1441 debugfs_remove(dc->debugfs);
1442 dc->debugfs = NULL;
1443
1444 return err;
1445 }
1446
1447 static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1448 {
1449 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1450 dc->minor);
1451 dc->minor = NULL;
1452
1453 kfree(dc->debugfs_files);
1454 dc->debugfs_files = NULL;
1455
1456 debugfs_remove(dc->debugfs);
1457 dc->debugfs = NULL;
1458
1459 return 0;
1460 }
1461
1462 static int tegra_dc_init(struct host1x_client *client)
1463 {
1464 struct drm_device *drm = dev_get_drvdata(client->parent);
1465 struct tegra_dc *dc = host1x_client_to_dc(client);
1466 struct tegra_drm *tegra = drm->dev_private;
1467 struct drm_plane *primary = NULL;
1468 struct drm_plane *cursor = NULL;
1469 int err;
1470
1471 if (tegra->domain) {
1472 err = iommu_attach_device(tegra->domain, dc->dev);
1473 if (err < 0) {
1474 dev_err(dc->dev, "failed to attach to domain: %d\n",
1475 err);
1476 return err;
1477 }
1478
1479 dc->domain = tegra->domain;
1480 }
1481
1482 primary = tegra_dc_primary_plane_create(drm, dc);
1483 if (IS_ERR(primary)) {
1484 err = PTR_ERR(primary);
1485 goto cleanup;
1486 }
1487
1488 if (dc->soc->supports_cursor) {
1489 cursor = tegra_dc_cursor_plane_create(drm, dc);
1490 if (IS_ERR(cursor)) {
1491 err = PTR_ERR(cursor);
1492 goto cleanup;
1493 }
1494 }
1495
1496 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1497 &tegra_crtc_funcs);
1498 if (err < 0)
1499 goto cleanup;
1500
1501 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1502 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1503
1504 /*
1505 * Keep track of the minimum pitch alignment across all display
1506 * controllers.
1507 */
1508 if (dc->soc->pitch_align > tegra->pitch_align)
1509 tegra->pitch_align = dc->soc->pitch_align;
1510
1511 err = tegra_dc_rgb_init(drm, dc);
1512 if (err < 0 && err != -ENODEV) {
1513 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1514 goto cleanup;
1515 }
1516
1517 err = tegra_dc_add_planes(drm, dc);
1518 if (err < 0)
1519 goto cleanup;
1520
1521 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1522 err = tegra_dc_debugfs_init(dc, drm->primary);
1523 if (err < 0)
1524 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1525 }
1526
1527 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1528 dev_name(dc->dev), dc);
1529 if (err < 0) {
1530 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1531 err);
1532 goto cleanup;
1533 }
1534
1535 return 0;
1536
1537 cleanup:
1538 if (cursor)
1539 drm_plane_cleanup(cursor);
1540
1541 if (primary)
1542 drm_plane_cleanup(primary);
1543
1544 if (tegra->domain) {
1545 iommu_detach_device(tegra->domain, dc->dev);
1546 dc->domain = NULL;
1547 }
1548
1549 return err;
1550 }
1551
1552 static int tegra_dc_exit(struct host1x_client *client)
1553 {
1554 struct tegra_dc *dc = host1x_client_to_dc(client);
1555 int err;
1556
1557 devm_free_irq(dc->dev, dc->irq, dc);
1558
1559 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1560 err = tegra_dc_debugfs_exit(dc);
1561 if (err < 0)
1562 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1563 }
1564
1565 err = tegra_dc_rgb_exit(dc);
1566 if (err) {
1567 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1568 return err;
1569 }
1570
1571 if (dc->domain) {
1572 iommu_detach_device(dc->domain, dc->dev);
1573 dc->domain = NULL;
1574 }
1575
1576 return 0;
1577 }
1578
1579 static const struct host1x_client_ops dc_client_ops = {
1580 .init = tegra_dc_init,
1581 .exit = tegra_dc_exit,
1582 };
1583
1584 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1585 .supports_border_color = true,
1586 .supports_interlacing = false,
1587 .supports_cursor = false,
1588 .supports_block_linear = false,
1589 .pitch_align = 8,
1590 .has_powergate = false,
1591 };
1592
1593 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1594 .supports_border_color = true,
1595 .supports_interlacing = false,
1596 .supports_cursor = false,
1597 .supports_block_linear = false,
1598 .pitch_align = 8,
1599 .has_powergate = false,
1600 };
1601
1602 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
1603 .supports_border_color = true,
1604 .supports_interlacing = false,
1605 .supports_cursor = false,
1606 .supports_block_linear = false,
1607 .pitch_align = 64,
1608 .has_powergate = true,
1609 };
1610
1611 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1612 .supports_border_color = false,
1613 .supports_interlacing = true,
1614 .supports_cursor = true,
1615 .supports_block_linear = true,
1616 .pitch_align = 64,
1617 .has_powergate = true,
1618 };
1619
1620 static const struct of_device_id tegra_dc_of_match[] = {
1621 {
1622 .compatible = "nvidia,tegra124-dc",
1623 .data = &tegra124_dc_soc_info,
1624 }, {
1625 .compatible = "nvidia,tegra114-dc",
1626 .data = &tegra114_dc_soc_info,
1627 }, {
1628 .compatible = "nvidia,tegra30-dc",
1629 .data = &tegra30_dc_soc_info,
1630 }, {
1631 .compatible = "nvidia,tegra20-dc",
1632 .data = &tegra20_dc_soc_info,
1633 }, {
1634 /* sentinel */
1635 }
1636 };
1637 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
1638
1639 static int tegra_dc_parse_dt(struct tegra_dc *dc)
1640 {
1641 struct device_node *np;
1642 u32 value = 0;
1643 int err;
1644
1645 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1646 if (err < 0) {
1647 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1648
1649 /*
1650 * If the nvidia,head property isn't present, try to find the
1651 * correct head number by looking up the position of this
1652 * display controller's node within the device tree. Assuming
1653 * that the nodes are ordered properly in the DTS file and
1654 * that the translation into a flattened device tree blob
1655 * preserves that ordering this will actually yield the right
1656 * head number.
1657 *
1658 * If those assumptions don't hold, this will still work for
1659 * cases where only a single display controller is used.
1660 */
1661 for_each_matching_node(np, tegra_dc_of_match) {
1662 if (np == dc->dev->of_node)
1663 break;
1664
1665 value++;
1666 }
1667 }
1668
1669 dc->pipe = value;
1670
1671 return 0;
1672 }
1673
1674 static int tegra_dc_probe(struct platform_device *pdev)
1675 {
1676 const struct of_device_id *id;
1677 struct resource *regs;
1678 struct tegra_dc *dc;
1679 int err;
1680
1681 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1682 if (!dc)
1683 return -ENOMEM;
1684
1685 id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1686 if (!id)
1687 return -ENODEV;
1688
1689 spin_lock_init(&dc->lock);
1690 INIT_LIST_HEAD(&dc->list);
1691 dc->dev = &pdev->dev;
1692 dc->soc = id->data;
1693
1694 err = tegra_dc_parse_dt(dc);
1695 if (err < 0)
1696 return err;
1697
1698 dc->clk = devm_clk_get(&pdev->dev, NULL);
1699 if (IS_ERR(dc->clk)) {
1700 dev_err(&pdev->dev, "failed to get clock\n");
1701 return PTR_ERR(dc->clk);
1702 }
1703
1704 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1705 if (IS_ERR(dc->rst)) {
1706 dev_err(&pdev->dev, "failed to get reset\n");
1707 return PTR_ERR(dc->rst);
1708 }
1709
1710 if (dc->soc->has_powergate) {
1711 if (dc->pipe == 0)
1712 dc->powergate = TEGRA_POWERGATE_DIS;
1713 else
1714 dc->powergate = TEGRA_POWERGATE_DISB;
1715
1716 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
1717 dc->rst);
1718 if (err < 0) {
1719 dev_err(&pdev->dev, "failed to power partition: %d\n",
1720 err);
1721 return err;
1722 }
1723 } else {
1724 err = clk_prepare_enable(dc->clk);
1725 if (err < 0) {
1726 dev_err(&pdev->dev, "failed to enable clock: %d\n",
1727 err);
1728 return err;
1729 }
1730
1731 err = reset_control_deassert(dc->rst);
1732 if (err < 0) {
1733 dev_err(&pdev->dev, "failed to deassert reset: %d\n",
1734 err);
1735 return err;
1736 }
1737 }
1738
1739 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1740 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1741 if (IS_ERR(dc->regs))
1742 return PTR_ERR(dc->regs);
1743
1744 dc->irq = platform_get_irq(pdev, 0);
1745 if (dc->irq < 0) {
1746 dev_err(&pdev->dev, "failed to get IRQ\n");
1747 return -ENXIO;
1748 }
1749
1750 INIT_LIST_HEAD(&dc->client.list);
1751 dc->client.ops = &dc_client_ops;
1752 dc->client.dev = &pdev->dev;
1753
1754 err = tegra_dc_rgb_probe(dc);
1755 if (err < 0 && err != -ENODEV) {
1756 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1757 return err;
1758 }
1759
1760 err = host1x_client_register(&dc->client);
1761 if (err < 0) {
1762 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1763 err);
1764 return err;
1765 }
1766
1767 platform_set_drvdata(pdev, dc);
1768
1769 return 0;
1770 }
1771
1772 static int tegra_dc_remove(struct platform_device *pdev)
1773 {
1774 struct tegra_dc *dc = platform_get_drvdata(pdev);
1775 int err;
1776
1777 err = host1x_client_unregister(&dc->client);
1778 if (err < 0) {
1779 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1780 err);
1781 return err;
1782 }
1783
1784 err = tegra_dc_rgb_remove(dc);
1785 if (err < 0) {
1786 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
1787 return err;
1788 }
1789
1790 reset_control_assert(dc->rst);
1791
1792 if (dc->soc->has_powergate)
1793 tegra_powergate_power_off(dc->powergate);
1794
1795 clk_disable_unprepare(dc->clk);
1796
1797 return 0;
1798 }
1799
1800 struct platform_driver tegra_dc_driver = {
1801 .driver = {
1802 .name = "tegra-dc",
1803 .owner = THIS_MODULE,
1804 .of_match_table = tegra_dc_of_match,
1805 },
1806 .probe = tegra_dc_probe,
1807 .remove = tegra_dc_remove,
1808 };
Linux kernel - Deliverables
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