2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/iommu.h>
13 #include <linux/reset.h>
15 #include <soc/tegra/pmc.h>
21 #include <drm/drm_plane_helper.h>
23 struct tegra_dc_soc_info
{
24 bool supports_border_color
;
25 bool supports_interlacing
;
27 bool supports_block_linear
;
28 unsigned int pitch_align
;
33 struct drm_plane base
;
37 static inline struct tegra_plane
*to_tegra_plane(struct drm_plane
*plane
)
39 return container_of(plane
, struct tegra_plane
, base
);
42 static void tegra_dc_window_commit(struct tegra_dc
*dc
, unsigned int index
)
44 u32 value
= WIN_A_ACT_REQ
<< index
;
46 tegra_dc_writel(dc
, value
<< 8, DC_CMD_STATE_CONTROL
);
47 tegra_dc_writel(dc
, value
, DC_CMD_STATE_CONTROL
);
50 static void tegra_dc_cursor_commit(struct tegra_dc
*dc
)
52 tegra_dc_writel(dc
, CURSOR_ACT_REQ
<< 8, DC_CMD_STATE_CONTROL
);
53 tegra_dc_writel(dc
, CURSOR_ACT_REQ
, DC_CMD_STATE_CONTROL
);
57 * Reads the active copy of a register. This takes the dc->lock spinlock to
58 * prevent races with the VBLANK processing which also needs access to the
59 * active copy of some registers.
61 static u32
tegra_dc_readl_active(struct tegra_dc
*dc
, unsigned long offset
)
66 spin_lock_irqsave(&dc
->lock
, flags
);
68 tegra_dc_writel(dc
, READ_MUX
, DC_CMD_STATE_ACCESS
);
69 value
= tegra_dc_readl(dc
, offset
);
70 tegra_dc_writel(dc
, 0, DC_CMD_STATE_ACCESS
);
72 spin_unlock_irqrestore(&dc
->lock
, flags
);
77 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
78 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
79 * Latching happens mmediately if the display controller is in STOP mode or
80 * on the next frame boundary otherwise.
82 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
83 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
84 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
85 * into the ACTIVE copy, either immediately if the display controller is in
86 * STOP mode, or at the next frame boundary otherwise.
88 void tegra_dc_commit(struct tegra_dc
*dc
)
90 tegra_dc_writel(dc
, GENERAL_ACT_REQ
<< 8, DC_CMD_STATE_CONTROL
);
91 tegra_dc_writel(dc
, GENERAL_ACT_REQ
, DC_CMD_STATE_CONTROL
);
94 static unsigned int tegra_dc_format(uint32_t format
, uint32_t *swap
)
96 /* assume no swapping of fetched data */
98 *swap
= BYTE_SWAP_NOSWAP
;
101 case DRM_FORMAT_XBGR8888
:
102 return WIN_COLOR_DEPTH_R8G8B8A8
;
104 case DRM_FORMAT_XRGB8888
:
105 return WIN_COLOR_DEPTH_B8G8R8A8
;
107 case DRM_FORMAT_RGB565
:
108 return WIN_COLOR_DEPTH_B5G6R5
;
110 case DRM_FORMAT_UYVY
:
111 return WIN_COLOR_DEPTH_YCbCr422
;
113 case DRM_FORMAT_YUYV
:
115 *swap
= BYTE_SWAP_SWAP2
;
117 return WIN_COLOR_DEPTH_YCbCr422
;
119 case DRM_FORMAT_YUV420
:
120 return WIN_COLOR_DEPTH_YCbCr420P
;
122 case DRM_FORMAT_YUV422
:
123 return WIN_COLOR_DEPTH_YCbCr422P
;
129 WARN(1, "unsupported pixel format %u, using default\n", format
);
130 return WIN_COLOR_DEPTH_B8G8R8A8
;
133 static bool tegra_dc_format_is_yuv(unsigned int format
, bool *planar
)
136 case WIN_COLOR_DEPTH_YCbCr422
:
137 case WIN_COLOR_DEPTH_YUV422
:
143 case WIN_COLOR_DEPTH_YCbCr420P
:
144 case WIN_COLOR_DEPTH_YUV420P
:
145 case WIN_COLOR_DEPTH_YCbCr422P
:
146 case WIN_COLOR_DEPTH_YUV422P
:
147 case WIN_COLOR_DEPTH_YCbCr422R
:
148 case WIN_COLOR_DEPTH_YUV422R
:
149 case WIN_COLOR_DEPTH_YCbCr422RA
:
150 case WIN_COLOR_DEPTH_YUV422RA
:
163 static inline u32
compute_dda_inc(unsigned int in
, unsigned int out
, bool v
,
166 fixed20_12 outf
= dfixed_init(out
);
167 fixed20_12 inf
= dfixed_init(in
);
188 outf
.full
= max_t(u32
, outf
.full
- dfixed_const(1), dfixed_const(1));
189 inf
.full
-= dfixed_const(1);
191 dda_inc
= dfixed_div(inf
, outf
);
192 dda_inc
= min_t(u32
, dda_inc
, dfixed_const(max
));
197 static inline u32
compute_initial_dda(unsigned int in
)
199 fixed20_12 inf
= dfixed_init(in
);
200 return dfixed_frac(inf
);
203 static int tegra_dc_setup_window(struct tegra_dc
*dc
, unsigned int index
,
204 const struct tegra_dc_window
*window
)
206 unsigned h_offset
, v_offset
, h_size
, v_size
, h_dda
, v_dda
, bpp
;
207 unsigned long value
, flags
;
211 * For YUV planar modes, the number of bytes per pixel takes into
212 * account only the luma component and therefore is 1.
214 yuv
= tegra_dc_format_is_yuv(window
->format
, &planar
);
216 bpp
= window
->bits_per_pixel
/ 8;
218 bpp
= planar
? 1 : 2;
220 spin_lock_irqsave(&dc
->lock
, flags
);
222 value
= WINDOW_A_SELECT
<< index
;
223 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_WINDOW_HEADER
);
225 tegra_dc_writel(dc
, window
->format
, DC_WIN_COLOR_DEPTH
);
226 tegra_dc_writel(dc
, window
->swap
, DC_WIN_BYTE_SWAP
);
228 value
= V_POSITION(window
->dst
.y
) | H_POSITION(window
->dst
.x
);
229 tegra_dc_writel(dc
, value
, DC_WIN_POSITION
);
231 value
= V_SIZE(window
->dst
.h
) | H_SIZE(window
->dst
.w
);
232 tegra_dc_writel(dc
, value
, DC_WIN_SIZE
);
234 h_offset
= window
->src
.x
* bpp
;
235 v_offset
= window
->src
.y
;
236 h_size
= window
->src
.w
* bpp
;
237 v_size
= window
->src
.h
;
239 value
= V_PRESCALED_SIZE(v_size
) | H_PRESCALED_SIZE(h_size
);
240 tegra_dc_writel(dc
, value
, DC_WIN_PRESCALED_SIZE
);
243 * For DDA computations the number of bytes per pixel for YUV planar
244 * modes needs to take into account all Y, U and V components.
249 h_dda
= compute_dda_inc(window
->src
.w
, window
->dst
.w
, false, bpp
);
250 v_dda
= compute_dda_inc(window
->src
.h
, window
->dst
.h
, true, bpp
);
252 value
= V_DDA_INC(v_dda
) | H_DDA_INC(h_dda
);
253 tegra_dc_writel(dc
, value
, DC_WIN_DDA_INC
);
255 h_dda
= compute_initial_dda(window
->src
.x
);
256 v_dda
= compute_initial_dda(window
->src
.y
);
258 tegra_dc_writel(dc
, h_dda
, DC_WIN_H_INITIAL_DDA
);
259 tegra_dc_writel(dc
, v_dda
, DC_WIN_V_INITIAL_DDA
);
261 tegra_dc_writel(dc
, 0, DC_WIN_UV_BUF_STRIDE
);
262 tegra_dc_writel(dc
, 0, DC_WIN_BUF_STRIDE
);
264 tegra_dc_writel(dc
, window
->base
[0], DC_WINBUF_START_ADDR
);
267 tegra_dc_writel(dc
, window
->base
[1], DC_WINBUF_START_ADDR_U
);
268 tegra_dc_writel(dc
, window
->base
[2], DC_WINBUF_START_ADDR_V
);
269 value
= window
->stride
[1] << 16 | window
->stride
[0];
270 tegra_dc_writel(dc
, value
, DC_WIN_LINE_STRIDE
);
272 tegra_dc_writel(dc
, window
->stride
[0], DC_WIN_LINE_STRIDE
);
275 if (window
->bottom_up
)
276 v_offset
+= window
->src
.h
- 1;
278 tegra_dc_writel(dc
, h_offset
, DC_WINBUF_ADDR_H_OFFSET
);
279 tegra_dc_writel(dc
, v_offset
, DC_WINBUF_ADDR_V_OFFSET
);
281 if (dc
->soc
->supports_block_linear
) {
282 unsigned long height
= window
->tiling
.value
;
284 switch (window
->tiling
.mode
) {
285 case TEGRA_BO_TILING_MODE_PITCH
:
286 value
= DC_WINBUF_SURFACE_KIND_PITCH
;
289 case TEGRA_BO_TILING_MODE_TILED
:
290 value
= DC_WINBUF_SURFACE_KIND_TILED
;
293 case TEGRA_BO_TILING_MODE_BLOCK
:
294 value
= DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height
) |
295 DC_WINBUF_SURFACE_KIND_BLOCK
;
299 tegra_dc_writel(dc
, value
, DC_WINBUF_SURFACE_KIND
);
301 switch (window
->tiling
.mode
) {
302 case TEGRA_BO_TILING_MODE_PITCH
:
303 value
= DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV
|
304 DC_WIN_BUFFER_ADDR_MODE_LINEAR
;
307 case TEGRA_BO_TILING_MODE_TILED
:
308 value
= DC_WIN_BUFFER_ADDR_MODE_TILE_UV
|
309 DC_WIN_BUFFER_ADDR_MODE_TILE
;
312 case TEGRA_BO_TILING_MODE_BLOCK
:
313 DRM_ERROR("hardware doesn't support block linear mode\n");
314 spin_unlock_irqrestore(&dc
->lock
, flags
);
318 tegra_dc_writel(dc
, value
, DC_WIN_BUFFER_ADDR_MODE
);
324 /* setup default colorspace conversion coefficients */
325 tegra_dc_writel(dc
, 0x00f0, DC_WIN_CSC_YOF
);
326 tegra_dc_writel(dc
, 0x012a, DC_WIN_CSC_KYRGB
);
327 tegra_dc_writel(dc
, 0x0000, DC_WIN_CSC_KUR
);
328 tegra_dc_writel(dc
, 0x0198, DC_WIN_CSC_KVR
);
329 tegra_dc_writel(dc
, 0x039b, DC_WIN_CSC_KUG
);
330 tegra_dc_writel(dc
, 0x032f, DC_WIN_CSC_KVG
);
331 tegra_dc_writel(dc
, 0x0204, DC_WIN_CSC_KUB
);
332 tegra_dc_writel(dc
, 0x0000, DC_WIN_CSC_KVB
);
335 } else if (window
->bits_per_pixel
< 24) {
336 value
|= COLOR_EXPAND
;
339 if (window
->bottom_up
)
340 value
|= V_DIRECTION
;
342 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
345 * Disable blending and assume Window A is the bottom-most window,
346 * Window C is the top-most window and Window B is in the middle.
348 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_NOKEY
);
349 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_1WIN
);
353 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_2WIN_X
);
354 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_2WIN_Y
);
355 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_3WIN_XY
);
359 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_2WIN_X
);
360 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_2WIN_Y
);
361 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_3WIN_XY
);
365 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_2WIN_X
);
366 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_2WIN_Y
);
367 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_3WIN_XY
);
371 tegra_dc_window_commit(dc
, index
);
373 spin_unlock_irqrestore(&dc
->lock
, flags
);
378 static int tegra_window_plane_disable(struct drm_plane
*plane
)
380 struct tegra_dc
*dc
= to_tegra_dc(plane
->crtc
);
381 struct tegra_plane
*p
= to_tegra_plane(plane
);
388 spin_lock_irqsave(&dc
->lock
, flags
);
390 value
= WINDOW_A_SELECT
<< p
->index
;
391 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_WINDOW_HEADER
);
393 value
= tegra_dc_readl(dc
, DC_WIN_WIN_OPTIONS
);
394 value
&= ~WIN_ENABLE
;
395 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
397 tegra_dc_window_commit(dc
, p
->index
);
399 spin_unlock_irqrestore(&dc
->lock
, flags
);
404 static void tegra_plane_destroy(struct drm_plane
*plane
)
406 struct tegra_plane
*p
= to_tegra_plane(plane
);
408 drm_plane_cleanup(plane
);
412 static const u32 tegra_primary_plane_formats
[] = {
418 static int tegra_primary_plane_update(struct drm_plane
*plane
,
419 struct drm_crtc
*crtc
,
420 struct drm_framebuffer
*fb
, int crtc_x
,
421 int crtc_y
, unsigned int crtc_w
,
422 unsigned int crtc_h
, uint32_t src_x
,
423 uint32_t src_y
, uint32_t src_w
,
426 struct tegra_bo
*bo
= tegra_fb_get_plane(fb
, 0);
427 struct tegra_plane
*p
= to_tegra_plane(plane
);
428 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
429 struct tegra_dc_window window
;
432 memset(&window
, 0, sizeof(window
));
433 window
.src
.x
= src_x
>> 16;
434 window
.src
.y
= src_y
>> 16;
435 window
.src
.w
= src_w
>> 16;
436 window
.src
.h
= src_h
>> 16;
437 window
.dst
.x
= crtc_x
;
438 window
.dst
.y
= crtc_y
;
439 window
.dst
.w
= crtc_w
;
440 window
.dst
.h
= crtc_h
;
441 window
.format
= tegra_dc_format(fb
->pixel_format
, &window
.swap
);
442 window
.bits_per_pixel
= fb
->bits_per_pixel
;
443 window
.bottom_up
= tegra_fb_is_bottom_up(fb
);
445 err
= tegra_fb_get_tiling(fb
, &window
.tiling
);
449 window
.base
[0] = bo
->paddr
+ fb
->offsets
[0];
450 window
.stride
[0] = fb
->pitches
[0];
452 err
= tegra_dc_setup_window(dc
, p
->index
, &window
);
459 static void tegra_primary_plane_destroy(struct drm_plane
*plane
)
461 tegra_window_plane_disable(plane
);
462 tegra_plane_destroy(plane
);
465 static const struct drm_plane_funcs tegra_primary_plane_funcs
= {
466 .update_plane
= tegra_primary_plane_update
,
467 .disable_plane
= tegra_window_plane_disable
,
468 .destroy
= tegra_primary_plane_destroy
,
471 static struct drm_plane
*tegra_dc_primary_plane_create(struct drm_device
*drm
,
475 * Ideally this would use drm_crtc_mask(), but that would require the
476 * CRTC to already be in the mode_config's list of CRTCs. However, it
477 * will only be added to that list in the drm_crtc_init_with_planes()
478 * (in tegra_dc_init()), which in turn requires registration of these
479 * planes. So we have ourselves a nice little chicken and egg problem
482 * We work around this by manually creating the mask from the number
483 * of CRTCs that have been registered, and should therefore always be
484 * the same as drm_crtc_index() after registration.
486 unsigned long possible_crtcs
= 1 << drm
->mode_config
.num_crtc
;
487 struct tegra_plane
*plane
;
488 unsigned int num_formats
;
492 plane
= kzalloc(sizeof(*plane
), GFP_KERNEL
);
494 return ERR_PTR(-ENOMEM
);
496 num_formats
= ARRAY_SIZE(tegra_primary_plane_formats
);
497 formats
= tegra_primary_plane_formats
;
499 err
= drm_universal_plane_init(drm
, &plane
->base
, possible_crtcs
,
500 &tegra_primary_plane_funcs
, formats
,
501 num_formats
, DRM_PLANE_TYPE_PRIMARY
);
510 static const u32 tegra_cursor_plane_formats
[] = {
514 static int tegra_cursor_plane_update(struct drm_plane
*plane
,
515 struct drm_crtc
*crtc
,
516 struct drm_framebuffer
*fb
, int crtc_x
,
517 int crtc_y
, unsigned int crtc_w
,
518 unsigned int crtc_h
, uint32_t src_x
,
519 uint32_t src_y
, uint32_t src_w
,
522 struct tegra_bo
*bo
= tegra_fb_get_plane(fb
, 0);
523 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
524 u32 value
= CURSOR_CLIP_DISPLAY
;
526 /* scaling not supported for cursor */
527 if ((src_w
>> 16 != crtc_w
) || (src_h
>> 16 != crtc_h
))
530 /* only square cursors supported */
536 value
|= CURSOR_SIZE_32x32
;
540 value
|= CURSOR_SIZE_64x64
;
544 value
|= CURSOR_SIZE_128x128
;
548 value
|= CURSOR_SIZE_256x256
;
555 value
|= (bo
->paddr
>> 10) & 0x3fffff;
556 tegra_dc_writel(dc
, value
, DC_DISP_CURSOR_START_ADDR
);
558 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
559 value
= (bo
->paddr
>> 32) & 0x3;
560 tegra_dc_writel(dc
, value
, DC_DISP_CURSOR_START_ADDR_HI
);
563 /* enable cursor and set blend mode */
564 value
= tegra_dc_readl(dc
, DC_DISP_DISP_WIN_OPTIONS
);
565 value
|= CURSOR_ENABLE
;
566 tegra_dc_writel(dc
, value
, DC_DISP_DISP_WIN_OPTIONS
);
568 value
= tegra_dc_readl(dc
, DC_DISP_BLEND_CURSOR_CONTROL
);
569 value
&= ~CURSOR_DST_BLEND_MASK
;
570 value
&= ~CURSOR_SRC_BLEND_MASK
;
571 value
|= CURSOR_MODE_NORMAL
;
572 value
|= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC
;
573 value
|= CURSOR_SRC_BLEND_K1_TIMES_SRC
;
574 value
|= CURSOR_ALPHA
;
575 tegra_dc_writel(dc
, value
, DC_DISP_BLEND_CURSOR_CONTROL
);
577 /* position the cursor */
578 value
= (crtc_y
& 0x3fff) << 16 | (crtc_x
& 0x3fff);
579 tegra_dc_writel(dc
, value
, DC_DISP_CURSOR_POSITION
);
582 tegra_dc_cursor_commit(dc
);
588 static int tegra_cursor_plane_disable(struct drm_plane
*plane
)
590 struct tegra_dc
*dc
= to_tegra_dc(plane
->crtc
);
596 value
= tegra_dc_readl(dc
, DC_DISP_DISP_WIN_OPTIONS
);
597 value
&= ~CURSOR_ENABLE
;
598 tegra_dc_writel(dc
, value
, DC_DISP_DISP_WIN_OPTIONS
);
600 tegra_dc_cursor_commit(dc
);
606 static const struct drm_plane_funcs tegra_cursor_plane_funcs
= {
607 .update_plane
= tegra_cursor_plane_update
,
608 .disable_plane
= tegra_cursor_plane_disable
,
609 .destroy
= tegra_plane_destroy
,
612 static struct drm_plane
*tegra_dc_cursor_plane_create(struct drm_device
*drm
,
615 struct tegra_plane
*plane
;
616 unsigned int num_formats
;
620 plane
= kzalloc(sizeof(*plane
), GFP_KERNEL
);
622 return ERR_PTR(-ENOMEM
);
624 num_formats
= ARRAY_SIZE(tegra_cursor_plane_formats
);
625 formats
= tegra_cursor_plane_formats
;
627 err
= drm_universal_plane_init(drm
, &plane
->base
, 1 << dc
->pipe
,
628 &tegra_cursor_plane_funcs
, formats
,
629 num_formats
, DRM_PLANE_TYPE_CURSOR
);
638 static int tegra_overlay_plane_update(struct drm_plane
*plane
,
639 struct drm_crtc
*crtc
,
640 struct drm_framebuffer
*fb
, int crtc_x
,
641 int crtc_y
, unsigned int crtc_w
,
642 unsigned int crtc_h
, uint32_t src_x
,
643 uint32_t src_y
, uint32_t src_w
,
646 struct tegra_plane
*p
= to_tegra_plane(plane
);
647 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
648 struct tegra_dc_window window
;
652 memset(&window
, 0, sizeof(window
));
653 window
.src
.x
= src_x
>> 16;
654 window
.src
.y
= src_y
>> 16;
655 window
.src
.w
= src_w
>> 16;
656 window
.src
.h
= src_h
>> 16;
657 window
.dst
.x
= crtc_x
;
658 window
.dst
.y
= crtc_y
;
659 window
.dst
.w
= crtc_w
;
660 window
.dst
.h
= crtc_h
;
661 window
.format
= tegra_dc_format(fb
->pixel_format
, &window
.swap
);
662 window
.bits_per_pixel
= fb
->bits_per_pixel
;
663 window
.bottom_up
= tegra_fb_is_bottom_up(fb
);
665 err
= tegra_fb_get_tiling(fb
, &window
.tiling
);
669 for (i
= 0; i
< drm_format_num_planes(fb
->pixel_format
); i
++) {
670 struct tegra_bo
*bo
= tegra_fb_get_plane(fb
, i
);
672 window
.base
[i
] = bo
->paddr
+ fb
->offsets
[i
];
675 * Tegra doesn't support different strides for U and V planes
676 * so we display a warning if the user tries to display a
677 * framebuffer with such a configuration.
680 if (fb
->pitches
[i
] != window
.stride
[1])
681 DRM_ERROR("unsupported UV-plane configuration\n");
683 window
.stride
[i
] = fb
->pitches
[i
];
687 return tegra_dc_setup_window(dc
, p
->index
, &window
);
690 static void tegra_overlay_plane_destroy(struct drm_plane
*plane
)
692 tegra_window_plane_disable(plane
);
693 tegra_plane_destroy(plane
);
696 static const struct drm_plane_funcs tegra_overlay_plane_funcs
= {
697 .update_plane
= tegra_overlay_plane_update
,
698 .disable_plane
= tegra_window_plane_disable
,
699 .destroy
= tegra_overlay_plane_destroy
,
702 static const uint32_t tegra_overlay_plane_formats
[] = {
712 static struct drm_plane
*tegra_dc_overlay_plane_create(struct drm_device
*drm
,
716 struct tegra_plane
*plane
;
717 unsigned int num_formats
;
721 plane
= kzalloc(sizeof(*plane
), GFP_KERNEL
);
723 return ERR_PTR(-ENOMEM
);
725 plane
->index
= index
;
727 num_formats
= ARRAY_SIZE(tegra_overlay_plane_formats
);
728 formats
= tegra_overlay_plane_formats
;
730 err
= drm_universal_plane_init(drm
, &plane
->base
, 1 << dc
->pipe
,
731 &tegra_overlay_plane_funcs
, formats
,
732 num_formats
, DRM_PLANE_TYPE_OVERLAY
);
741 static int tegra_dc_add_planes(struct drm_device
*drm
, struct tegra_dc
*dc
)
743 struct drm_plane
*plane
;
746 for (i
= 0; i
< 2; i
++) {
747 plane
= tegra_dc_overlay_plane_create(drm
, dc
, 1 + i
);
749 return PTR_ERR(plane
);
755 static int tegra_dc_set_base(struct tegra_dc
*dc
, int x
, int y
,
756 struct drm_framebuffer
*fb
)
758 struct tegra_bo
*bo
= tegra_fb_get_plane(fb
, 0);
759 unsigned int h_offset
= 0, v_offset
= 0;
760 struct tegra_bo_tiling tiling
;
761 unsigned long value
, flags
;
762 unsigned int format
, swap
;
765 err
= tegra_fb_get_tiling(fb
, &tiling
);
769 spin_lock_irqsave(&dc
->lock
, flags
);
771 tegra_dc_writel(dc
, WINDOW_A_SELECT
, DC_CMD_DISPLAY_WINDOW_HEADER
);
773 value
= fb
->offsets
[0] + y
* fb
->pitches
[0] +
774 x
* fb
->bits_per_pixel
/ 8;
776 tegra_dc_writel(dc
, bo
->paddr
+ value
, DC_WINBUF_START_ADDR
);
777 tegra_dc_writel(dc
, fb
->pitches
[0], DC_WIN_LINE_STRIDE
);
779 format
= tegra_dc_format(fb
->pixel_format
, &swap
);
780 tegra_dc_writel(dc
, format
, DC_WIN_COLOR_DEPTH
);
781 tegra_dc_writel(dc
, swap
, DC_WIN_BYTE_SWAP
);
783 if (dc
->soc
->supports_block_linear
) {
784 unsigned long height
= tiling
.value
;
786 switch (tiling
.mode
) {
787 case TEGRA_BO_TILING_MODE_PITCH
:
788 value
= DC_WINBUF_SURFACE_KIND_PITCH
;
791 case TEGRA_BO_TILING_MODE_TILED
:
792 value
= DC_WINBUF_SURFACE_KIND_TILED
;
795 case TEGRA_BO_TILING_MODE_BLOCK
:
796 value
= DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height
) |
797 DC_WINBUF_SURFACE_KIND_BLOCK
;
801 tegra_dc_writel(dc
, value
, DC_WINBUF_SURFACE_KIND
);
803 switch (tiling
.mode
) {
804 case TEGRA_BO_TILING_MODE_PITCH
:
805 value
= DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV
|
806 DC_WIN_BUFFER_ADDR_MODE_LINEAR
;
809 case TEGRA_BO_TILING_MODE_TILED
:
810 value
= DC_WIN_BUFFER_ADDR_MODE_TILE_UV
|
811 DC_WIN_BUFFER_ADDR_MODE_TILE
;
814 case TEGRA_BO_TILING_MODE_BLOCK
:
815 DRM_ERROR("hardware doesn't support block linear mode\n");
816 spin_unlock_irqrestore(&dc
->lock
, flags
);
820 tegra_dc_writel(dc
, value
, DC_WIN_BUFFER_ADDR_MODE
);
823 /* make sure bottom-up buffers are properly displayed */
824 if (tegra_fb_is_bottom_up(fb
)) {
825 value
= tegra_dc_readl(dc
, DC_WIN_WIN_OPTIONS
);
826 value
|= V_DIRECTION
;
827 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
829 v_offset
+= fb
->height
- 1;
831 value
= tegra_dc_readl(dc
, DC_WIN_WIN_OPTIONS
);
832 value
&= ~V_DIRECTION
;
833 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
836 tegra_dc_writel(dc
, h_offset
, DC_WINBUF_ADDR_H_OFFSET
);
837 tegra_dc_writel(dc
, v_offset
, DC_WINBUF_ADDR_V_OFFSET
);
839 value
= GENERAL_ACT_REQ
| WIN_A_ACT_REQ
;
840 tegra_dc_writel(dc
, value
<< 8, DC_CMD_STATE_CONTROL
);
841 tegra_dc_writel(dc
, value
, DC_CMD_STATE_CONTROL
);
843 spin_unlock_irqrestore(&dc
->lock
, flags
);
848 void tegra_dc_enable_vblank(struct tegra_dc
*dc
)
850 unsigned long value
, flags
;
852 spin_lock_irqsave(&dc
->lock
, flags
);
854 value
= tegra_dc_readl(dc
, DC_CMD_INT_MASK
);
856 tegra_dc_writel(dc
, value
, DC_CMD_INT_MASK
);
858 spin_unlock_irqrestore(&dc
->lock
, flags
);
861 void tegra_dc_disable_vblank(struct tegra_dc
*dc
)
863 unsigned long value
, flags
;
865 spin_lock_irqsave(&dc
->lock
, flags
);
867 value
= tegra_dc_readl(dc
, DC_CMD_INT_MASK
);
868 value
&= ~VBLANK_INT
;
869 tegra_dc_writel(dc
, value
, DC_CMD_INT_MASK
);
871 spin_unlock_irqrestore(&dc
->lock
, flags
);
874 static void tegra_dc_finish_page_flip(struct tegra_dc
*dc
)
876 struct drm_device
*drm
= dc
->base
.dev
;
877 struct drm_crtc
*crtc
= &dc
->base
;
878 unsigned long flags
, base
;
881 spin_lock_irqsave(&drm
->event_lock
, flags
);
884 spin_unlock_irqrestore(&drm
->event_lock
, flags
);
888 bo
= tegra_fb_get_plane(crtc
->primary
->fb
, 0);
890 spin_lock(&dc
->lock
);
892 /* check if new start address has been latched */
893 tegra_dc_writel(dc
, WINDOW_A_SELECT
, DC_CMD_DISPLAY_WINDOW_HEADER
);
894 tegra_dc_writel(dc
, READ_MUX
, DC_CMD_STATE_ACCESS
);
895 base
= tegra_dc_readl(dc
, DC_WINBUF_START_ADDR
);
896 tegra_dc_writel(dc
, 0, DC_CMD_STATE_ACCESS
);
898 spin_unlock(&dc
->lock
);
900 if (base
== bo
->paddr
+ crtc
->primary
->fb
->offsets
[0]) {
901 drm_crtc_send_vblank_event(crtc
, dc
->event
);
902 drm_crtc_vblank_put(crtc
);
906 spin_unlock_irqrestore(&drm
->event_lock
, flags
);
909 void tegra_dc_cancel_page_flip(struct drm_crtc
*crtc
, struct drm_file
*file
)
911 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
912 struct drm_device
*drm
= crtc
->dev
;
915 spin_lock_irqsave(&drm
->event_lock
, flags
);
917 if (dc
->event
&& dc
->event
->base
.file_priv
== file
) {
918 dc
->event
->base
.destroy(&dc
->event
->base
);
919 drm_crtc_vblank_put(crtc
);
923 spin_unlock_irqrestore(&drm
->event_lock
, flags
);
926 static int tegra_dc_page_flip(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
927 struct drm_pending_vblank_event
*event
, uint32_t page_flip_flags
)
929 unsigned int pipe
= drm_crtc_index(crtc
);
930 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
938 drm_crtc_vblank_get(crtc
);
941 tegra_dc_set_base(dc
, 0, 0, fb
);
942 crtc
->primary
->fb
= fb
;
947 static void tegra_dc_destroy(struct drm_crtc
*crtc
)
949 drm_crtc_cleanup(crtc
);
952 static const struct drm_crtc_funcs tegra_crtc_funcs
= {
953 .page_flip
= tegra_dc_page_flip
,
954 .set_config
= drm_crtc_helper_set_config
,
955 .destroy
= tegra_dc_destroy
,
958 static void tegra_dc_stop(struct tegra_dc
*dc
)
962 /* stop the display controller */
963 value
= tegra_dc_readl(dc
, DC_CMD_DISPLAY_COMMAND
);
964 value
&= ~DISP_CTRL_MODE_MASK
;
965 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_COMMAND
);
970 static bool tegra_dc_idle(struct tegra_dc
*dc
)
974 value
= tegra_dc_readl_active(dc
, DC_CMD_DISPLAY_COMMAND
);
976 return (value
& DISP_CTRL_MODE_MASK
) == 0;
979 static int tegra_dc_wait_idle(struct tegra_dc
*dc
, unsigned long timeout
)
981 timeout
= jiffies
+ msecs_to_jiffies(timeout
);
983 while (time_before(jiffies
, timeout
)) {
984 if (tegra_dc_idle(dc
))
987 usleep_range(1000, 2000);
990 dev_dbg(dc
->dev
, "timeout waiting for DC to become idle\n");
994 static void tegra_crtc_disable(struct drm_crtc
*crtc
)
996 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
999 if (!tegra_dc_idle(dc
)) {
1003 * Ignore the return value, there isn't anything useful to do
1004 * in case this fails.
1006 tegra_dc_wait_idle(dc
, 100);
1010 * This should really be part of the RGB encoder driver, but clearing
1011 * these bits has the side-effect of stopping the display controller.
1012 * When that happens no VBLANK interrupts will be raised. At the same
1013 * time the encoder is disabled before the display controller, so the
1014 * above code is always going to timeout waiting for the controller
1017 * Given the close coupling between the RGB encoder and the display
1018 * controller doing it here is still kind of okay. None of the other
1019 * encoder drivers require these bits to be cleared.
1021 * XXX: Perhaps given that the display controller is switched off at
1022 * this point anyway maybe clearing these bits isn't even useful for
1026 value
= tegra_dc_readl(dc
, DC_CMD_DISPLAY_POWER_CONTROL
);
1027 value
&= ~(PW0_ENABLE
| PW1_ENABLE
| PW2_ENABLE
| PW3_ENABLE
|
1028 PW4_ENABLE
| PM0_ENABLE
| PM1_ENABLE
);
1029 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_POWER_CONTROL
);
1032 drm_crtc_vblank_off(crtc
);
1033 tegra_dc_commit(dc
);
1036 static bool tegra_crtc_mode_fixup(struct drm_crtc
*crtc
,
1037 const struct drm_display_mode
*mode
,
1038 struct drm_display_mode
*adjusted
)
1043 static int tegra_dc_set_timings(struct tegra_dc
*dc
,
1044 struct drm_display_mode
*mode
)
1046 unsigned int h_ref_to_sync
= 1;
1047 unsigned int v_ref_to_sync
= 1;
1048 unsigned long value
;
1050 tegra_dc_writel(dc
, 0x0, DC_DISP_DISP_TIMING_OPTIONS
);
1052 value
= (v_ref_to_sync
<< 16) | h_ref_to_sync
;
1053 tegra_dc_writel(dc
, value
, DC_DISP_REF_TO_SYNC
);
1055 value
= ((mode
->vsync_end
- mode
->vsync_start
) << 16) |
1056 ((mode
->hsync_end
- mode
->hsync_start
) << 0);
1057 tegra_dc_writel(dc
, value
, DC_DISP_SYNC_WIDTH
);
1059 value
= ((mode
->vtotal
- mode
->vsync_end
) << 16) |
1060 ((mode
->htotal
- mode
->hsync_end
) << 0);
1061 tegra_dc_writel(dc
, value
, DC_DISP_BACK_PORCH
);
1063 value
= ((mode
->vsync_start
- mode
->vdisplay
) << 16) |
1064 ((mode
->hsync_start
- mode
->hdisplay
) << 0);
1065 tegra_dc_writel(dc
, value
, DC_DISP_FRONT_PORCH
);
1067 value
= (mode
->vdisplay
<< 16) | mode
->hdisplay
;
1068 tegra_dc_writel(dc
, value
, DC_DISP_ACTIVE
);
1073 static int tegra_crtc_setup_clk(struct drm_crtc
*crtc
,
1074 struct drm_display_mode
*mode
)
1076 unsigned long pclk
= mode
->clock
* 1000;
1077 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
1078 struct tegra_output
*output
= NULL
;
1079 struct drm_encoder
*encoder
;
1084 list_for_each_entry(encoder
, &crtc
->dev
->mode_config
.encoder_list
, head
)
1085 if (encoder
->crtc
== crtc
) {
1086 output
= encoder_to_output(encoder
);
1094 * The ->setup_clock() callback is optional, but if encoders don't
1095 * implement it they most likely need to do the equivalent within the
1096 * ->mode_fixup() callback.
1098 if (!output
->ops
|| !output
->ops
->setup_clock
)
1102 * This assumes that the parent clock is pll_d_out0 or pll_d2_out
1103 * respectively, each of which divides the base pll_d by 2.
1105 err
= output
->ops
->setup_clock(output
, dc
->clk
, pclk
, &div
);
1107 dev_err(dc
->dev
, "failed to setup clock: %ld\n", err
);
1111 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc
->clk
), div
);
1113 value
= SHIFT_CLK_DIVIDER(div
) | PIXEL_CLK_DIVIDER_PCD1
;
1114 tegra_dc_writel(dc
, value
, DC_DISP_DISP_CLOCK_CONTROL
);
1119 int tegra_dc_setup_clock(struct tegra_dc
*dc
, struct clk
*parent
,
1120 unsigned long pclk
, unsigned int div
)
1125 err
= clk_set_parent(dc
->clk
, parent
);
1127 dev_err(dc
->dev
, "failed to set parent clock: %d\n", err
);
1131 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc
->clk
), div
);
1133 value
= SHIFT_CLK_DIVIDER(div
) | PIXEL_CLK_DIVIDER_PCD1
;
1134 tegra_dc_writel(dc
, value
, DC_DISP_DISP_CLOCK_CONTROL
);
1139 static int tegra_crtc_mode_set(struct drm_crtc
*crtc
,
1140 struct drm_display_mode
*mode
,
1141 struct drm_display_mode
*adjusted
,
1142 int x
, int y
, struct drm_framebuffer
*old_fb
)
1144 struct tegra_bo
*bo
= tegra_fb_get_plane(crtc
->primary
->fb
, 0);
1145 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
1146 struct tegra_dc_window window
;
1150 err
= tegra_crtc_setup_clk(crtc
, mode
);
1152 dev_err(dc
->dev
, "failed to setup clock for CRTC: %d\n", err
);
1156 /* program display mode */
1157 tegra_dc_set_timings(dc
, mode
);
1159 if (dc
->soc
->supports_border_color
)
1160 tegra_dc_writel(dc
, 0, DC_DISP_BORDER_COLOR
);
1162 /* interlacing isn't supported yet, so disable it */
1163 if (dc
->soc
->supports_interlacing
) {
1164 value
= tegra_dc_readl(dc
, DC_DISP_INTERLACE_CONTROL
);
1165 value
&= ~INTERLACE_ENABLE
;
1166 tegra_dc_writel(dc
, value
, DC_DISP_INTERLACE_CONTROL
);
1169 /* setup window parameters */
1170 memset(&window
, 0, sizeof(window
));
1173 window
.src
.w
= mode
->hdisplay
;
1174 window
.src
.h
= mode
->vdisplay
;
1177 window
.dst
.w
= mode
->hdisplay
;
1178 window
.dst
.h
= mode
->vdisplay
;
1179 window
.format
= tegra_dc_format(crtc
->primary
->fb
->pixel_format
,
1181 window
.bits_per_pixel
= crtc
->primary
->fb
->bits_per_pixel
;
1182 window
.stride
[0] = crtc
->primary
->fb
->pitches
[0];
1183 window
.base
[0] = bo
->paddr
;
1185 err
= tegra_dc_setup_window(dc
, 0, &window
);
1187 dev_err(dc
->dev
, "failed to enable root plane\n");
1192 static int tegra_crtc_mode_set_base(struct drm_crtc
*crtc
, int x
, int y
,
1193 struct drm_framebuffer
*old_fb
)
1195 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
1197 return tegra_dc_set_base(dc
, x
, y
, crtc
->primary
->fb
);
1200 static void tegra_crtc_prepare(struct drm_crtc
*crtc
)
1202 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
1203 unsigned int syncpt
;
1204 unsigned long value
;
1206 drm_crtc_vblank_off(crtc
);
1208 /* hardware initialization */
1209 reset_control_deassert(dc
->rst
);
1210 usleep_range(10000, 20000);
1213 syncpt
= SYNCPT_VBLANK1
;
1215 syncpt
= SYNCPT_VBLANK0
;
1217 /* initialize display controller */
1218 tegra_dc_writel(dc
, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL
);
1219 tegra_dc_writel(dc
, 0x100 | syncpt
, DC_CMD_CONT_SYNCPT_VSYNC
);
1221 value
= WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
| WIN_A_OF_INT
;
1222 tegra_dc_writel(dc
, value
, DC_CMD_INT_TYPE
);
1224 value
= WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
|
1225 WIN_A_OF_INT
| WIN_B_OF_INT
| WIN_C_OF_INT
;
1226 tegra_dc_writel(dc
, value
, DC_CMD_INT_POLARITY
);
1228 /* initialize timer */
1229 value
= CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1230 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1231 tegra_dc_writel(dc
, value
, DC_DISP_DISP_MEM_HIGH_PRIORITY
);
1233 value
= CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1234 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1235 tegra_dc_writel(dc
, value
, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER
);
1237 value
= VBLANK_INT
| WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
;
1238 tegra_dc_writel(dc
, value
, DC_CMD_INT_ENABLE
);
1240 value
= WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
;
1241 tegra_dc_writel(dc
, value
, DC_CMD_INT_MASK
);
1244 static void tegra_crtc_commit(struct drm_crtc
*crtc
)
1246 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
1248 drm_crtc_vblank_on(crtc
);
1249 tegra_dc_commit(dc
);
1252 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs
= {
1253 .disable
= tegra_crtc_disable
,
1254 .mode_fixup
= tegra_crtc_mode_fixup
,
1255 .mode_set
= tegra_crtc_mode_set
,
1256 .mode_set_base
= tegra_crtc_mode_set_base
,
1257 .prepare
= tegra_crtc_prepare
,
1258 .commit
= tegra_crtc_commit
,
1261 static irqreturn_t
tegra_dc_irq(int irq
, void *data
)
1263 struct tegra_dc
*dc
= data
;
1264 unsigned long status
;
1266 status
= tegra_dc_readl(dc
, DC_CMD_INT_STATUS
);
1267 tegra_dc_writel(dc
, status
, DC_CMD_INT_STATUS
);
1269 if (status
& FRAME_END_INT
) {
1271 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1275 if (status
& VBLANK_INT
) {
1277 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1279 drm_crtc_handle_vblank(&dc
->base
);
1280 tegra_dc_finish_page_flip(dc
);
1283 if (status
& (WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
)) {
1285 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1292 static int tegra_dc_show_regs(struct seq_file
*s
, void *data
)
1294 struct drm_info_node
*node
= s
->private;
1295 struct tegra_dc
*dc
= node
->info_ent
->data
;
1297 #define DUMP_REG(name) \
1298 seq_printf(s, "%-40s %#05x %08x\n", #name, name, \
1299 tegra_dc_readl(dc, name))
1301 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT
);
1302 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL
);
1303 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR
);
1304 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT
);
1305 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL
);
1306 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR
);
1307 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT
);
1308 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL
);
1309 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR
);
1310 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT
);
1311 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL
);
1312 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR
);
1313 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC
);
1314 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0
);
1315 DUMP_REG(DC_CMD_DISPLAY_COMMAND
);
1316 DUMP_REG(DC_CMD_SIGNAL_RAISE
);
1317 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL
);
1318 DUMP_REG(DC_CMD_INT_STATUS
);
1319 DUMP_REG(DC_CMD_INT_MASK
);
1320 DUMP_REG(DC_CMD_INT_ENABLE
);
1321 DUMP_REG(DC_CMD_INT_TYPE
);
1322 DUMP_REG(DC_CMD_INT_POLARITY
);
1323 DUMP_REG(DC_CMD_SIGNAL_RAISE1
);
1324 DUMP_REG(DC_CMD_SIGNAL_RAISE2
);
1325 DUMP_REG(DC_CMD_SIGNAL_RAISE3
);
1326 DUMP_REG(DC_CMD_STATE_ACCESS
);
1327 DUMP_REG(DC_CMD_STATE_CONTROL
);
1328 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER
);
1329 DUMP_REG(DC_CMD_REG_ACT_CONTROL
);
1330 DUMP_REG(DC_COM_CRC_CONTROL
);
1331 DUMP_REG(DC_COM_CRC_CHECKSUM
);
1332 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1333 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1334 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1335 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1336 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1337 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1338 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1339 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1340 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1341 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1342 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1343 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1344 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1345 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1346 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1347 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1348 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1349 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1350 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1351 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1352 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1353 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1354 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1355 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1356 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1357 DUMP_REG(DC_COM_PIN_MISC_CONTROL
);
1358 DUMP_REG(DC_COM_PIN_PM0_CONTROL
);
1359 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE
);
1360 DUMP_REG(DC_COM_PIN_PM1_CONTROL
);
1361 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE
);
1362 DUMP_REG(DC_COM_SPI_CONTROL
);
1363 DUMP_REG(DC_COM_SPI_START_BYTE
);
1364 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB
);
1365 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD
);
1366 DUMP_REG(DC_COM_HSPI_CS_DC
);
1367 DUMP_REG(DC_COM_SCRATCH_REGISTER_A
);
1368 DUMP_REG(DC_COM_SCRATCH_REGISTER_B
);
1369 DUMP_REG(DC_COM_GPIO_CTRL
);
1370 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER
);
1371 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED
);
1372 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0
);
1373 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1
);
1374 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS
);
1375 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY
);
1376 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER
);
1377 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS
);
1378 DUMP_REG(DC_DISP_REF_TO_SYNC
);
1379 DUMP_REG(DC_DISP_SYNC_WIDTH
);
1380 DUMP_REG(DC_DISP_BACK_PORCH
);
1381 DUMP_REG(DC_DISP_ACTIVE
);
1382 DUMP_REG(DC_DISP_FRONT_PORCH
);
1383 DUMP_REG(DC_DISP_H_PULSE0_CONTROL
);
1384 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A
);
1385 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B
);
1386 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C
);
1387 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D
);
1388 DUMP_REG(DC_DISP_H_PULSE1_CONTROL
);
1389 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A
);
1390 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B
);
1391 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C
);
1392 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D
);
1393 DUMP_REG(DC_DISP_H_PULSE2_CONTROL
);
1394 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A
);
1395 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B
);
1396 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C
);
1397 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D
);
1398 DUMP_REG(DC_DISP_V_PULSE0_CONTROL
);
1399 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A
);
1400 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B
);
1401 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C
);
1402 DUMP_REG(DC_DISP_V_PULSE1_CONTROL
);
1403 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A
);
1404 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B
);
1405 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C
);
1406 DUMP_REG(DC_DISP_V_PULSE2_CONTROL
);
1407 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A
);
1408 DUMP_REG(DC_DISP_V_PULSE3_CONTROL
);
1409 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A
);
1410 DUMP_REG(DC_DISP_M0_CONTROL
);
1411 DUMP_REG(DC_DISP_M1_CONTROL
);
1412 DUMP_REG(DC_DISP_DI_CONTROL
);
1413 DUMP_REG(DC_DISP_PP_CONTROL
);
1414 DUMP_REG(DC_DISP_PP_SELECT_A
);
1415 DUMP_REG(DC_DISP_PP_SELECT_B
);
1416 DUMP_REG(DC_DISP_PP_SELECT_C
);
1417 DUMP_REG(DC_DISP_PP_SELECT_D
);
1418 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL
);
1419 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL
);
1420 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL
);
1421 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS
);
1422 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS
);
1423 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS
);
1424 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS
);
1425 DUMP_REG(DC_DISP_BORDER_COLOR
);
1426 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER
);
1427 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER
);
1428 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER
);
1429 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER
);
1430 DUMP_REG(DC_DISP_CURSOR_FOREGROUND
);
1431 DUMP_REG(DC_DISP_CURSOR_BACKGROUND
);
1432 DUMP_REG(DC_DISP_CURSOR_START_ADDR
);
1433 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS
);
1434 DUMP_REG(DC_DISP_CURSOR_POSITION
);
1435 DUMP_REG(DC_DISP_CURSOR_POSITION_NS
);
1436 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL
);
1437 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A
);
1438 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B
);
1439 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C
);
1440 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D
);
1441 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL
);
1442 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST
);
1443 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST
);
1444 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST
);
1445 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST
);
1446 DUMP_REG(DC_DISP_DAC_CRT_CTRL
);
1447 DUMP_REG(DC_DISP_DISP_MISC_CONTROL
);
1448 DUMP_REG(DC_DISP_SD_CONTROL
);
1449 DUMP_REG(DC_DISP_SD_CSC_COEFF
);
1450 DUMP_REG(DC_DISP_SD_LUT(0));
1451 DUMP_REG(DC_DISP_SD_LUT(1));
1452 DUMP_REG(DC_DISP_SD_LUT(2));
1453 DUMP_REG(DC_DISP_SD_LUT(3));
1454 DUMP_REG(DC_DISP_SD_LUT(4));
1455 DUMP_REG(DC_DISP_SD_LUT(5));
1456 DUMP_REG(DC_DISP_SD_LUT(6));
1457 DUMP_REG(DC_DISP_SD_LUT(7));
1458 DUMP_REG(DC_DISP_SD_LUT(8));
1459 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL
);
1460 DUMP_REG(DC_DISP_DC_PIXEL_COUNT
);
1461 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1462 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1463 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1464 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1465 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1466 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1467 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1468 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1469 DUMP_REG(DC_DISP_SD_BL_TF(0));
1470 DUMP_REG(DC_DISP_SD_BL_TF(1));
1471 DUMP_REG(DC_DISP_SD_BL_TF(2));
1472 DUMP_REG(DC_DISP_SD_BL_TF(3));
1473 DUMP_REG(DC_DISP_SD_BL_CONTROL
);
1474 DUMP_REG(DC_DISP_SD_HW_K_VALUES
);
1475 DUMP_REG(DC_DISP_SD_MAN_K_VALUES
);
1476 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI
);
1477 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL
);
1478 DUMP_REG(DC_WIN_WIN_OPTIONS
);
1479 DUMP_REG(DC_WIN_BYTE_SWAP
);
1480 DUMP_REG(DC_WIN_BUFFER_CONTROL
);
1481 DUMP_REG(DC_WIN_COLOR_DEPTH
);
1482 DUMP_REG(DC_WIN_POSITION
);
1483 DUMP_REG(DC_WIN_SIZE
);
1484 DUMP_REG(DC_WIN_PRESCALED_SIZE
);
1485 DUMP_REG(DC_WIN_H_INITIAL_DDA
);
1486 DUMP_REG(DC_WIN_V_INITIAL_DDA
);
1487 DUMP_REG(DC_WIN_DDA_INC
);
1488 DUMP_REG(DC_WIN_LINE_STRIDE
);
1489 DUMP_REG(DC_WIN_BUF_STRIDE
);
1490 DUMP_REG(DC_WIN_UV_BUF_STRIDE
);
1491 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE
);
1492 DUMP_REG(DC_WIN_DV_CONTROL
);
1493 DUMP_REG(DC_WIN_BLEND_NOKEY
);
1494 DUMP_REG(DC_WIN_BLEND_1WIN
);
1495 DUMP_REG(DC_WIN_BLEND_2WIN_X
);
1496 DUMP_REG(DC_WIN_BLEND_2WIN_Y
);
1497 DUMP_REG(DC_WIN_BLEND_3WIN_XY
);
1498 DUMP_REG(DC_WIN_HP_FETCH_CONTROL
);
1499 DUMP_REG(DC_WINBUF_START_ADDR
);
1500 DUMP_REG(DC_WINBUF_START_ADDR_NS
);
1501 DUMP_REG(DC_WINBUF_START_ADDR_U
);
1502 DUMP_REG(DC_WINBUF_START_ADDR_U_NS
);
1503 DUMP_REG(DC_WINBUF_START_ADDR_V
);
1504 DUMP_REG(DC_WINBUF_START_ADDR_V_NS
);
1505 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET
);
1506 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS
);
1507 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET
);
1508 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS
);
1509 DUMP_REG(DC_WINBUF_UFLOW_STATUS
);
1510 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS
);
1511 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS
);
1512 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS
);
1519 static struct drm_info_list debugfs_files
[] = {
1520 { "regs", tegra_dc_show_regs
, 0, NULL
},
1523 static int tegra_dc_debugfs_init(struct tegra_dc
*dc
, struct drm_minor
*minor
)
1529 name
= kasprintf(GFP_KERNEL
, "dc.%d", dc
->pipe
);
1530 dc
->debugfs
= debugfs_create_dir(name
, minor
->debugfs_root
);
1536 dc
->debugfs_files
= kmemdup(debugfs_files
, sizeof(debugfs_files
),
1538 if (!dc
->debugfs_files
) {
1543 for (i
= 0; i
< ARRAY_SIZE(debugfs_files
); i
++)
1544 dc
->debugfs_files
[i
].data
= dc
;
1546 err
= drm_debugfs_create_files(dc
->debugfs_files
,
1547 ARRAY_SIZE(debugfs_files
),
1548 dc
->debugfs
, minor
);
1557 kfree(dc
->debugfs_files
);
1558 dc
->debugfs_files
= NULL
;
1560 debugfs_remove(dc
->debugfs
);
1566 static int tegra_dc_debugfs_exit(struct tegra_dc
*dc
)
1568 drm_debugfs_remove_files(dc
->debugfs_files
, ARRAY_SIZE(debugfs_files
),
1572 kfree(dc
->debugfs_files
);
1573 dc
->debugfs_files
= NULL
;
1575 debugfs_remove(dc
->debugfs
);
1581 static int tegra_dc_init(struct host1x_client
*client
)
1583 struct drm_device
*drm
= dev_get_drvdata(client
->parent
);
1584 struct tegra_dc
*dc
= host1x_client_to_dc(client
);
1585 struct tegra_drm
*tegra
= drm
->dev_private
;
1586 struct drm_plane
*primary
= NULL
;
1587 struct drm_plane
*cursor
= NULL
;
1590 if (tegra
->domain
) {
1591 err
= iommu_attach_device(tegra
->domain
, dc
->dev
);
1593 dev_err(dc
->dev
, "failed to attach to domain: %d\n",
1598 dc
->domain
= tegra
->domain
;
1601 primary
= tegra_dc_primary_plane_create(drm
, dc
);
1602 if (IS_ERR(primary
)) {
1603 err
= PTR_ERR(primary
);
1607 if (dc
->soc
->supports_cursor
) {
1608 cursor
= tegra_dc_cursor_plane_create(drm
, dc
);
1609 if (IS_ERR(cursor
)) {
1610 err
= PTR_ERR(cursor
);
1615 err
= drm_crtc_init_with_planes(drm
, &dc
->base
, primary
, cursor
,
1620 drm_mode_crtc_set_gamma_size(&dc
->base
, 256);
1621 drm_crtc_helper_add(&dc
->base
, &tegra_crtc_helper_funcs
);
1624 * Keep track of the minimum pitch alignment across all display
1627 if (dc
->soc
->pitch_align
> tegra
->pitch_align
)
1628 tegra
->pitch_align
= dc
->soc
->pitch_align
;
1630 err
= tegra_dc_rgb_init(drm
, dc
);
1631 if (err
< 0 && err
!= -ENODEV
) {
1632 dev_err(dc
->dev
, "failed to initialize RGB output: %d\n", err
);
1636 err
= tegra_dc_add_planes(drm
, dc
);
1640 if (IS_ENABLED(CONFIG_DEBUG_FS
)) {
1641 err
= tegra_dc_debugfs_init(dc
, drm
->primary
);
1643 dev_err(dc
->dev
, "debugfs setup failed: %d\n", err
);
1646 err
= devm_request_irq(dc
->dev
, dc
->irq
, tegra_dc_irq
, 0,
1647 dev_name(dc
->dev
), dc
);
1649 dev_err(dc
->dev
, "failed to request IRQ#%u: %d\n", dc
->irq
,
1658 drm_plane_cleanup(cursor
);
1661 drm_plane_cleanup(primary
);
1663 if (tegra
->domain
) {
1664 iommu_detach_device(tegra
->domain
, dc
->dev
);
1671 static int tegra_dc_exit(struct host1x_client
*client
)
1673 struct tegra_dc
*dc
= host1x_client_to_dc(client
);
1676 devm_free_irq(dc
->dev
, dc
->irq
, dc
);
1678 if (IS_ENABLED(CONFIG_DEBUG_FS
)) {
1679 err
= tegra_dc_debugfs_exit(dc
);
1681 dev_err(dc
->dev
, "debugfs cleanup failed: %d\n", err
);
1684 err
= tegra_dc_rgb_exit(dc
);
1686 dev_err(dc
->dev
, "failed to shutdown RGB output: %d\n", err
);
1691 iommu_detach_device(dc
->domain
, dc
->dev
);
1698 static const struct host1x_client_ops dc_client_ops
= {
1699 .init
= tegra_dc_init
,
1700 .exit
= tegra_dc_exit
,
1703 static const struct tegra_dc_soc_info tegra20_dc_soc_info
= {
1704 .supports_border_color
= true,
1705 .supports_interlacing
= false,
1706 .supports_cursor
= false,
1707 .supports_block_linear
= false,
1709 .has_powergate
= false,
1712 static const struct tegra_dc_soc_info tegra30_dc_soc_info
= {
1713 .supports_border_color
= true,
1714 .supports_interlacing
= false,
1715 .supports_cursor
= false,
1716 .supports_block_linear
= false,
1718 .has_powergate
= false,
1721 static const struct tegra_dc_soc_info tegra114_dc_soc_info
= {
1722 .supports_border_color
= true,
1723 .supports_interlacing
= false,
1724 .supports_cursor
= false,
1725 .supports_block_linear
= false,
1727 .has_powergate
= true,
1730 static const struct tegra_dc_soc_info tegra124_dc_soc_info
= {
1731 .supports_border_color
= false,
1732 .supports_interlacing
= true,
1733 .supports_cursor
= true,
1734 .supports_block_linear
= true,
1736 .has_powergate
= true,
1739 static const struct of_device_id tegra_dc_of_match
[] = {
1741 .compatible
= "nvidia,tegra124-dc",
1742 .data
= &tegra124_dc_soc_info
,
1744 .compatible
= "nvidia,tegra114-dc",
1745 .data
= &tegra114_dc_soc_info
,
1747 .compatible
= "nvidia,tegra30-dc",
1748 .data
= &tegra30_dc_soc_info
,
1750 .compatible
= "nvidia,tegra20-dc",
1751 .data
= &tegra20_dc_soc_info
,
1756 MODULE_DEVICE_TABLE(of
, tegra_dc_of_match
);
1758 static int tegra_dc_parse_dt(struct tegra_dc
*dc
)
1760 struct device_node
*np
;
1764 err
= of_property_read_u32(dc
->dev
->of_node
, "nvidia,head", &value
);
1766 dev_err(dc
->dev
, "missing \"nvidia,head\" property\n");
1769 * If the nvidia,head property isn't present, try to find the
1770 * correct head number by looking up the position of this
1771 * display controller's node within the device tree. Assuming
1772 * that the nodes are ordered properly in the DTS file and
1773 * that the translation into a flattened device tree blob
1774 * preserves that ordering this will actually yield the right
1777 * If those assumptions don't hold, this will still work for
1778 * cases where only a single display controller is used.
1780 for_each_matching_node(np
, tegra_dc_of_match
) {
1781 if (np
== dc
->dev
->of_node
)
1793 static int tegra_dc_probe(struct platform_device
*pdev
)
1795 const struct of_device_id
*id
;
1796 struct resource
*regs
;
1797 struct tegra_dc
*dc
;
1800 dc
= devm_kzalloc(&pdev
->dev
, sizeof(*dc
), GFP_KERNEL
);
1804 id
= of_match_node(tegra_dc_of_match
, pdev
->dev
.of_node
);
1808 spin_lock_init(&dc
->lock
);
1809 INIT_LIST_HEAD(&dc
->list
);
1810 dc
->dev
= &pdev
->dev
;
1813 err
= tegra_dc_parse_dt(dc
);
1817 dc
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1818 if (IS_ERR(dc
->clk
)) {
1819 dev_err(&pdev
->dev
, "failed to get clock\n");
1820 return PTR_ERR(dc
->clk
);
1823 dc
->rst
= devm_reset_control_get(&pdev
->dev
, "dc");
1824 if (IS_ERR(dc
->rst
)) {
1825 dev_err(&pdev
->dev
, "failed to get reset\n");
1826 return PTR_ERR(dc
->rst
);
1829 if (dc
->soc
->has_powergate
) {
1831 dc
->powergate
= TEGRA_POWERGATE_DIS
;
1833 dc
->powergate
= TEGRA_POWERGATE_DISB
;
1835 err
= tegra_powergate_sequence_power_up(dc
->powergate
, dc
->clk
,
1838 dev_err(&pdev
->dev
, "failed to power partition: %d\n",
1843 err
= clk_prepare_enable(dc
->clk
);
1845 dev_err(&pdev
->dev
, "failed to enable clock: %d\n",
1850 err
= reset_control_deassert(dc
->rst
);
1852 dev_err(&pdev
->dev
, "failed to deassert reset: %d\n",
1858 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1859 dc
->regs
= devm_ioremap_resource(&pdev
->dev
, regs
);
1860 if (IS_ERR(dc
->regs
))
1861 return PTR_ERR(dc
->regs
);
1863 dc
->irq
= platform_get_irq(pdev
, 0);
1865 dev_err(&pdev
->dev
, "failed to get IRQ\n");
1869 INIT_LIST_HEAD(&dc
->client
.list
);
1870 dc
->client
.ops
= &dc_client_ops
;
1871 dc
->client
.dev
= &pdev
->dev
;
1873 err
= tegra_dc_rgb_probe(dc
);
1874 if (err
< 0 && err
!= -ENODEV
) {
1875 dev_err(&pdev
->dev
, "failed to probe RGB output: %d\n", err
);
1879 err
= host1x_client_register(&dc
->client
);
1881 dev_err(&pdev
->dev
, "failed to register host1x client: %d\n",
1886 platform_set_drvdata(pdev
, dc
);
1891 static int tegra_dc_remove(struct platform_device
*pdev
)
1893 struct tegra_dc
*dc
= platform_get_drvdata(pdev
);
1896 err
= host1x_client_unregister(&dc
->client
);
1898 dev_err(&pdev
->dev
, "failed to unregister host1x client: %d\n",
1903 err
= tegra_dc_rgb_remove(dc
);
1905 dev_err(&pdev
->dev
, "failed to remove RGB output: %d\n", err
);
1909 reset_control_assert(dc
->rst
);
1911 if (dc
->soc
->has_powergate
)
1912 tegra_powergate_power_off(dc
->powergate
);
1914 clk_disable_unprepare(dc
->clk
);
1919 struct platform_driver tegra_dc_driver
= {
1922 .owner
= THIS_MODULE
,
1923 .of_match_table
= tegra_dc_of_match
,
1925 .probe
= tegra_dc_probe
,
1926 .remove
= tegra_dc_remove
,