2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/reset.h>
18 struct tegra_dc_soc_info
{
19 bool supports_interlacing
;
23 struct drm_plane base
;
27 static inline struct tegra_plane
*to_tegra_plane(struct drm_plane
*plane
)
29 return container_of(plane
, struct tegra_plane
, base
);
32 static int tegra_plane_update(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
33 struct drm_framebuffer
*fb
, int crtc_x
,
34 int crtc_y
, unsigned int crtc_w
,
35 unsigned int crtc_h
, uint32_t src_x
,
36 uint32_t src_y
, uint32_t src_w
, uint32_t src_h
)
38 struct tegra_plane
*p
= to_tegra_plane(plane
);
39 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
40 struct tegra_dc_window window
;
43 memset(&window
, 0, sizeof(window
));
44 window
.src
.x
= src_x
>> 16;
45 window
.src
.y
= src_y
>> 16;
46 window
.src
.w
= src_w
>> 16;
47 window
.src
.h
= src_h
>> 16;
48 window
.dst
.x
= crtc_x
;
49 window
.dst
.y
= crtc_y
;
50 window
.dst
.w
= crtc_w
;
51 window
.dst
.h
= crtc_h
;
52 window
.format
= tegra_dc_format(fb
->pixel_format
, &window
.swap
);
53 window
.bits_per_pixel
= fb
->bits_per_pixel
;
54 window
.bottom_up
= tegra_fb_is_bottom_up(fb
);
55 window
.tiled
= tegra_fb_is_tiled(fb
);
57 for (i
= 0; i
< drm_format_num_planes(fb
->pixel_format
); i
++) {
58 struct tegra_bo
*bo
= tegra_fb_get_plane(fb
, i
);
60 window
.base
[i
] = bo
->paddr
+ fb
->offsets
[i
];
63 * Tegra doesn't support different strides for U and V planes
64 * so we display a warning if the user tries to display a
65 * framebuffer with such a configuration.
68 if (fb
->pitches
[i
] != window
.stride
[1])
69 DRM_ERROR("unsupported UV-plane configuration\n");
71 window
.stride
[i
] = fb
->pitches
[i
];
75 return tegra_dc_setup_window(dc
, p
->index
, &window
);
78 static int tegra_plane_disable(struct drm_plane
*plane
)
80 struct tegra_dc
*dc
= to_tegra_dc(plane
->crtc
);
81 struct tegra_plane
*p
= to_tegra_plane(plane
);
87 value
= WINDOW_A_SELECT
<< p
->index
;
88 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_WINDOW_HEADER
);
90 value
= tegra_dc_readl(dc
, DC_WIN_WIN_OPTIONS
);
92 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
94 tegra_dc_writel(dc
, WIN_A_UPDATE
<< p
->index
, DC_CMD_STATE_CONTROL
);
95 tegra_dc_writel(dc
, WIN_A_ACT_REQ
<< p
->index
, DC_CMD_STATE_CONTROL
);
100 static void tegra_plane_destroy(struct drm_plane
*plane
)
102 struct tegra_plane
*p
= to_tegra_plane(plane
);
104 tegra_plane_disable(plane
);
105 drm_plane_cleanup(plane
);
109 static const struct drm_plane_funcs tegra_plane_funcs
= {
110 .update_plane
= tegra_plane_update
,
111 .disable_plane
= tegra_plane_disable
,
112 .destroy
= tegra_plane_destroy
,
115 static const uint32_t plane_formats
[] = {
125 static int tegra_dc_add_planes(struct drm_device
*drm
, struct tegra_dc
*dc
)
130 for (i
= 0; i
< 2; i
++) {
131 struct tegra_plane
*plane
;
133 plane
= kzalloc(sizeof(*plane
), GFP_KERNEL
);
137 plane
->index
= 1 + i
;
139 err
= drm_plane_init(drm
, &plane
->base
, 1 << dc
->pipe
,
140 &tegra_plane_funcs
, plane_formats
,
141 ARRAY_SIZE(plane_formats
), false);
151 static int tegra_dc_set_base(struct tegra_dc
*dc
, int x
, int y
,
152 struct drm_framebuffer
*fb
)
154 struct tegra_bo
*bo
= tegra_fb_get_plane(fb
, 0);
155 unsigned int h_offset
= 0, v_offset
= 0;
156 unsigned int format
, swap
;
159 tegra_dc_writel(dc
, WINDOW_A_SELECT
, DC_CMD_DISPLAY_WINDOW_HEADER
);
161 value
= fb
->offsets
[0] + y
* fb
->pitches
[0] +
162 x
* fb
->bits_per_pixel
/ 8;
164 tegra_dc_writel(dc
, bo
->paddr
+ value
, DC_WINBUF_START_ADDR
);
165 tegra_dc_writel(dc
, fb
->pitches
[0], DC_WIN_LINE_STRIDE
);
167 format
= tegra_dc_format(fb
->pixel_format
, &swap
);
168 tegra_dc_writel(dc
, format
, DC_WIN_COLOR_DEPTH
);
169 tegra_dc_writel(dc
, swap
, DC_WIN_BYTE_SWAP
);
171 if (tegra_fb_is_tiled(fb
)) {
172 value
= DC_WIN_BUFFER_ADDR_MODE_TILE_UV
|
173 DC_WIN_BUFFER_ADDR_MODE_TILE
;
175 value
= DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV
|
176 DC_WIN_BUFFER_ADDR_MODE_LINEAR
;
179 tegra_dc_writel(dc
, value
, DC_WIN_BUFFER_ADDR_MODE
);
181 /* make sure bottom-up buffers are properly displayed */
182 if (tegra_fb_is_bottom_up(fb
)) {
183 value
= tegra_dc_readl(dc
, DC_WIN_WIN_OPTIONS
);
184 value
|= V_DIRECTION
;
185 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
187 v_offset
+= fb
->height
- 1;
189 value
= tegra_dc_readl(dc
, DC_WIN_WIN_OPTIONS
);
190 value
&= ~V_DIRECTION
;
191 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
194 tegra_dc_writel(dc
, h_offset
, DC_WINBUF_ADDR_H_OFFSET
);
195 tegra_dc_writel(dc
, v_offset
, DC_WINBUF_ADDR_V_OFFSET
);
197 value
= GENERAL_UPDATE
| WIN_A_UPDATE
;
198 tegra_dc_writel(dc
, value
, DC_CMD_STATE_CONTROL
);
200 value
= GENERAL_ACT_REQ
| WIN_A_ACT_REQ
;
201 tegra_dc_writel(dc
, value
, DC_CMD_STATE_CONTROL
);
206 void tegra_dc_enable_vblank(struct tegra_dc
*dc
)
208 unsigned long value
, flags
;
210 spin_lock_irqsave(&dc
->lock
, flags
);
212 value
= tegra_dc_readl(dc
, DC_CMD_INT_MASK
);
214 tegra_dc_writel(dc
, value
, DC_CMD_INT_MASK
);
216 spin_unlock_irqrestore(&dc
->lock
, flags
);
219 void tegra_dc_disable_vblank(struct tegra_dc
*dc
)
221 unsigned long value
, flags
;
223 spin_lock_irqsave(&dc
->lock
, flags
);
225 value
= tegra_dc_readl(dc
, DC_CMD_INT_MASK
);
226 value
&= ~VBLANK_INT
;
227 tegra_dc_writel(dc
, value
, DC_CMD_INT_MASK
);
229 spin_unlock_irqrestore(&dc
->lock
, flags
);
232 static void tegra_dc_finish_page_flip(struct tegra_dc
*dc
)
234 struct drm_device
*drm
= dc
->base
.dev
;
235 struct drm_crtc
*crtc
= &dc
->base
;
236 unsigned long flags
, base
;
242 bo
= tegra_fb_get_plane(crtc
->primary
->fb
, 0);
244 /* check if new start address has been latched */
245 tegra_dc_writel(dc
, READ_MUX
, DC_CMD_STATE_ACCESS
);
246 base
= tegra_dc_readl(dc
, DC_WINBUF_START_ADDR
);
247 tegra_dc_writel(dc
, 0, DC_CMD_STATE_ACCESS
);
249 if (base
== bo
->paddr
+ crtc
->primary
->fb
->offsets
[0]) {
250 spin_lock_irqsave(&drm
->event_lock
, flags
);
251 drm_send_vblank_event(drm
, dc
->pipe
, dc
->event
);
252 drm_vblank_put(drm
, dc
->pipe
);
254 spin_unlock_irqrestore(&drm
->event_lock
, flags
);
258 void tegra_dc_cancel_page_flip(struct drm_crtc
*crtc
, struct drm_file
*file
)
260 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
261 struct drm_device
*drm
= crtc
->dev
;
264 spin_lock_irqsave(&drm
->event_lock
, flags
);
266 if (dc
->event
&& dc
->event
->base
.file_priv
== file
) {
267 dc
->event
->base
.destroy(&dc
->event
->base
);
268 drm_vblank_put(drm
, dc
->pipe
);
272 spin_unlock_irqrestore(&drm
->event_lock
, flags
);
275 static int tegra_dc_page_flip(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
276 struct drm_pending_vblank_event
*event
, uint32_t page_flip_flags
)
278 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
279 struct drm_device
*drm
= crtc
->dev
;
285 event
->pipe
= dc
->pipe
;
287 drm_vblank_get(drm
, dc
->pipe
);
290 tegra_dc_set_base(dc
, 0, 0, fb
);
291 crtc
->primary
->fb
= fb
;
296 static void drm_crtc_clear(struct drm_crtc
*crtc
)
298 memset(crtc
, 0, sizeof(*crtc
));
301 static void tegra_dc_destroy(struct drm_crtc
*crtc
)
303 drm_crtc_cleanup(crtc
);
304 drm_crtc_clear(crtc
);
307 static const struct drm_crtc_funcs tegra_crtc_funcs
= {
308 .page_flip
= tegra_dc_page_flip
,
309 .set_config
= drm_crtc_helper_set_config
,
310 .destroy
= tegra_dc_destroy
,
313 static void tegra_crtc_disable(struct drm_crtc
*crtc
)
315 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
316 struct drm_device
*drm
= crtc
->dev
;
317 struct drm_plane
*plane
;
319 drm_for_each_legacy_plane(plane
, &drm
->mode_config
.plane_list
) {
320 if (plane
->crtc
== crtc
) {
321 tegra_plane_disable(plane
);
325 drm_framebuffer_unreference(plane
->fb
);
331 drm_vblank_off(drm
, dc
->pipe
);
334 static bool tegra_crtc_mode_fixup(struct drm_crtc
*crtc
,
335 const struct drm_display_mode
*mode
,
336 struct drm_display_mode
*adjusted
)
341 static inline u32
compute_dda_inc(unsigned int in
, unsigned int out
, bool v
,
344 fixed20_12 outf
= dfixed_init(out
);
345 fixed20_12 inf
= dfixed_init(in
);
366 outf
.full
= max_t(u32
, outf
.full
- dfixed_const(1), dfixed_const(1));
367 inf
.full
-= dfixed_const(1);
369 dda_inc
= dfixed_div(inf
, outf
);
370 dda_inc
= min_t(u32
, dda_inc
, dfixed_const(max
));
375 static inline u32
compute_initial_dda(unsigned int in
)
377 fixed20_12 inf
= dfixed_init(in
);
378 return dfixed_frac(inf
);
381 static int tegra_dc_set_timings(struct tegra_dc
*dc
,
382 struct drm_display_mode
*mode
)
384 /* TODO: For HDMI compliance, h & v ref_to_sync should be set to 1 */
385 unsigned int h_ref_to_sync
= 0;
386 unsigned int v_ref_to_sync
= 0;
389 tegra_dc_writel(dc
, 0x0, DC_DISP_DISP_TIMING_OPTIONS
);
391 value
= (v_ref_to_sync
<< 16) | h_ref_to_sync
;
392 tegra_dc_writel(dc
, value
, DC_DISP_REF_TO_SYNC
);
394 value
= ((mode
->vsync_end
- mode
->vsync_start
) << 16) |
395 ((mode
->hsync_end
- mode
->hsync_start
) << 0);
396 tegra_dc_writel(dc
, value
, DC_DISP_SYNC_WIDTH
);
398 value
= ((mode
->vtotal
- mode
->vsync_end
) << 16) |
399 ((mode
->htotal
- mode
->hsync_end
) << 0);
400 tegra_dc_writel(dc
, value
, DC_DISP_BACK_PORCH
);
402 value
= ((mode
->vsync_start
- mode
->vdisplay
) << 16) |
403 ((mode
->hsync_start
- mode
->hdisplay
) << 0);
404 tegra_dc_writel(dc
, value
, DC_DISP_FRONT_PORCH
);
406 value
= (mode
->vdisplay
<< 16) | mode
->hdisplay
;
407 tegra_dc_writel(dc
, value
, DC_DISP_ACTIVE
);
412 static int tegra_crtc_setup_clk(struct drm_crtc
*crtc
,
413 struct drm_display_mode
*mode
,
416 unsigned long pclk
= mode
->clock
* 1000, rate
;
417 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
418 struct tegra_output
*output
= NULL
;
419 struct drm_encoder
*encoder
;
422 list_for_each_entry(encoder
, &crtc
->dev
->mode_config
.encoder_list
, head
)
423 if (encoder
->crtc
== crtc
) {
424 output
= encoder_to_output(encoder
);
432 * This assumes that the display controller will divide its parent
433 * clock by 2 to generate the pixel clock.
435 err
= tegra_output_setup_clock(output
, dc
->clk
, pclk
* 2);
437 dev_err(dc
->dev
, "failed to setup clock: %ld\n", err
);
441 rate
= clk_get_rate(dc
->clk
);
442 *div
= (rate
* 2 / pclk
) - 2;
444 DRM_DEBUG_KMS("rate: %lu, div: %lu\n", rate
, *div
);
449 static bool tegra_dc_format_is_yuv(unsigned int format
, bool *planar
)
452 case WIN_COLOR_DEPTH_YCbCr422
:
453 case WIN_COLOR_DEPTH_YUV422
:
459 case WIN_COLOR_DEPTH_YCbCr420P
:
460 case WIN_COLOR_DEPTH_YUV420P
:
461 case WIN_COLOR_DEPTH_YCbCr422P
:
462 case WIN_COLOR_DEPTH_YUV422P
:
463 case WIN_COLOR_DEPTH_YCbCr422R
:
464 case WIN_COLOR_DEPTH_YUV422R
:
465 case WIN_COLOR_DEPTH_YCbCr422RA
:
466 case WIN_COLOR_DEPTH_YUV422RA
:
476 int tegra_dc_setup_window(struct tegra_dc
*dc
, unsigned int index
,
477 const struct tegra_dc_window
*window
)
479 unsigned h_offset
, v_offset
, h_size
, v_size
, h_dda
, v_dda
, bpp
;
484 * For YUV planar modes, the number of bytes per pixel takes into
485 * account only the luma component and therefore is 1.
487 yuv
= tegra_dc_format_is_yuv(window
->format
, &planar
);
489 bpp
= window
->bits_per_pixel
/ 8;
491 bpp
= planar
? 1 : 2;
493 value
= WINDOW_A_SELECT
<< index
;
494 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_WINDOW_HEADER
);
496 tegra_dc_writel(dc
, window
->format
, DC_WIN_COLOR_DEPTH
);
497 tegra_dc_writel(dc
, window
->swap
, DC_WIN_BYTE_SWAP
);
499 value
= V_POSITION(window
->dst
.y
) | H_POSITION(window
->dst
.x
);
500 tegra_dc_writel(dc
, value
, DC_WIN_POSITION
);
502 value
= V_SIZE(window
->dst
.h
) | H_SIZE(window
->dst
.w
);
503 tegra_dc_writel(dc
, value
, DC_WIN_SIZE
);
505 h_offset
= window
->src
.x
* bpp
;
506 v_offset
= window
->src
.y
;
507 h_size
= window
->src
.w
* bpp
;
508 v_size
= window
->src
.h
;
510 value
= V_PRESCALED_SIZE(v_size
) | H_PRESCALED_SIZE(h_size
);
511 tegra_dc_writel(dc
, value
, DC_WIN_PRESCALED_SIZE
);
514 * For DDA computations the number of bytes per pixel for YUV planar
515 * modes needs to take into account all Y, U and V components.
520 h_dda
= compute_dda_inc(window
->src
.w
, window
->dst
.w
, false, bpp
);
521 v_dda
= compute_dda_inc(window
->src
.h
, window
->dst
.h
, true, bpp
);
523 value
= V_DDA_INC(v_dda
) | H_DDA_INC(h_dda
);
524 tegra_dc_writel(dc
, value
, DC_WIN_DDA_INC
);
526 h_dda
= compute_initial_dda(window
->src
.x
);
527 v_dda
= compute_initial_dda(window
->src
.y
);
529 tegra_dc_writel(dc
, h_dda
, DC_WIN_H_INITIAL_DDA
);
530 tegra_dc_writel(dc
, v_dda
, DC_WIN_V_INITIAL_DDA
);
532 tegra_dc_writel(dc
, 0, DC_WIN_UV_BUF_STRIDE
);
533 tegra_dc_writel(dc
, 0, DC_WIN_BUF_STRIDE
);
535 tegra_dc_writel(dc
, window
->base
[0], DC_WINBUF_START_ADDR
);
538 tegra_dc_writel(dc
, window
->base
[1], DC_WINBUF_START_ADDR_U
);
539 tegra_dc_writel(dc
, window
->base
[2], DC_WINBUF_START_ADDR_V
);
540 value
= window
->stride
[1] << 16 | window
->stride
[0];
541 tegra_dc_writel(dc
, value
, DC_WIN_LINE_STRIDE
);
543 tegra_dc_writel(dc
, window
->stride
[0], DC_WIN_LINE_STRIDE
);
546 if (window
->bottom_up
)
547 v_offset
+= window
->src
.h
- 1;
549 tegra_dc_writel(dc
, h_offset
, DC_WINBUF_ADDR_H_OFFSET
);
550 tegra_dc_writel(dc
, v_offset
, DC_WINBUF_ADDR_V_OFFSET
);
553 value
= DC_WIN_BUFFER_ADDR_MODE_TILE_UV
|
554 DC_WIN_BUFFER_ADDR_MODE_TILE
;
556 value
= DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV
|
557 DC_WIN_BUFFER_ADDR_MODE_LINEAR
;
560 tegra_dc_writel(dc
, value
, DC_WIN_BUFFER_ADDR_MODE
);
565 /* setup default colorspace conversion coefficients */
566 tegra_dc_writel(dc
, 0x00f0, DC_WIN_CSC_YOF
);
567 tegra_dc_writel(dc
, 0x012a, DC_WIN_CSC_KYRGB
);
568 tegra_dc_writel(dc
, 0x0000, DC_WIN_CSC_KUR
);
569 tegra_dc_writel(dc
, 0x0198, DC_WIN_CSC_KVR
);
570 tegra_dc_writel(dc
, 0x039b, DC_WIN_CSC_KUG
);
571 tegra_dc_writel(dc
, 0x032f, DC_WIN_CSC_KVG
);
572 tegra_dc_writel(dc
, 0x0204, DC_WIN_CSC_KUB
);
573 tegra_dc_writel(dc
, 0x0000, DC_WIN_CSC_KVB
);
576 } else if (window
->bits_per_pixel
< 24) {
577 value
|= COLOR_EXPAND
;
580 if (window
->bottom_up
)
581 value
|= V_DIRECTION
;
583 tegra_dc_writel(dc
, value
, DC_WIN_WIN_OPTIONS
);
586 * Disable blending and assume Window A is the bottom-most window,
587 * Window C is the top-most window and Window B is in the middle.
589 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_NOKEY
);
590 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_1WIN
);
594 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_2WIN_X
);
595 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_2WIN_Y
);
596 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_3WIN_XY
);
600 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_2WIN_X
);
601 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_2WIN_Y
);
602 tegra_dc_writel(dc
, 0x000000, DC_WIN_BLEND_3WIN_XY
);
606 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_2WIN_X
);
607 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_2WIN_Y
);
608 tegra_dc_writel(dc
, 0xffff00, DC_WIN_BLEND_3WIN_XY
);
612 tegra_dc_writel(dc
, WIN_A_UPDATE
<< index
, DC_CMD_STATE_CONTROL
);
613 tegra_dc_writel(dc
, WIN_A_ACT_REQ
<< index
, DC_CMD_STATE_CONTROL
);
618 unsigned int tegra_dc_format(uint32_t format
, uint32_t *swap
)
620 /* assume no swapping of fetched data */
622 *swap
= BYTE_SWAP_NOSWAP
;
625 case DRM_FORMAT_XBGR8888
:
626 return WIN_COLOR_DEPTH_R8G8B8A8
;
628 case DRM_FORMAT_XRGB8888
:
629 return WIN_COLOR_DEPTH_B8G8R8A8
;
631 case DRM_FORMAT_RGB565
:
632 return WIN_COLOR_DEPTH_B5G6R5
;
634 case DRM_FORMAT_UYVY
:
635 return WIN_COLOR_DEPTH_YCbCr422
;
637 case DRM_FORMAT_YUYV
:
639 *swap
= BYTE_SWAP_SWAP2
;
641 return WIN_COLOR_DEPTH_YCbCr422
;
643 case DRM_FORMAT_YUV420
:
644 return WIN_COLOR_DEPTH_YCbCr420P
;
646 case DRM_FORMAT_YUV422
:
647 return WIN_COLOR_DEPTH_YCbCr422P
;
653 WARN(1, "unsupported pixel format %u, using default\n", format
);
654 return WIN_COLOR_DEPTH_B8G8R8A8
;
657 static int tegra_crtc_mode_set(struct drm_crtc
*crtc
,
658 struct drm_display_mode
*mode
,
659 struct drm_display_mode
*adjusted
,
660 int x
, int y
, struct drm_framebuffer
*old_fb
)
662 struct tegra_bo
*bo
= tegra_fb_get_plane(crtc
->primary
->fb
, 0);
663 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
664 struct tegra_dc_window window
;
665 unsigned long div
, value
;
668 drm_vblank_pre_modeset(crtc
->dev
, dc
->pipe
);
670 err
= tegra_crtc_setup_clk(crtc
, mode
, &div
);
672 dev_err(dc
->dev
, "failed to setup clock for CRTC: %d\n", err
);
676 /* program display mode */
677 tegra_dc_set_timings(dc
, mode
);
679 /* interlacing isn't supported yet, so disable it */
680 if (dc
->soc
->supports_interlacing
) {
681 value
= tegra_dc_readl(dc
, DC_DISP_INTERLACE_CONTROL
);
682 value
&= ~INTERLACE_ENABLE
;
683 tegra_dc_writel(dc
, value
, DC_DISP_INTERLACE_CONTROL
);
686 value
= SHIFT_CLK_DIVIDER(div
) | PIXEL_CLK_DIVIDER_PCD1
;
687 tegra_dc_writel(dc
, value
, DC_DISP_DISP_CLOCK_CONTROL
);
689 /* setup window parameters */
690 memset(&window
, 0, sizeof(window
));
693 window
.src
.w
= mode
->hdisplay
;
694 window
.src
.h
= mode
->vdisplay
;
697 window
.dst
.w
= mode
->hdisplay
;
698 window
.dst
.h
= mode
->vdisplay
;
699 window
.format
= tegra_dc_format(crtc
->primary
->fb
->pixel_format
,
701 window
.bits_per_pixel
= crtc
->primary
->fb
->bits_per_pixel
;
702 window
.stride
[0] = crtc
->primary
->fb
->pitches
[0];
703 window
.base
[0] = bo
->paddr
;
705 err
= tegra_dc_setup_window(dc
, 0, &window
);
707 dev_err(dc
->dev
, "failed to enable root plane\n");
712 static int tegra_crtc_mode_set_base(struct drm_crtc
*crtc
, int x
, int y
,
713 struct drm_framebuffer
*old_fb
)
715 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
717 return tegra_dc_set_base(dc
, x
, y
, crtc
->primary
->fb
);
720 static void tegra_crtc_prepare(struct drm_crtc
*crtc
)
722 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
726 /* hardware initialization */
727 reset_control_deassert(dc
->rst
);
728 usleep_range(10000, 20000);
731 syncpt
= SYNCPT_VBLANK1
;
733 syncpt
= SYNCPT_VBLANK0
;
735 /* initialize display controller */
736 tegra_dc_writel(dc
, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL
);
737 tegra_dc_writel(dc
, 0x100 | syncpt
, DC_CMD_CONT_SYNCPT_VSYNC
);
739 value
= WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
| WIN_A_OF_INT
;
740 tegra_dc_writel(dc
, value
, DC_CMD_INT_TYPE
);
742 value
= WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
|
743 WIN_A_OF_INT
| WIN_B_OF_INT
| WIN_C_OF_INT
;
744 tegra_dc_writel(dc
, value
, DC_CMD_INT_POLARITY
);
746 value
= PW0_ENABLE
| PW1_ENABLE
| PW2_ENABLE
| PW3_ENABLE
|
747 PW4_ENABLE
| PM0_ENABLE
| PM1_ENABLE
;
748 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_POWER_CONTROL
);
750 /* initialize timer */
751 value
= CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
752 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
753 tegra_dc_writel(dc
, value
, DC_DISP_DISP_MEM_HIGH_PRIORITY
);
755 value
= CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
756 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
757 tegra_dc_writel(dc
, value
, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER
);
759 value
= VBLANK_INT
| WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
;
760 tegra_dc_writel(dc
, value
, DC_CMD_INT_ENABLE
);
762 value
= WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
;
763 tegra_dc_writel(dc
, value
, DC_CMD_INT_MASK
);
766 static void tegra_crtc_commit(struct drm_crtc
*crtc
)
768 struct tegra_dc
*dc
= to_tegra_dc(crtc
);
771 value
= GENERAL_UPDATE
| WIN_A_UPDATE
;
772 tegra_dc_writel(dc
, value
, DC_CMD_STATE_CONTROL
);
774 value
= GENERAL_ACT_REQ
| WIN_A_ACT_REQ
;
775 tegra_dc_writel(dc
, value
, DC_CMD_STATE_CONTROL
);
777 drm_vblank_post_modeset(crtc
->dev
, dc
->pipe
);
780 static void tegra_crtc_load_lut(struct drm_crtc
*crtc
)
784 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs
= {
785 .disable
= tegra_crtc_disable
,
786 .mode_fixup
= tegra_crtc_mode_fixup
,
787 .mode_set
= tegra_crtc_mode_set
,
788 .mode_set_base
= tegra_crtc_mode_set_base
,
789 .prepare
= tegra_crtc_prepare
,
790 .commit
= tegra_crtc_commit
,
791 .load_lut
= tegra_crtc_load_lut
,
794 static irqreturn_t
tegra_dc_irq(int irq
, void *data
)
796 struct tegra_dc
*dc
= data
;
797 unsigned long status
;
799 status
= tegra_dc_readl(dc
, DC_CMD_INT_STATUS
);
800 tegra_dc_writel(dc
, status
, DC_CMD_INT_STATUS
);
802 if (status
& FRAME_END_INT
) {
804 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
808 if (status
& VBLANK_INT
) {
810 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
812 drm_handle_vblank(dc
->base
.dev
, dc
->pipe
);
813 tegra_dc_finish_page_flip(dc
);
816 if (status
& (WIN_A_UF_INT
| WIN_B_UF_INT
| WIN_C_UF_INT
)) {
818 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
825 static int tegra_dc_show_regs(struct seq_file
*s
, void *data
)
827 struct drm_info_node
*node
= s
->private;
828 struct tegra_dc
*dc
= node
->info_ent
->data
;
830 #define DUMP_REG(name) \
831 seq_printf(s, "%-40s %#05x %08lx\n", #name, name, \
832 tegra_dc_readl(dc, name))
834 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT
);
835 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL
);
836 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR
);
837 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT
);
838 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL
);
839 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR
);
840 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT
);
841 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL
);
842 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR
);
843 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT
);
844 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL
);
845 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR
);
846 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC
);
847 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0
);
848 DUMP_REG(DC_CMD_DISPLAY_COMMAND
);
849 DUMP_REG(DC_CMD_SIGNAL_RAISE
);
850 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL
);
851 DUMP_REG(DC_CMD_INT_STATUS
);
852 DUMP_REG(DC_CMD_INT_MASK
);
853 DUMP_REG(DC_CMD_INT_ENABLE
);
854 DUMP_REG(DC_CMD_INT_TYPE
);
855 DUMP_REG(DC_CMD_INT_POLARITY
);
856 DUMP_REG(DC_CMD_SIGNAL_RAISE1
);
857 DUMP_REG(DC_CMD_SIGNAL_RAISE2
);
858 DUMP_REG(DC_CMD_SIGNAL_RAISE3
);
859 DUMP_REG(DC_CMD_STATE_ACCESS
);
860 DUMP_REG(DC_CMD_STATE_CONTROL
);
861 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER
);
862 DUMP_REG(DC_CMD_REG_ACT_CONTROL
);
863 DUMP_REG(DC_COM_CRC_CONTROL
);
864 DUMP_REG(DC_COM_CRC_CHECKSUM
);
865 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
866 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
867 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
868 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
869 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
870 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
871 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
872 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
873 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
874 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
875 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
876 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
877 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
878 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
879 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
880 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
881 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
882 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
883 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
884 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
885 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
886 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
887 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
888 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
889 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
890 DUMP_REG(DC_COM_PIN_MISC_CONTROL
);
891 DUMP_REG(DC_COM_PIN_PM0_CONTROL
);
892 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE
);
893 DUMP_REG(DC_COM_PIN_PM1_CONTROL
);
894 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE
);
895 DUMP_REG(DC_COM_SPI_CONTROL
);
896 DUMP_REG(DC_COM_SPI_START_BYTE
);
897 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB
);
898 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD
);
899 DUMP_REG(DC_COM_HSPI_CS_DC
);
900 DUMP_REG(DC_COM_SCRATCH_REGISTER_A
);
901 DUMP_REG(DC_COM_SCRATCH_REGISTER_B
);
902 DUMP_REG(DC_COM_GPIO_CTRL
);
903 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER
);
904 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED
);
905 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0
);
906 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1
);
907 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS
);
908 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY
);
909 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER
);
910 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS
);
911 DUMP_REG(DC_DISP_REF_TO_SYNC
);
912 DUMP_REG(DC_DISP_SYNC_WIDTH
);
913 DUMP_REG(DC_DISP_BACK_PORCH
);
914 DUMP_REG(DC_DISP_ACTIVE
);
915 DUMP_REG(DC_DISP_FRONT_PORCH
);
916 DUMP_REG(DC_DISP_H_PULSE0_CONTROL
);
917 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A
);
918 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B
);
919 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C
);
920 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D
);
921 DUMP_REG(DC_DISP_H_PULSE1_CONTROL
);
922 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A
);
923 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B
);
924 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C
);
925 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D
);
926 DUMP_REG(DC_DISP_H_PULSE2_CONTROL
);
927 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A
);
928 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B
);
929 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C
);
930 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D
);
931 DUMP_REG(DC_DISP_V_PULSE0_CONTROL
);
932 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A
);
933 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B
);
934 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C
);
935 DUMP_REG(DC_DISP_V_PULSE1_CONTROL
);
936 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A
);
937 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B
);
938 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C
);
939 DUMP_REG(DC_DISP_V_PULSE2_CONTROL
);
940 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A
);
941 DUMP_REG(DC_DISP_V_PULSE3_CONTROL
);
942 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A
);
943 DUMP_REG(DC_DISP_M0_CONTROL
);
944 DUMP_REG(DC_DISP_M1_CONTROL
);
945 DUMP_REG(DC_DISP_DI_CONTROL
);
946 DUMP_REG(DC_DISP_PP_CONTROL
);
947 DUMP_REG(DC_DISP_PP_SELECT_A
);
948 DUMP_REG(DC_DISP_PP_SELECT_B
);
949 DUMP_REG(DC_DISP_PP_SELECT_C
);
950 DUMP_REG(DC_DISP_PP_SELECT_D
);
951 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL
);
952 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL
);
953 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL
);
954 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS
);
955 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS
);
956 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS
);
957 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS
);
958 DUMP_REG(DC_DISP_BORDER_COLOR
);
959 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER
);
960 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER
);
961 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER
);
962 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER
);
963 DUMP_REG(DC_DISP_CURSOR_FOREGROUND
);
964 DUMP_REG(DC_DISP_CURSOR_BACKGROUND
);
965 DUMP_REG(DC_DISP_CURSOR_START_ADDR
);
966 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS
);
967 DUMP_REG(DC_DISP_CURSOR_POSITION
);
968 DUMP_REG(DC_DISP_CURSOR_POSITION_NS
);
969 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL
);
970 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A
);
971 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B
);
972 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C
);
973 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D
);
974 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL
);
975 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST
);
976 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST
);
977 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST
);
978 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST
);
979 DUMP_REG(DC_DISP_DAC_CRT_CTRL
);
980 DUMP_REG(DC_DISP_DISP_MISC_CONTROL
);
981 DUMP_REG(DC_DISP_SD_CONTROL
);
982 DUMP_REG(DC_DISP_SD_CSC_COEFF
);
983 DUMP_REG(DC_DISP_SD_LUT(0));
984 DUMP_REG(DC_DISP_SD_LUT(1));
985 DUMP_REG(DC_DISP_SD_LUT(2));
986 DUMP_REG(DC_DISP_SD_LUT(3));
987 DUMP_REG(DC_DISP_SD_LUT(4));
988 DUMP_REG(DC_DISP_SD_LUT(5));
989 DUMP_REG(DC_DISP_SD_LUT(6));
990 DUMP_REG(DC_DISP_SD_LUT(7));
991 DUMP_REG(DC_DISP_SD_LUT(8));
992 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL
);
993 DUMP_REG(DC_DISP_DC_PIXEL_COUNT
);
994 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
995 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
996 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
997 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
998 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
999 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1000 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1001 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1002 DUMP_REG(DC_DISP_SD_BL_TF(0));
1003 DUMP_REG(DC_DISP_SD_BL_TF(1));
1004 DUMP_REG(DC_DISP_SD_BL_TF(2));
1005 DUMP_REG(DC_DISP_SD_BL_TF(3));
1006 DUMP_REG(DC_DISP_SD_BL_CONTROL
);
1007 DUMP_REG(DC_DISP_SD_HW_K_VALUES
);
1008 DUMP_REG(DC_DISP_SD_MAN_K_VALUES
);
1009 DUMP_REG(DC_WIN_WIN_OPTIONS
);
1010 DUMP_REG(DC_WIN_BYTE_SWAP
);
1011 DUMP_REG(DC_WIN_BUFFER_CONTROL
);
1012 DUMP_REG(DC_WIN_COLOR_DEPTH
);
1013 DUMP_REG(DC_WIN_POSITION
);
1014 DUMP_REG(DC_WIN_SIZE
);
1015 DUMP_REG(DC_WIN_PRESCALED_SIZE
);
1016 DUMP_REG(DC_WIN_H_INITIAL_DDA
);
1017 DUMP_REG(DC_WIN_V_INITIAL_DDA
);
1018 DUMP_REG(DC_WIN_DDA_INC
);
1019 DUMP_REG(DC_WIN_LINE_STRIDE
);
1020 DUMP_REG(DC_WIN_BUF_STRIDE
);
1021 DUMP_REG(DC_WIN_UV_BUF_STRIDE
);
1022 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE
);
1023 DUMP_REG(DC_WIN_DV_CONTROL
);
1024 DUMP_REG(DC_WIN_BLEND_NOKEY
);
1025 DUMP_REG(DC_WIN_BLEND_1WIN
);
1026 DUMP_REG(DC_WIN_BLEND_2WIN_X
);
1027 DUMP_REG(DC_WIN_BLEND_2WIN_Y
);
1028 DUMP_REG(DC_WIN_BLEND_3WIN_XY
);
1029 DUMP_REG(DC_WIN_HP_FETCH_CONTROL
);
1030 DUMP_REG(DC_WINBUF_START_ADDR
);
1031 DUMP_REG(DC_WINBUF_START_ADDR_NS
);
1032 DUMP_REG(DC_WINBUF_START_ADDR_U
);
1033 DUMP_REG(DC_WINBUF_START_ADDR_U_NS
);
1034 DUMP_REG(DC_WINBUF_START_ADDR_V
);
1035 DUMP_REG(DC_WINBUF_START_ADDR_V_NS
);
1036 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET
);
1037 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS
);
1038 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET
);
1039 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS
);
1040 DUMP_REG(DC_WINBUF_UFLOW_STATUS
);
1041 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS
);
1042 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS
);
1043 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS
);
1050 static struct drm_info_list debugfs_files
[] = {
1051 { "regs", tegra_dc_show_regs
, 0, NULL
},
1054 static int tegra_dc_debugfs_init(struct tegra_dc
*dc
, struct drm_minor
*minor
)
1060 name
= kasprintf(GFP_KERNEL
, "dc.%d", dc
->pipe
);
1061 dc
->debugfs
= debugfs_create_dir(name
, minor
->debugfs_root
);
1067 dc
->debugfs_files
= kmemdup(debugfs_files
, sizeof(debugfs_files
),
1069 if (!dc
->debugfs_files
) {
1074 for (i
= 0; i
< ARRAY_SIZE(debugfs_files
); i
++)
1075 dc
->debugfs_files
[i
].data
= dc
;
1077 err
= drm_debugfs_create_files(dc
->debugfs_files
,
1078 ARRAY_SIZE(debugfs_files
),
1079 dc
->debugfs
, minor
);
1088 kfree(dc
->debugfs_files
);
1089 dc
->debugfs_files
= NULL
;
1091 debugfs_remove(dc
->debugfs
);
1097 static int tegra_dc_debugfs_exit(struct tegra_dc
*dc
)
1099 drm_debugfs_remove_files(dc
->debugfs_files
, ARRAY_SIZE(debugfs_files
),
1103 kfree(dc
->debugfs_files
);
1104 dc
->debugfs_files
= NULL
;
1106 debugfs_remove(dc
->debugfs
);
1112 static int tegra_dc_init(struct host1x_client
*client
)
1114 struct tegra_drm
*tegra
= dev_get_drvdata(client
->parent
);
1115 struct tegra_dc
*dc
= host1x_client_to_dc(client
);
1118 drm_crtc_init(tegra
->drm
, &dc
->base
, &tegra_crtc_funcs
);
1119 drm_mode_crtc_set_gamma_size(&dc
->base
, 256);
1120 drm_crtc_helper_add(&dc
->base
, &tegra_crtc_helper_funcs
);
1122 err
= tegra_dc_rgb_init(tegra
->drm
, dc
);
1123 if (err
< 0 && err
!= -ENODEV
) {
1124 dev_err(dc
->dev
, "failed to initialize RGB output: %d\n", err
);
1128 err
= tegra_dc_add_planes(tegra
->drm
, dc
);
1132 if (IS_ENABLED(CONFIG_DEBUG_FS
)) {
1133 err
= tegra_dc_debugfs_init(dc
, tegra
->drm
->primary
);
1135 dev_err(dc
->dev
, "debugfs setup failed: %d\n", err
);
1138 err
= devm_request_irq(dc
->dev
, dc
->irq
, tegra_dc_irq
, 0,
1139 dev_name(dc
->dev
), dc
);
1141 dev_err(dc
->dev
, "failed to request IRQ#%u: %d\n", dc
->irq
,
1149 static int tegra_dc_exit(struct host1x_client
*client
)
1151 struct tegra_dc
*dc
= host1x_client_to_dc(client
);
1154 devm_free_irq(dc
->dev
, dc
->irq
, dc
);
1156 if (IS_ENABLED(CONFIG_DEBUG_FS
)) {
1157 err
= tegra_dc_debugfs_exit(dc
);
1159 dev_err(dc
->dev
, "debugfs cleanup failed: %d\n", err
);
1162 err
= tegra_dc_rgb_exit(dc
);
1164 dev_err(dc
->dev
, "failed to shutdown RGB output: %d\n", err
);
1171 static const struct host1x_client_ops dc_client_ops
= {
1172 .init
= tegra_dc_init
,
1173 .exit
= tegra_dc_exit
,
1176 static const struct tegra_dc_soc_info tegra20_dc_soc_info
= {
1177 .supports_interlacing
= false,
1180 static const struct tegra_dc_soc_info tegra30_dc_soc_info
= {
1181 .supports_interlacing
= false,
1184 static const struct tegra_dc_soc_info tegra124_dc_soc_info
= {
1185 .supports_interlacing
= true,
1188 static const struct of_device_id tegra_dc_of_match
[] = {
1190 .compatible
= "nvidia,tegra124-dc",
1191 .data
= &tegra124_dc_soc_info
,
1193 .compatible
= "nvidia,tegra30-dc",
1194 .data
= &tegra30_dc_soc_info
,
1196 .compatible
= "nvidia,tegra20-dc",
1197 .data
= &tegra20_dc_soc_info
,
1203 static int tegra_dc_parse_dt(struct tegra_dc
*dc
)
1205 struct device_node
*np
;
1209 err
= of_property_read_u32(dc
->dev
->of_node
, "nvidia,head", &value
);
1211 dev_err(dc
->dev
, "missing \"nvidia,head\" property\n");
1214 * If the nvidia,head property isn't present, try to find the
1215 * correct head number by looking up the position of this
1216 * display controller's node within the device tree. Assuming
1217 * that the nodes are ordered properly in the DTS file and
1218 * that the translation into a flattened device tree blob
1219 * preserves that ordering this will actually yield the right
1222 * If those assumptions don't hold, this will still work for
1223 * cases where only a single display controller is used.
1225 for_each_matching_node(np
, tegra_dc_of_match
) {
1226 if (np
== dc
->dev
->of_node
)
1238 static int tegra_dc_probe(struct platform_device
*pdev
)
1240 const struct of_device_id
*id
;
1241 struct resource
*regs
;
1242 struct tegra_dc
*dc
;
1245 dc
= devm_kzalloc(&pdev
->dev
, sizeof(*dc
), GFP_KERNEL
);
1249 id
= of_match_node(tegra_dc_of_match
, pdev
->dev
.of_node
);
1253 spin_lock_init(&dc
->lock
);
1254 INIT_LIST_HEAD(&dc
->list
);
1255 dc
->dev
= &pdev
->dev
;
1258 err
= tegra_dc_parse_dt(dc
);
1262 dc
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1263 if (IS_ERR(dc
->clk
)) {
1264 dev_err(&pdev
->dev
, "failed to get clock\n");
1265 return PTR_ERR(dc
->clk
);
1268 dc
->rst
= devm_reset_control_get(&pdev
->dev
, "dc");
1269 if (IS_ERR(dc
->rst
)) {
1270 dev_err(&pdev
->dev
, "failed to get reset\n");
1271 return PTR_ERR(dc
->rst
);
1274 err
= clk_prepare_enable(dc
->clk
);
1278 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1279 dc
->regs
= devm_ioremap_resource(&pdev
->dev
, regs
);
1280 if (IS_ERR(dc
->regs
))
1281 return PTR_ERR(dc
->regs
);
1283 dc
->irq
= platform_get_irq(pdev
, 0);
1285 dev_err(&pdev
->dev
, "failed to get IRQ\n");
1289 INIT_LIST_HEAD(&dc
->client
.list
);
1290 dc
->client
.ops
= &dc_client_ops
;
1291 dc
->client
.dev
= &pdev
->dev
;
1293 err
= tegra_dc_rgb_probe(dc
);
1294 if (err
< 0 && err
!= -ENODEV
) {
1295 dev_err(&pdev
->dev
, "failed to probe RGB output: %d\n", err
);
1299 err
= host1x_client_register(&dc
->client
);
1301 dev_err(&pdev
->dev
, "failed to register host1x client: %d\n",
1306 platform_set_drvdata(pdev
, dc
);
1311 static int tegra_dc_remove(struct platform_device
*pdev
)
1313 struct tegra_dc
*dc
= platform_get_drvdata(pdev
);
1316 err
= host1x_client_unregister(&dc
->client
);
1318 dev_err(&pdev
->dev
, "failed to unregister host1x client: %d\n",
1323 err
= tegra_dc_rgb_remove(dc
);
1325 dev_err(&pdev
->dev
, "failed to remove RGB output: %d\n", err
);
1329 clk_disable_unprepare(dc
->clk
);
1334 struct platform_driver tegra_dc_driver
= {
1337 .owner
= THIS_MODULE
,
1338 .of_match_table
= tegra_dc_of_match
,
1340 .probe
= tegra_dc_probe
,
1341 .remove
= tegra_dc_remove
,