drivers/gpu/drm/tegra/dpaux.c

   1 /*
   2  * Copyright (C) 2013 NVIDIA Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/gpio.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/of_gpio.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/reset.h>
  17 #include <linux/regulator/consumer.h>
  18 #include <linux/workqueue.h>
  19
  20 #include <drm/drm_dp_helper.h>
  21 #include <drm/drm_panel.h>
  22
  23 #include "dpaux.h"
  24 #include "drm.h"
  25
  26 static DEFINE_MUTEX(dpaux_lock);
  27 static LIST_HEAD(dpaux_list);
  28
  29 struct tegra_dpaux {
  30         struct drm_dp_aux aux;
  31         struct device *dev;
  32
  33         void __iomem *regs;
  34         int irq;
  35
  36         struct tegra_output *output;
  37
  38         struct reset_control *rst;
  39         struct clk *clk_parent;
  40         struct clk *clk;
  41
  42         struct regulator *vdd;
  43
  44         struct completion complete;
  45         struct work_struct work;
  46         struct list_head list;
  47 };
  48
  49 static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
  50 {
  51         return container_of(aux, struct tegra_dpaux, aux);
  52 }
  53
  54 static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
  55 {
  56         return container_of(work, struct tegra_dpaux, work);
  57 }
  58
  59 static inline unsigned long tegra_dpaux_readl(struct tegra_dpaux *dpaux,
  60                                               unsigned long offset)
  61 {
  62         return readl(dpaux->regs + (offset << 2));
  63 }
  64
  65 static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
  66                                       unsigned long value,
  67                                       unsigned long offset)
  68 {
  69         writel(value, dpaux->regs + (offset << 2));
  70 }
  71
  72 static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
  73                                    size_t size)
  74 {
  75         unsigned long offset = DPAUX_DP_AUXDATA_WRITE(0);
  76         size_t i, j;
  77
  78         for (i = 0; i < size; i += 4) {
  79                 size_t num = min_t(size_t, size - i, 4);
  80                 unsigned long value = 0;
  81
  82                 for (j = 0; j < num; j++)
  83                         value |= buffer[i + j] << (j * 8);
  84
  85                 tegra_dpaux_writel(dpaux, value, offset++);
  86         }
  87 }
  88
  89 static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
  90                                   size_t size)
  91 {
  92         unsigned long offset = DPAUX_DP_AUXDATA_READ(0);
  93         size_t i, j;
  94
  95         for (i = 0; i < size; i += 4) {
  96                 size_t num = min_t(size_t, size - i, 4);
  97                 unsigned long value;
  98
  99                 value = tegra_dpaux_readl(dpaux, offset++);
 100
 101                 for (j = 0; j < num; j++)
 102                         buffer[i + j] = value >> (j * 8);
 103         }
 104 }
 105
 106 static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
 107                                     struct drm_dp_aux_msg *msg)
 108 {
 109         unsigned long timeout = msecs_to_jiffies(250);
 110         struct tegra_dpaux *dpaux = to_dpaux(aux);
 111         unsigned long status;
 112         ssize_t ret = 0;
 113         u32 value;
 114
 115         /* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */
 116         if (msg->size > 16)
 117                 return -EINVAL;
 118
 119         /*
 120          * Allow zero-sized messages only for I2C, in which case they specify
 121          * address-only transactions.
 122          */
 123         if (msg->size < 1) {
 124                 switch (msg->request & ~DP_AUX_I2C_MOT) {
 125                 case DP_AUX_I2C_WRITE:
 126                 case DP_AUX_I2C_READ:
 127                         value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;
 128                         break;
 129
 130                 default:
 131                         return -EINVAL;
 132                 }
 133         } else {
 134                 /* For non-zero-sized messages, set the CMDLEN field. */
 135                 value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
 136         }
 137
 138         switch (msg->request & ~DP_AUX_I2C_MOT) {
 139         case DP_AUX_I2C_WRITE:
 140                 if (msg->request & DP_AUX_I2C_MOT)
 141                         value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;
 142                 else
 143                         value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;
 144
 145                 break;
 146
 147         case DP_AUX_I2C_READ:
 148                 if (msg->request & DP_AUX_I2C_MOT)
 149                         value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;
 150                 else
 151                         value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;
 152
 153                 break;
 154
 155         case DP_AUX_I2C_STATUS:
 156                 if (msg->request & DP_AUX_I2C_MOT)
 157                         value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;
 158                 else
 159                         value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;
 160
 161                 break;
 162
 163         case DP_AUX_NATIVE_WRITE:
 164                 value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;
 165                 break;
 166
 167         case DP_AUX_NATIVE_READ:
 168                 value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;
 169                 break;
 170
 171         default:
 172                 return -EINVAL;
 173         }
 174
 175         tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
 176         tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
 177
 178         if ((msg->request & DP_AUX_I2C_READ) == 0) {
 179                 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
 180                 ret = msg->size;
 181         }
 182
 183         /* start transaction */
 184         value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
 185         value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
 186         tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
 187
 188         status = wait_for_completion_timeout(&dpaux->complete, timeout);
 189         if (!status)
 190                 return -ETIMEDOUT;
 191
 192         /* read status and clear errors */
 193         value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
 194         tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
 195
 196         if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
 197                 return -ETIMEDOUT;
 198
 199         if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
 200             (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
 201             (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
 202                 return -EIO;
 203
 204         switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
 205         case 0x00:
 206                 msg->reply = DP_AUX_NATIVE_REPLY_ACK;
 207                 break;
 208
 209         case 0x01:
 210                 msg->reply = DP_AUX_NATIVE_REPLY_NACK;
 211                 break;
 212
 213         case 0x02:
 214                 msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
 215                 break;
 216
 217         case 0x04:
 218                 msg->reply = DP_AUX_I2C_REPLY_NACK;
 219                 break;
 220
 221         case 0x08:
 222                 msg->reply = DP_AUX_I2C_REPLY_DEFER;
 223                 break;
 224         }
 225
 226         if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) {
 227                 if (msg->request & DP_AUX_I2C_READ) {
 228                         size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
 229
 230                         if (WARN_ON(count != msg->size))
 231                                 count = min_t(size_t, count, msg->size);
 232
 233                         tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
 234                         ret = count;
 235                 }
 236         }
 237
 238         return ret;
 239 }
 240
 241 static void tegra_dpaux_hotplug(struct work_struct *work)
 242 {
 243         struct tegra_dpaux *dpaux = work_to_dpaux(work);
 244
 245         if (dpaux->output)
 246                 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
 247 }
 248
 249 static irqreturn_t tegra_dpaux_irq(int irq, void *data)
 250 {
 251         struct tegra_dpaux *dpaux = data;
 252         irqreturn_t ret = IRQ_HANDLED;
 253         unsigned long value;
 254
 255         /* clear interrupts */
 256         value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
 257         tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
 258
 259         if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))
 260                 schedule_work(&dpaux->work);
 261
 262         if (value & DPAUX_INTR_IRQ_EVENT) {
 263                 /* TODO: handle this */
 264         }
 265
 266         if (value & DPAUX_INTR_AUX_DONE)
 267                 complete(&dpaux->complete);
 268
 269         return ret;
 270 }
 271
 272 static int tegra_dpaux_probe(struct platform_device *pdev)
 273 {
 274         struct tegra_dpaux *dpaux;
 275         struct resource *regs;
 276         unsigned long value;
 277         int err;
 278
 279         dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
 280         if (!dpaux)
 281                 return -ENOMEM;
 282
 283         INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
 284         init_completion(&dpaux->complete);
 285         INIT_LIST_HEAD(&dpaux->list);
 286         dpaux->dev = &pdev->dev;
 287
 288         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 289         dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
 290         if (IS_ERR(dpaux->regs))
 291                 return PTR_ERR(dpaux->regs);
 292
 293         dpaux->irq = platform_get_irq(pdev, 0);
 294         if (dpaux->irq < 0) {
 295                 dev_err(&pdev->dev, "failed to get IRQ\n");
 296                 return -ENXIO;
 297         }
 298
 299         dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
 300         if (IS_ERR(dpaux->rst))
 301                 return PTR_ERR(dpaux->rst);
 302
 303         dpaux->clk = devm_clk_get(&pdev->dev, NULL);
 304         if (IS_ERR(dpaux->clk))
 305                 return PTR_ERR(dpaux->clk);
 306
 307         err = clk_prepare_enable(dpaux->clk);
 308         if (err < 0)
 309                 return err;
 310
 311         reset_control_deassert(dpaux->rst);
 312
 313         dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
 314         if (IS_ERR(dpaux->clk_parent))
 315                 return PTR_ERR(dpaux->clk_parent);
 316
 317         err = clk_prepare_enable(dpaux->clk_parent);
 318         if (err < 0)
 319                 return err;
 320
 321         err = clk_set_rate(dpaux->clk_parent, 270000000);
 322         if (err < 0) {
 323                 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
 324                         err);
 325                 return err;
 326         }
 327
 328         dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd");
 329         if (IS_ERR(dpaux->vdd))
 330                 return PTR_ERR(dpaux->vdd);
 331
 332         err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
 333                                dev_name(dpaux->dev), dpaux);
 334         if (err < 0) {
 335                 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
 336                         dpaux->irq, err);
 337                 return err;
 338         }
 339
 340         dpaux->aux.transfer = tegra_dpaux_transfer;
 341         dpaux->aux.dev = &pdev->dev;
 342
 343         err = drm_dp_aux_register(&dpaux->aux);
 344         if (err < 0)
 345                 return err;
 346
 347         /* enable and clear all interrupts */
 348         value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
 349                 DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
 350         tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
 351         tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
 352
 353         mutex_lock(&dpaux_lock);
 354         list_add_tail(&dpaux->list, &dpaux_list);
 355         mutex_unlock(&dpaux_lock);
 356
 357         platform_set_drvdata(pdev, dpaux);
 358
 359         return 0;
 360 }
 361
 362 static int tegra_dpaux_remove(struct platform_device *pdev)
 363 {
 364         struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
 365
 366         drm_dp_aux_unregister(&dpaux->aux);
 367
 368         mutex_lock(&dpaux_lock);
 369         list_del(&dpaux->list);
 370         mutex_unlock(&dpaux_lock);
 371
 372         cancel_work_sync(&dpaux->work);
 373
 374         clk_disable_unprepare(dpaux->clk_parent);
 375         reset_control_assert(dpaux->rst);
 376         clk_disable_unprepare(dpaux->clk);
 377
 378         return 0;
 379 }
 380
 381 static const struct of_device_id tegra_dpaux_of_match[] = {
 382         { .compatible = "nvidia,tegra124-dpaux", },
 383         { },
 384 };
 385 MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match);
 386
 387 struct platform_driver tegra_dpaux_driver = {
 388         .driver = {
 389                 .name = "tegra-dpaux",
 390                 .of_match_table = tegra_dpaux_of_match,
 391         },
 392         .probe = tegra_dpaux_probe,
 393         .remove = tegra_dpaux_remove,
 394 };
 395
 396 struct tegra_dpaux *tegra_dpaux_find_by_of_node(struct device_node *np)
 397 {
 398         struct tegra_dpaux *dpaux;
 399
 400         mutex_lock(&dpaux_lock);
 401
 402         list_for_each_entry(dpaux, &dpaux_list, list)
 403                 if (np == dpaux->dev->of_node) {
 404                         mutex_unlock(&dpaux_lock);
 405                         return dpaux;
 406                 }
 407
 408         mutex_unlock(&dpaux_lock);
 409
 410         return NULL;
 411 }
 412
 413 int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output)
 414 {
 415         unsigned long timeout;
 416         int err;
 417
 418         output->connector.polled = DRM_CONNECTOR_POLL_HPD;
 419         dpaux->output = output;
 420
 421         err = regulator_enable(dpaux->vdd);
 422         if (err < 0)
 423                 return err;
 424
 425         timeout = jiffies + msecs_to_jiffies(250);
 426
 427         while (time_before(jiffies, timeout)) {
 428                 enum drm_connector_status status;
 429
 430                 status = tegra_dpaux_detect(dpaux);
 431                 if (status == connector_status_connected)
 432                         return 0;
 433
 434                 usleep_range(1000, 2000);
 435         }
 436
 437         return -ETIMEDOUT;
 438 }
 439
 440 int tegra_dpaux_detach(struct tegra_dpaux *dpaux)
 441 {
 442         unsigned long timeout;
 443         int err;
 444
 445         err = regulator_disable(dpaux->vdd);
 446         if (err < 0)
 447                 return err;
 448
 449         timeout = jiffies + msecs_to_jiffies(250);
 450
 451         while (time_before(jiffies, timeout)) {
 452                 enum drm_connector_status status;
 453
 454                 status = tegra_dpaux_detect(dpaux);
 455                 if (status == connector_status_disconnected) {
 456                         dpaux->output = NULL;
 457                         return 0;
 458                 }
 459
 460                 usleep_range(1000, 2000);
 461         }
 462
 463         return -ETIMEDOUT;
 464 }
 465
 466 enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux)
 467 {
 468         unsigned long value;
 469
 470         value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
 471
 472         if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
 473                 return connector_status_connected;
 474
 475         return connector_status_disconnected;
 476 }
 477
 478 int tegra_dpaux_enable(struct tegra_dpaux *dpaux)
 479 {
 480         unsigned long value;
 481
 482         value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
 483                 DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
 484                 DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
 485                 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
 486                 DPAUX_HYBRID_PADCTL_MODE_AUX;
 487         tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
 488
 489         value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
 490         value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
 491         tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
 492
 493         return 0;
 494 }
 495
 496 int tegra_dpaux_disable(struct tegra_dpaux *dpaux)
 497 {
 498         unsigned long value;
 499
 500         value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
 501         value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
 502         tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
 503
 504         return 0;
 505 }
 506
 507 int tegra_dpaux_prepare(struct tegra_dpaux *dpaux, u8 encoding)
 508 {
 509         int err;
 510
 511         err = drm_dp_dpcd_writeb(&dpaux->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
 512                                  encoding);
 513         if (err < 0)
 514                 return err;
 515
 516         return 0;
 517 }
 518
 519 int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link,
 520                       u8 pattern)
 521 {
 522         u8 tp = pattern & DP_TRAINING_PATTERN_MASK;
 523         u8 status[DP_LINK_STATUS_SIZE], values[4];
 524         unsigned int i;
 525         int err;
 526
 527         err = drm_dp_dpcd_writeb(&dpaux->aux, DP_TRAINING_PATTERN_SET, pattern);
 528         if (err < 0)
 529                 return err;
 530
 531         if (tp == DP_TRAINING_PATTERN_DISABLE)
 532                 return 0;
 533
 534         for (i = 0; i < link->num_lanes; i++)
 535                 values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
 536                             DP_TRAIN_PRE_EMPHASIS_0 |
 537                             DP_TRAIN_MAX_SWING_REACHED |
 538                             DP_TRAIN_VOLTAGE_SWING_400;
 539
 540         err = drm_dp_dpcd_write(&dpaux->aux, DP_TRAINING_LANE0_SET, values,
 541                                 link->num_lanes);
 542         if (err < 0)
 543                 return err;
 544
 545         usleep_range(500, 1000);
 546
 547         err = drm_dp_dpcd_read_link_status(&dpaux->aux, status);
 548         if (err < 0)
 549                 return err;
 550
 551         switch (tp) {
 552         case DP_TRAINING_PATTERN_1:
 553                 if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
 554                         return -EAGAIN;
 555
 556                 break;
 557
 558         case DP_TRAINING_PATTERN_2:
 559                 if (!drm_dp_channel_eq_ok(status, link->num_lanes))
 560                         return -EAGAIN;
 561
 562                 break;
 563
 564         default:
 565                 dev_err(dpaux->dev, "unsupported training pattern %u\n", tp);
 566                 return -EINVAL;
 567         }
 568
 569         err = drm_dp_dpcd_writeb(&dpaux->aux, DP_EDP_CONFIGURATION_SET, 0);
 570         if (err < 0)
 571                 return err;
 572
 573         return 0;
 574 }