2 * Copyright (C) 2013 NVIDIA Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/debugfs.h>
11 #include <linux/host1x.h>
12 #include <linux/module.h>
14 #include <linux/of_platform.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/reset.h>
19 #include <linux/regulator/consumer.h>
21 #include <drm/drm_atomic_helper.h>
22 #include <drm/drm_mipi_dsi.h>
23 #include <drm/drm_panel.h>
25 #include <video/mipi_display.h>
32 struct tegra_dsi_state
{
33 struct drm_connector_state base
;
35 struct mipi_dphy_timing timing
;
38 unsigned int vrefresh
;
43 enum tegra_dsi_format format
;
48 static inline struct tegra_dsi_state
*
49 to_dsi_state(struct drm_connector_state
*state
)
51 return container_of(state
, struct tegra_dsi_state
, base
);
55 struct host1x_client client
;
56 struct tegra_output output
;
61 struct reset_control
*rst
;
62 struct clk
*clk_parent
;
66 struct drm_info_list
*debugfs_files
;
67 struct drm_minor
*minor
;
68 struct dentry
*debugfs
;
71 enum mipi_dsi_pixel_format format
;
74 struct tegra_mipi_device
*mipi
;
75 struct mipi_dsi_host host
;
77 struct regulator
*vdd
;
79 unsigned int video_fifo_depth
;
80 unsigned int host_fifo_depth
;
82 /* for ganged-mode support */
83 struct tegra_dsi
*master
;
84 struct tegra_dsi
*slave
;
87 static inline struct tegra_dsi
*
88 host1x_client_to_dsi(struct host1x_client
*client
)
90 return container_of(client
, struct tegra_dsi
, client
);
93 static inline struct tegra_dsi
*host_to_tegra(struct mipi_dsi_host
*host
)
95 return container_of(host
, struct tegra_dsi
, host
);
98 static inline struct tegra_dsi
*to_dsi(struct tegra_output
*output
)
100 return container_of(output
, struct tegra_dsi
, output
);
103 static struct tegra_dsi_state
*tegra_dsi_get_state(struct tegra_dsi
*dsi
)
105 return to_dsi_state(dsi
->output
.connector
.state
);
108 static inline u32
tegra_dsi_readl(struct tegra_dsi
*dsi
, unsigned long reg
)
110 return readl(dsi
->regs
+ (reg
<< 2));
113 static inline void tegra_dsi_writel(struct tegra_dsi
*dsi
, u32 value
,
116 writel(value
, dsi
->regs
+ (reg
<< 2));
119 static int tegra_dsi_show_regs(struct seq_file
*s
, void *data
)
121 struct drm_info_node
*node
= s
->private;
122 struct tegra_dsi
*dsi
= node
->info_ent
->data
;
123 struct drm_crtc
*crtc
= dsi
->output
.encoder
.crtc
;
124 struct drm_device
*drm
= node
->minor
->dev
;
127 drm_modeset_lock_all(drm
);
129 if (!crtc
|| !crtc
->state
->active
) {
134 #define DUMP_REG(name) \
135 seq_printf(s, "%-32s %#05x %08x\n", #name, name, \
136 tegra_dsi_readl(dsi, name))
138 DUMP_REG(DSI_INCR_SYNCPT
);
139 DUMP_REG(DSI_INCR_SYNCPT_CONTROL
);
140 DUMP_REG(DSI_INCR_SYNCPT_ERROR
);
142 DUMP_REG(DSI_RD_DATA
);
143 DUMP_REG(DSI_WR_DATA
);
144 DUMP_REG(DSI_POWER_CONTROL
);
145 DUMP_REG(DSI_INT_ENABLE
);
146 DUMP_REG(DSI_INT_STATUS
);
147 DUMP_REG(DSI_INT_MASK
);
148 DUMP_REG(DSI_HOST_CONTROL
);
149 DUMP_REG(DSI_CONTROL
);
150 DUMP_REG(DSI_SOL_DELAY
);
151 DUMP_REG(DSI_MAX_THRESHOLD
);
152 DUMP_REG(DSI_TRIGGER
);
153 DUMP_REG(DSI_TX_CRC
);
154 DUMP_REG(DSI_STATUS
);
156 DUMP_REG(DSI_INIT_SEQ_CONTROL
);
157 DUMP_REG(DSI_INIT_SEQ_DATA_0
);
158 DUMP_REG(DSI_INIT_SEQ_DATA_1
);
159 DUMP_REG(DSI_INIT_SEQ_DATA_2
);
160 DUMP_REG(DSI_INIT_SEQ_DATA_3
);
161 DUMP_REG(DSI_INIT_SEQ_DATA_4
);
162 DUMP_REG(DSI_INIT_SEQ_DATA_5
);
163 DUMP_REG(DSI_INIT_SEQ_DATA_6
);
164 DUMP_REG(DSI_INIT_SEQ_DATA_7
);
166 DUMP_REG(DSI_PKT_SEQ_0_LO
);
167 DUMP_REG(DSI_PKT_SEQ_0_HI
);
168 DUMP_REG(DSI_PKT_SEQ_1_LO
);
169 DUMP_REG(DSI_PKT_SEQ_1_HI
);
170 DUMP_REG(DSI_PKT_SEQ_2_LO
);
171 DUMP_REG(DSI_PKT_SEQ_2_HI
);
172 DUMP_REG(DSI_PKT_SEQ_3_LO
);
173 DUMP_REG(DSI_PKT_SEQ_3_HI
);
174 DUMP_REG(DSI_PKT_SEQ_4_LO
);
175 DUMP_REG(DSI_PKT_SEQ_4_HI
);
176 DUMP_REG(DSI_PKT_SEQ_5_LO
);
177 DUMP_REG(DSI_PKT_SEQ_5_HI
);
179 DUMP_REG(DSI_DCS_CMDS
);
181 DUMP_REG(DSI_PKT_LEN_0_1
);
182 DUMP_REG(DSI_PKT_LEN_2_3
);
183 DUMP_REG(DSI_PKT_LEN_4_5
);
184 DUMP_REG(DSI_PKT_LEN_6_7
);
186 DUMP_REG(DSI_PHY_TIMING_0
);
187 DUMP_REG(DSI_PHY_TIMING_1
);
188 DUMP_REG(DSI_PHY_TIMING_2
);
189 DUMP_REG(DSI_BTA_TIMING
);
191 DUMP_REG(DSI_TIMEOUT_0
);
192 DUMP_REG(DSI_TIMEOUT_1
);
193 DUMP_REG(DSI_TO_TALLY
);
195 DUMP_REG(DSI_PAD_CONTROL_0
);
196 DUMP_REG(DSI_PAD_CONTROL_CD
);
197 DUMP_REG(DSI_PAD_CD_STATUS
);
198 DUMP_REG(DSI_VIDEO_MODE_CONTROL
);
199 DUMP_REG(DSI_PAD_CONTROL_1
);
200 DUMP_REG(DSI_PAD_CONTROL_2
);
201 DUMP_REG(DSI_PAD_CONTROL_3
);
202 DUMP_REG(DSI_PAD_CONTROL_4
);
204 DUMP_REG(DSI_GANGED_MODE_CONTROL
);
205 DUMP_REG(DSI_GANGED_MODE_START
);
206 DUMP_REG(DSI_GANGED_MODE_SIZE
);
208 DUMP_REG(DSI_RAW_DATA_BYTE_COUNT
);
209 DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL
);
211 DUMP_REG(DSI_INIT_SEQ_DATA_8
);
212 DUMP_REG(DSI_INIT_SEQ_DATA_9
);
213 DUMP_REG(DSI_INIT_SEQ_DATA_10
);
214 DUMP_REG(DSI_INIT_SEQ_DATA_11
);
215 DUMP_REG(DSI_INIT_SEQ_DATA_12
);
216 DUMP_REG(DSI_INIT_SEQ_DATA_13
);
217 DUMP_REG(DSI_INIT_SEQ_DATA_14
);
218 DUMP_REG(DSI_INIT_SEQ_DATA_15
);
223 drm_modeset_unlock_all(drm
);
227 static struct drm_info_list debugfs_files
[] = {
228 { "regs", tegra_dsi_show_regs
, 0, NULL
},
231 static int tegra_dsi_debugfs_init(struct tegra_dsi
*dsi
,
232 struct drm_minor
*minor
)
234 const char *name
= dev_name(dsi
->dev
);
238 dsi
->debugfs
= debugfs_create_dir(name
, minor
->debugfs_root
);
242 dsi
->debugfs_files
= kmemdup(debugfs_files
, sizeof(debugfs_files
),
244 if (!dsi
->debugfs_files
) {
249 for (i
= 0; i
< ARRAY_SIZE(debugfs_files
); i
++)
250 dsi
->debugfs_files
[i
].data
= dsi
;
252 err
= drm_debugfs_create_files(dsi
->debugfs_files
,
253 ARRAY_SIZE(debugfs_files
),
254 dsi
->debugfs
, minor
);
263 kfree(dsi
->debugfs_files
);
264 dsi
->debugfs_files
= NULL
;
266 debugfs_remove(dsi
->debugfs
);
272 static void tegra_dsi_debugfs_exit(struct tegra_dsi
*dsi
)
274 drm_debugfs_remove_files(dsi
->debugfs_files
, ARRAY_SIZE(debugfs_files
),
278 kfree(dsi
->debugfs_files
);
279 dsi
->debugfs_files
= NULL
;
281 debugfs_remove(dsi
->debugfs
);
285 #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
286 #define PKT_LEN0(len) (((len) & 0x07) << 0)
287 #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
288 #define PKT_LEN1(len) (((len) & 0x07) << 10)
289 #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
290 #define PKT_LEN2(len) (((len) & 0x07) << 20)
292 #define PKT_LP (1 << 30)
293 #define NUM_PKT_SEQ 12
296 * non-burst mode with sync pulses
298 static const u32 pkt_seq_video_non_burst_sync_pulses
[NUM_PKT_SEQ
] = {
299 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START
) | PKT_LEN0(0) |
300 PKT_ID1(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN1(1) |
301 PKT_ID2(MIPI_DSI_H_SYNC_END
) | PKT_LEN2(0) |
304 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END
) | PKT_LEN0(0) |
305 PKT_ID1(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN1(1) |
306 PKT_ID2(MIPI_DSI_H_SYNC_END
) | PKT_LEN2(0) |
309 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START
) | PKT_LEN0(0) |
310 PKT_ID1(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN1(1) |
311 PKT_ID2(MIPI_DSI_H_SYNC_END
) | PKT_LEN2(0) |
314 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START
) | PKT_LEN0(0) |
315 PKT_ID1(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN1(1) |
316 PKT_ID2(MIPI_DSI_H_SYNC_END
) | PKT_LEN2(0),
317 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN0(2) |
318 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24
) | PKT_LEN1(3) |
319 PKT_ID2(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN2(4),
320 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START
) | PKT_LEN0(0) |
321 PKT_ID1(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN1(1) |
322 PKT_ID2(MIPI_DSI_H_SYNC_END
) | PKT_LEN2(0) |
325 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START
) | PKT_LEN0(0) |
326 PKT_ID1(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN1(1) |
327 PKT_ID2(MIPI_DSI_H_SYNC_END
) | PKT_LEN2(0),
328 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN0(2) |
329 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24
) | PKT_LEN1(3) |
330 PKT_ID2(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN2(4),
334 * non-burst mode with sync events
336 static const u32 pkt_seq_video_non_burst_sync_events
[NUM_PKT_SEQ
] = {
337 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START
) | PKT_LEN0(0) |
338 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION
) | PKT_LEN1(7) |
341 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START
) | PKT_LEN0(0) |
342 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION
) | PKT_LEN1(7) |
345 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START
) | PKT_LEN0(0) |
346 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION
) | PKT_LEN1(7) |
349 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START
) | PKT_LEN0(0) |
350 PKT_ID1(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN1(2) |
351 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24
) | PKT_LEN2(3),
352 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN0(4),
353 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START
) | PKT_LEN0(0) |
354 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION
) | PKT_LEN1(7) |
357 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START
) | PKT_LEN0(0) |
358 PKT_ID1(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN1(2) |
359 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24
) | PKT_LEN2(3),
360 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN0(4),
363 static const u32 pkt_seq_command_mode
[NUM_PKT_SEQ
] = {
370 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE
) | PKT_LEN0(3) | PKT_LP
,
374 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE
) | PKT_LEN0(5) | PKT_LP
,
378 static void tegra_dsi_set_phy_timing(struct tegra_dsi
*dsi
,
379 unsigned long period
,
380 const struct mipi_dphy_timing
*timing
)
384 value
= DSI_TIMING_FIELD(timing
->hsexit
, period
, 1) << 24 |
385 DSI_TIMING_FIELD(timing
->hstrail
, period
, 0) << 16 |
386 DSI_TIMING_FIELD(timing
->hszero
, period
, 3) << 8 |
387 DSI_TIMING_FIELD(timing
->hsprepare
, period
, 1);
388 tegra_dsi_writel(dsi
, value
, DSI_PHY_TIMING_0
);
390 value
= DSI_TIMING_FIELD(timing
->clktrail
, period
, 1) << 24 |
391 DSI_TIMING_FIELD(timing
->clkpost
, period
, 1) << 16 |
392 DSI_TIMING_FIELD(timing
->clkzero
, period
, 1) << 8 |
393 DSI_TIMING_FIELD(timing
->lpx
, period
, 1);
394 tegra_dsi_writel(dsi
, value
, DSI_PHY_TIMING_1
);
396 value
= DSI_TIMING_FIELD(timing
->clkprepare
, period
, 1) << 16 |
397 DSI_TIMING_FIELD(timing
->clkpre
, period
, 1) << 8 |
398 DSI_TIMING_FIELD(0xff * period
, period
, 0) << 0;
399 tegra_dsi_writel(dsi
, value
, DSI_PHY_TIMING_2
);
401 value
= DSI_TIMING_FIELD(timing
->taget
, period
, 1) << 16 |
402 DSI_TIMING_FIELD(timing
->tasure
, period
, 1) << 8 |
403 DSI_TIMING_FIELD(timing
->tago
, period
, 1);
404 tegra_dsi_writel(dsi
, value
, DSI_BTA_TIMING
);
407 tegra_dsi_set_phy_timing(dsi
->slave
, period
, timing
);
410 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format
,
411 unsigned int *mulp
, unsigned int *divp
)
414 case MIPI_DSI_FMT_RGB666_PACKED
:
415 case MIPI_DSI_FMT_RGB888
:
420 case MIPI_DSI_FMT_RGB565
:
425 case MIPI_DSI_FMT_RGB666
:
437 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format
,
438 enum tegra_dsi_format
*fmt
)
441 case MIPI_DSI_FMT_RGB888
:
442 *fmt
= TEGRA_DSI_FORMAT_24P
;
445 case MIPI_DSI_FMT_RGB666
:
446 *fmt
= TEGRA_DSI_FORMAT_18NP
;
449 case MIPI_DSI_FMT_RGB666_PACKED
:
450 *fmt
= TEGRA_DSI_FORMAT_18P
;
453 case MIPI_DSI_FMT_RGB565
:
454 *fmt
= TEGRA_DSI_FORMAT_16P
;
464 static void tegra_dsi_ganged_enable(struct tegra_dsi
*dsi
, unsigned int start
,
469 tegra_dsi_writel(dsi
, start
, DSI_GANGED_MODE_START
);
470 tegra_dsi_writel(dsi
, size
<< 16 | size
, DSI_GANGED_MODE_SIZE
);
472 value
= DSI_GANGED_MODE_CONTROL_ENABLE
;
473 tegra_dsi_writel(dsi
, value
, DSI_GANGED_MODE_CONTROL
);
476 static void tegra_dsi_enable(struct tegra_dsi
*dsi
)
480 value
= tegra_dsi_readl(dsi
, DSI_POWER_CONTROL
);
481 value
|= DSI_POWER_CONTROL_ENABLE
;
482 tegra_dsi_writel(dsi
, value
, DSI_POWER_CONTROL
);
485 tegra_dsi_enable(dsi
->slave
);
488 static unsigned int tegra_dsi_get_lanes(struct tegra_dsi
*dsi
)
491 return dsi
->master
->lanes
+ dsi
->lanes
;
494 return dsi
->lanes
+ dsi
->slave
->lanes
;
499 static void tegra_dsi_configure(struct tegra_dsi
*dsi
, unsigned int pipe
,
500 const struct drm_display_mode
*mode
)
502 unsigned int hact
, hsw
, hbp
, hfp
, i
, mul
, div
;
503 struct tegra_dsi_state
*state
;
507 /* XXX: pass in state into this function? */
509 state
= tegra_dsi_get_state(dsi
->master
);
511 state
= tegra_dsi_get_state(dsi
);
516 if (dsi
->flags
& MIPI_DSI_MODE_VIDEO_SYNC_PULSE
) {
517 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
518 pkt_seq
= pkt_seq_video_non_burst_sync_pulses
;
519 } else if (dsi
->flags
& MIPI_DSI_MODE_VIDEO
) {
520 DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
521 pkt_seq
= pkt_seq_video_non_burst_sync_events
;
523 DRM_DEBUG_KMS("Command mode\n");
524 pkt_seq
= pkt_seq_command_mode
;
527 value
= DSI_CONTROL_CHANNEL(0) |
528 DSI_CONTROL_FORMAT(state
->format
) |
529 DSI_CONTROL_LANES(dsi
->lanes
- 1) |
530 DSI_CONTROL_SOURCE(pipe
);
531 tegra_dsi_writel(dsi
, value
, DSI_CONTROL
);
533 tegra_dsi_writel(dsi
, dsi
->video_fifo_depth
, DSI_MAX_THRESHOLD
);
535 value
= DSI_HOST_CONTROL_HS
;
536 tegra_dsi_writel(dsi
, value
, DSI_HOST_CONTROL
);
538 value
= tegra_dsi_readl(dsi
, DSI_CONTROL
);
540 if (dsi
->flags
& MIPI_DSI_CLOCK_NON_CONTINUOUS
)
541 value
|= DSI_CONTROL_HS_CLK_CTRL
;
543 value
&= ~DSI_CONTROL_TX_TRIG(3);
545 /* enable DCS commands for command mode */
546 if (dsi
->flags
& MIPI_DSI_MODE_VIDEO
)
547 value
&= ~DSI_CONTROL_DCS_ENABLE
;
549 value
|= DSI_CONTROL_DCS_ENABLE
;
551 value
|= DSI_CONTROL_VIDEO_ENABLE
;
552 value
&= ~DSI_CONTROL_HOST_ENABLE
;
553 tegra_dsi_writel(dsi
, value
, DSI_CONTROL
);
555 for (i
= 0; i
< NUM_PKT_SEQ
; i
++)
556 tegra_dsi_writel(dsi
, pkt_seq
[i
], DSI_PKT_SEQ_0_LO
+ i
);
558 if (dsi
->flags
& MIPI_DSI_MODE_VIDEO
) {
559 /* horizontal active pixels */
560 hact
= mode
->hdisplay
* mul
/ div
;
562 /* horizontal sync width */
563 hsw
= (mode
->hsync_end
- mode
->hsync_start
) * mul
/ div
;
565 /* horizontal back porch */
566 hbp
= (mode
->htotal
- mode
->hsync_end
) * mul
/ div
;
568 if ((dsi
->flags
& MIPI_DSI_MODE_VIDEO_SYNC_PULSE
) == 0)
571 /* horizontal front porch */
572 hfp
= (mode
->hsync_start
- mode
->hdisplay
) * mul
/ div
;
574 /* subtract packet overhead */
579 tegra_dsi_writel(dsi
, hsw
<< 16 | 0, DSI_PKT_LEN_0_1
);
580 tegra_dsi_writel(dsi
, hact
<< 16 | hbp
, DSI_PKT_LEN_2_3
);
581 tegra_dsi_writel(dsi
, hfp
, DSI_PKT_LEN_4_5
);
582 tegra_dsi_writel(dsi
, 0x0f0f << 16, DSI_PKT_LEN_6_7
);
584 /* set SOL delay (for non-burst mode only) */
585 tegra_dsi_writel(dsi
, 8 * mul
/ div
, DSI_SOL_DELAY
);
587 /* TODO: implement ganged mode */
591 if (dsi
->master
|| dsi
->slave
) {
593 * For ganged mode, assume symmetric left-right mode.
595 bytes
= 1 + (mode
->hdisplay
/ 2) * mul
/ div
;
597 /* 1 byte (DCS command) + pixel data */
598 bytes
= 1 + mode
->hdisplay
* mul
/ div
;
601 tegra_dsi_writel(dsi
, 0, DSI_PKT_LEN_0_1
);
602 tegra_dsi_writel(dsi
, bytes
<< 16, DSI_PKT_LEN_2_3
);
603 tegra_dsi_writel(dsi
, bytes
<< 16, DSI_PKT_LEN_4_5
);
604 tegra_dsi_writel(dsi
, 0, DSI_PKT_LEN_6_7
);
606 value
= MIPI_DCS_WRITE_MEMORY_START
<< 8 |
607 MIPI_DCS_WRITE_MEMORY_CONTINUE
;
608 tegra_dsi_writel(dsi
, value
, DSI_DCS_CMDS
);
611 if (dsi
->master
|| dsi
->slave
) {
612 unsigned long delay
, bclk
, bclk_ganged
;
613 unsigned int lanes
= state
->lanes
;
615 /* SOL to valid, valid to FIFO and FIFO write delay */
617 delay
= DIV_ROUND_UP(delay
* mul
, div
* lanes
);
618 /* FIFO read delay */
621 bclk
= DIV_ROUND_UP(mode
->htotal
* mul
, div
* lanes
);
622 bclk_ganged
= DIV_ROUND_UP(bclk
* lanes
/ 2, lanes
);
623 value
= bclk
- bclk_ganged
+ delay
+ 20;
625 /* TODO: revisit for non-ganged mode */
626 value
= 8 * mul
/ div
;
629 tegra_dsi_writel(dsi
, value
, DSI_SOL_DELAY
);
633 tegra_dsi_configure(dsi
->slave
, pipe
, mode
);
636 * TODO: Support modes other than symmetrical left-right
639 tegra_dsi_ganged_enable(dsi
, 0, mode
->hdisplay
/ 2);
640 tegra_dsi_ganged_enable(dsi
->slave
, mode
->hdisplay
/ 2,
645 static int tegra_dsi_wait_idle(struct tegra_dsi
*dsi
, unsigned long timeout
)
649 timeout
= jiffies
+ msecs_to_jiffies(timeout
);
651 while (time_before(jiffies
, timeout
)) {
652 value
= tegra_dsi_readl(dsi
, DSI_STATUS
);
653 if (value
& DSI_STATUS_IDLE
)
656 usleep_range(1000, 2000);
662 static void tegra_dsi_video_disable(struct tegra_dsi
*dsi
)
666 value
= tegra_dsi_readl(dsi
, DSI_CONTROL
);
667 value
&= ~DSI_CONTROL_VIDEO_ENABLE
;
668 tegra_dsi_writel(dsi
, value
, DSI_CONTROL
);
671 tegra_dsi_video_disable(dsi
->slave
);
674 static void tegra_dsi_ganged_disable(struct tegra_dsi
*dsi
)
676 tegra_dsi_writel(dsi
, 0, DSI_GANGED_MODE_START
);
677 tegra_dsi_writel(dsi
, 0, DSI_GANGED_MODE_SIZE
);
678 tegra_dsi_writel(dsi
, 0, DSI_GANGED_MODE_CONTROL
);
681 static int tegra_dsi_pad_enable(struct tegra_dsi
*dsi
)
685 value
= DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
686 tegra_dsi_writel(dsi
, value
, DSI_PAD_CONTROL_0
);
691 static int tegra_dsi_pad_calibrate(struct tegra_dsi
*dsi
)
696 * XXX Is this still needed? The module reset is deasserted right
697 * before this function is called.
699 tegra_dsi_writel(dsi
, 0, DSI_PAD_CONTROL_0
);
700 tegra_dsi_writel(dsi
, 0, DSI_PAD_CONTROL_1
);
701 tegra_dsi_writel(dsi
, 0, DSI_PAD_CONTROL_2
);
702 tegra_dsi_writel(dsi
, 0, DSI_PAD_CONTROL_3
);
703 tegra_dsi_writel(dsi
, 0, DSI_PAD_CONTROL_4
);
705 /* start calibration */
706 tegra_dsi_pad_enable(dsi
);
708 value
= DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
709 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
710 DSI_PAD_OUT_CLK(0x0);
711 tegra_dsi_writel(dsi
, value
, DSI_PAD_CONTROL_2
);
713 value
= DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
714 DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
715 tegra_dsi_writel(dsi
, value
, DSI_PAD_CONTROL_3
);
717 return tegra_mipi_calibrate(dsi
->mipi
);
720 static void tegra_dsi_set_timeout(struct tegra_dsi
*dsi
, unsigned long bclk
,
721 unsigned int vrefresh
)
723 unsigned int timeout
;
726 /* one frame high-speed transmission timeout */
727 timeout
= (bclk
/ vrefresh
) / 512;
728 value
= DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout
);
729 tegra_dsi_writel(dsi
, value
, DSI_TIMEOUT_0
);
731 /* 2 ms peripheral timeout for panel */
732 timeout
= 2 * bclk
/ 512 * 1000;
733 value
= DSI_TIMEOUT_PR(timeout
) | DSI_TIMEOUT_TA(0x2000);
734 tegra_dsi_writel(dsi
, value
, DSI_TIMEOUT_1
);
736 value
= DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
737 tegra_dsi_writel(dsi
, value
, DSI_TO_TALLY
);
740 tegra_dsi_set_timeout(dsi
->slave
, bclk
, vrefresh
);
743 static void tegra_dsi_disable(struct tegra_dsi
*dsi
)
748 tegra_dsi_ganged_disable(dsi
->slave
);
749 tegra_dsi_ganged_disable(dsi
);
752 value
= tegra_dsi_readl(dsi
, DSI_POWER_CONTROL
);
753 value
&= ~DSI_POWER_CONTROL_ENABLE
;
754 tegra_dsi_writel(dsi
, value
, DSI_POWER_CONTROL
);
757 tegra_dsi_disable(dsi
->slave
);
759 usleep_range(5000, 10000);
762 static void tegra_dsi_soft_reset(struct tegra_dsi
*dsi
)
766 value
= tegra_dsi_readl(dsi
, DSI_POWER_CONTROL
);
767 value
&= ~DSI_POWER_CONTROL_ENABLE
;
768 tegra_dsi_writel(dsi
, value
, DSI_POWER_CONTROL
);
770 usleep_range(300, 1000);
772 value
= tegra_dsi_readl(dsi
, DSI_POWER_CONTROL
);
773 value
|= DSI_POWER_CONTROL_ENABLE
;
774 tegra_dsi_writel(dsi
, value
, DSI_POWER_CONTROL
);
776 usleep_range(300, 1000);
778 value
= tegra_dsi_readl(dsi
, DSI_TRIGGER
);
780 tegra_dsi_writel(dsi
, 0, DSI_TRIGGER
);
783 tegra_dsi_soft_reset(dsi
->slave
);
786 static void tegra_dsi_connector_reset(struct drm_connector
*connector
)
788 struct tegra_dsi_state
*state
= kzalloc(sizeof(*state
), GFP_KERNEL
);
793 if (connector
->state
) {
794 __drm_atomic_helper_connector_destroy_state(connector
->state
);
795 kfree(connector
->state
);
798 __drm_atomic_helper_connector_reset(connector
, &state
->base
);
801 static struct drm_connector_state
*
802 tegra_dsi_connector_duplicate_state(struct drm_connector
*connector
)
804 struct tegra_dsi_state
*state
= to_dsi_state(connector
->state
);
805 struct tegra_dsi_state
*copy
;
807 copy
= kmemdup(state
, sizeof(*state
), GFP_KERNEL
);
811 __drm_atomic_helper_connector_duplicate_state(connector
,
817 static const struct drm_connector_funcs tegra_dsi_connector_funcs
= {
818 .dpms
= drm_atomic_helper_connector_dpms
,
819 .reset
= tegra_dsi_connector_reset
,
820 .detect
= tegra_output_connector_detect
,
821 .fill_modes
= drm_helper_probe_single_connector_modes
,
822 .destroy
= tegra_output_connector_destroy
,
823 .atomic_duplicate_state
= tegra_dsi_connector_duplicate_state
,
824 .atomic_destroy_state
= drm_atomic_helper_connector_destroy_state
,
827 static enum drm_mode_status
828 tegra_dsi_connector_mode_valid(struct drm_connector
*connector
,
829 struct drm_display_mode
*mode
)
834 static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs
= {
835 .get_modes
= tegra_output_connector_get_modes
,
836 .mode_valid
= tegra_dsi_connector_mode_valid
,
839 static const struct drm_encoder_funcs tegra_dsi_encoder_funcs
= {
840 .destroy
= tegra_output_encoder_destroy
,
843 static void tegra_dsi_encoder_disable(struct drm_encoder
*encoder
)
845 struct tegra_output
*output
= encoder_to_output(encoder
);
846 struct tegra_dc
*dc
= to_tegra_dc(encoder
->crtc
);
847 struct tegra_dsi
*dsi
= to_dsi(output
);
852 drm_panel_disable(output
->panel
);
854 tegra_dsi_video_disable(dsi
);
857 * The following accesses registers of the display controller, so make
858 * sure it's only executed when the output is attached to one.
861 value
= tegra_dc_readl(dc
, DC_DISP_DISP_WIN_OPTIONS
);
862 value
&= ~DSI_ENABLE
;
863 tegra_dc_writel(dc
, value
, DC_DISP_DISP_WIN_OPTIONS
);
868 err
= tegra_dsi_wait_idle(dsi
, 100);
870 dev_dbg(dsi
->dev
, "failed to idle DSI: %d\n", err
);
872 tegra_dsi_soft_reset(dsi
);
875 drm_panel_unprepare(output
->panel
);
877 tegra_dsi_disable(dsi
);
879 pm_runtime_put(dsi
->dev
);
882 static void tegra_dsi_encoder_enable(struct drm_encoder
*encoder
)
884 struct drm_display_mode
*mode
= &encoder
->crtc
->state
->adjusted_mode
;
885 struct tegra_output
*output
= encoder_to_output(encoder
);
886 struct tegra_dc
*dc
= to_tegra_dc(encoder
->crtc
);
887 struct tegra_dsi
*dsi
= to_dsi(output
);
888 struct tegra_dsi_state
*state
;
892 pm_runtime_get_sync(dsi
->dev
);
894 err
= tegra_dsi_pad_calibrate(dsi
);
896 dev_err(dsi
->dev
, "MIPI calibration failed: %d\n", err
);
898 state
= tegra_dsi_get_state(dsi
);
900 tegra_dsi_set_timeout(dsi
, state
->bclk
, state
->vrefresh
);
903 * The D-PHY timing fields are expressed in byte-clock cycles, so
904 * multiply the period by 8.
906 tegra_dsi_set_phy_timing(dsi
, state
->period
* 8, &state
->timing
);
909 drm_panel_prepare(output
->panel
);
911 tegra_dsi_configure(dsi
, dc
->pipe
, mode
);
913 /* enable display controller */
914 value
= tegra_dc_readl(dc
, DC_DISP_DISP_WIN_OPTIONS
);
916 tegra_dc_writel(dc
, value
, DC_DISP_DISP_WIN_OPTIONS
);
920 /* enable DSI controller */
921 tegra_dsi_enable(dsi
);
924 drm_panel_enable(output
->panel
);
928 tegra_dsi_encoder_atomic_check(struct drm_encoder
*encoder
,
929 struct drm_crtc_state
*crtc_state
,
930 struct drm_connector_state
*conn_state
)
932 struct tegra_output
*output
= encoder_to_output(encoder
);
933 struct tegra_dsi_state
*state
= to_dsi_state(conn_state
);
934 struct tegra_dc
*dc
= to_tegra_dc(conn_state
->crtc
);
935 struct tegra_dsi
*dsi
= to_dsi(output
);
940 state
->pclk
= crtc_state
->mode
.clock
* 1000;
942 err
= tegra_dsi_get_muldiv(dsi
->format
, &state
->mul
, &state
->div
);
946 state
->lanes
= tegra_dsi_get_lanes(dsi
);
948 err
= tegra_dsi_get_format(dsi
->format
, &state
->format
);
952 state
->vrefresh
= drm_mode_vrefresh(&crtc_state
->mode
);
954 /* compute byte clock */
955 state
->bclk
= (state
->pclk
* state
->mul
) / (state
->div
* state
->lanes
);
957 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state
->mul
, state
->div
,
959 DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state
->format
,
961 DRM_DEBUG_KMS("bclk: %lu\n", state
->bclk
);
964 * Compute bit clock and round up to the next MHz.
966 plld
= DIV_ROUND_UP(state
->bclk
* 8, USEC_PER_SEC
) * USEC_PER_SEC
;
967 state
->period
= DIV_ROUND_CLOSEST(NSEC_PER_SEC
, plld
);
969 err
= mipi_dphy_timing_get_default(&state
->timing
, state
->period
);
973 err
= mipi_dphy_timing_validate(&state
->timing
, state
->period
);
975 dev_err(dsi
->dev
, "failed to validate D-PHY timing: %d\n", err
);
980 * We divide the frequency by two here, but we make up for that by
981 * setting the shift clock divider (further below) to half of the
987 * Derive pixel clock from bit clock using the shift clock divider.
988 * Note that this is only half of what we would expect, but we need
989 * that to make up for the fact that we divided the bit clock by a
990 * factor of two above.
992 * It's not clear exactly why this is necessary, but the display is
993 * not working properly otherwise. Perhaps the PLLs cannot generate
994 * frequencies sufficiently high.
996 scdiv
= ((8 * state
->mul
) / (state
->div
* state
->lanes
)) - 2;
998 err
= tegra_dc_state_setup_clock(dc
, crtc_state
, dsi
->clk_parent
,
1001 dev_err(output
->dev
, "failed to setup CRTC state: %d\n", err
);
1008 static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs
= {
1009 .disable
= tegra_dsi_encoder_disable
,
1010 .enable
= tegra_dsi_encoder_enable
,
1011 .atomic_check
= tegra_dsi_encoder_atomic_check
,
1014 static int tegra_dsi_init(struct host1x_client
*client
)
1016 struct drm_device
*drm
= dev_get_drvdata(client
->parent
);
1017 struct tegra_dsi
*dsi
= host1x_client_to_dsi(client
);
1020 /* Gangsters must not register their own outputs. */
1022 dsi
->output
.dev
= client
->dev
;
1024 drm_connector_init(drm
, &dsi
->output
.connector
,
1025 &tegra_dsi_connector_funcs
,
1026 DRM_MODE_CONNECTOR_DSI
);
1027 drm_connector_helper_add(&dsi
->output
.connector
,
1028 &tegra_dsi_connector_helper_funcs
);
1029 dsi
->output
.connector
.dpms
= DRM_MODE_DPMS_OFF
;
1031 drm_encoder_init(drm
, &dsi
->output
.encoder
,
1032 &tegra_dsi_encoder_funcs
,
1033 DRM_MODE_ENCODER_DSI
, NULL
);
1034 drm_encoder_helper_add(&dsi
->output
.encoder
,
1035 &tegra_dsi_encoder_helper_funcs
);
1037 drm_mode_connector_attach_encoder(&dsi
->output
.connector
,
1038 &dsi
->output
.encoder
);
1039 drm_connector_register(&dsi
->output
.connector
);
1041 err
= tegra_output_init(drm
, &dsi
->output
);
1043 dev_err(dsi
->dev
, "failed to initialize output: %d\n",
1046 dsi
->output
.encoder
.possible_crtcs
= 0x3;
1049 if (IS_ENABLED(CONFIG_DEBUG_FS
)) {
1050 err
= tegra_dsi_debugfs_init(dsi
, drm
->primary
);
1052 dev_err(dsi
->dev
, "debugfs setup failed: %d\n", err
);
1058 static int tegra_dsi_exit(struct host1x_client
*client
)
1060 struct tegra_dsi
*dsi
= host1x_client_to_dsi(client
);
1062 tegra_output_exit(&dsi
->output
);
1064 if (IS_ENABLED(CONFIG_DEBUG_FS
))
1065 tegra_dsi_debugfs_exit(dsi
);
1067 regulator_disable(dsi
->vdd
);
1072 static const struct host1x_client_ops dsi_client_ops
= {
1073 .init
= tegra_dsi_init
,
1074 .exit
= tegra_dsi_exit
,
1077 static int tegra_dsi_setup_clocks(struct tegra_dsi
*dsi
)
1082 parent
= clk_get_parent(dsi
->clk
);
1086 err
= clk_set_parent(parent
, dsi
->clk_parent
);
1093 static const char * const error_report
[16] = {
1097 "Escape Mode Entry Command Error",
1098 "Low-Power Transmit Sync Error",
1099 "Peripheral Timeout Error",
1100 "False Control Error",
1101 "Contention Detected",
1102 "ECC Error, single-bit",
1103 "ECC Error, multi-bit",
1105 "DSI Data Type Not Recognized",
1106 "DSI VC ID Invalid",
1107 "Invalid Transmission Length",
1109 "DSI Protocol Violation",
1112 static ssize_t
tegra_dsi_read_response(struct tegra_dsi
*dsi
,
1113 const struct mipi_dsi_msg
*msg
,
1116 u8
*rx
= msg
->rx_buf
;
1117 unsigned int i
, j
, k
;
1122 /* read and parse packet header */
1123 value
= tegra_dsi_readl(dsi
, DSI_RD_DATA
);
1125 switch (value
& 0x3f) {
1126 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT
:
1127 errors
= (value
>> 8) & 0xffff;
1128 dev_dbg(dsi
->dev
, "Acknowledge and error report: %04x\n",
1130 for (i
= 0; i
< ARRAY_SIZE(error_report
); i
++)
1131 if (errors
& BIT(i
))
1132 dev_dbg(dsi
->dev
, " %2u: %s\n", i
,
1136 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE
:
1137 rx
[0] = (value
>> 8) & 0xff;
1141 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE
:
1142 rx
[0] = (value
>> 8) & 0xff;
1143 rx
[1] = (value
>> 16) & 0xff;
1147 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE
:
1148 size
= ((value
>> 8) & 0xff00) | ((value
>> 8) & 0xff);
1151 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE
:
1152 size
= ((value
>> 8) & 0xff00) | ((value
>> 8) & 0xff);
1156 dev_err(dsi
->dev
, "unhandled response type: %02x\n",
1161 size
= min(size
, msg
->rx_len
);
1163 if (msg
->rx_buf
&& size
> 0) {
1164 for (i
= 0, j
= 0; i
< count
- 1; i
++, j
+= 4) {
1165 u8
*rx
= msg
->rx_buf
+ j
;
1167 value
= tegra_dsi_readl(dsi
, DSI_RD_DATA
);
1169 for (k
= 0; k
< 4 && (j
+ k
) < msg
->rx_len
; k
++)
1170 rx
[j
+ k
] = (value
>> (k
<< 3)) & 0xff;
1177 static int tegra_dsi_transmit(struct tegra_dsi
*dsi
, unsigned long timeout
)
1179 tegra_dsi_writel(dsi
, DSI_TRIGGER_HOST
, DSI_TRIGGER
);
1181 timeout
= jiffies
+ msecs_to_jiffies(timeout
);
1183 while (time_before(jiffies
, timeout
)) {
1184 u32 value
= tegra_dsi_readl(dsi
, DSI_TRIGGER
);
1185 if ((value
& DSI_TRIGGER_HOST
) == 0)
1188 usleep_range(1000, 2000);
1191 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
1195 static int tegra_dsi_wait_for_response(struct tegra_dsi
*dsi
,
1196 unsigned long timeout
)
1198 timeout
= jiffies
+ msecs_to_jiffies(250);
1200 while (time_before(jiffies
, timeout
)) {
1201 u32 value
= tegra_dsi_readl(dsi
, DSI_STATUS
);
1202 u8 count
= value
& 0x1f;
1207 usleep_range(1000, 2000);
1210 DRM_DEBUG_KMS("peripheral returned no data\n");
1214 static void tegra_dsi_writesl(struct tegra_dsi
*dsi
, unsigned long offset
,
1215 const void *buffer
, size_t size
)
1217 const u8
*buf
= buffer
;
1221 for (j
= 0; j
< size
; j
+= 4) {
1224 for (i
= 0; i
< 4 && j
+ i
< size
; i
++)
1225 value
|= buf
[j
+ i
] << (i
<< 3);
1227 tegra_dsi_writel(dsi
, value
, DSI_WR_DATA
);
1231 static ssize_t
tegra_dsi_host_transfer(struct mipi_dsi_host
*host
,
1232 const struct mipi_dsi_msg
*msg
)
1234 struct tegra_dsi
*dsi
= host_to_tegra(host
);
1235 struct mipi_dsi_packet packet
;
1241 err
= mipi_dsi_create_packet(&packet
, msg
);
1245 header
= packet
.header
;
1247 /* maximum FIFO depth is 1920 words */
1248 if (packet
.size
> dsi
->video_fifo_depth
* 4)
1251 /* reset underflow/overflow flags */
1252 value
= tegra_dsi_readl(dsi
, DSI_STATUS
);
1253 if (value
& (DSI_STATUS_UNDERFLOW
| DSI_STATUS_OVERFLOW
)) {
1254 value
= DSI_HOST_CONTROL_FIFO_RESET
;
1255 tegra_dsi_writel(dsi
, value
, DSI_HOST_CONTROL
);
1256 usleep_range(10, 20);
1259 value
= tegra_dsi_readl(dsi
, DSI_POWER_CONTROL
);
1260 value
|= DSI_POWER_CONTROL_ENABLE
;
1261 tegra_dsi_writel(dsi
, value
, DSI_POWER_CONTROL
);
1263 usleep_range(5000, 10000);
1265 value
= DSI_HOST_CONTROL_CRC_RESET
| DSI_HOST_CONTROL_TX_TRIG_HOST
|
1266 DSI_HOST_CONTROL_CS
| DSI_HOST_CONTROL_ECC
;
1268 if ((msg
->flags
& MIPI_DSI_MSG_USE_LPM
) == 0)
1269 value
|= DSI_HOST_CONTROL_HS
;
1272 * The host FIFO has a maximum of 64 words, so larger transmissions
1273 * need to use the video FIFO.
1275 if (packet
.size
> dsi
->host_fifo_depth
* 4)
1276 value
|= DSI_HOST_CONTROL_FIFO_SEL
;
1278 tegra_dsi_writel(dsi
, value
, DSI_HOST_CONTROL
);
1281 * For reads and messages with explicitly requested ACK, generate a
1282 * BTA sequence after the transmission of the packet.
1284 if ((msg
->flags
& MIPI_DSI_MSG_REQ_ACK
) ||
1285 (msg
->rx_buf
&& msg
->rx_len
> 0)) {
1286 value
= tegra_dsi_readl(dsi
, DSI_HOST_CONTROL
);
1287 value
|= DSI_HOST_CONTROL_PKT_BTA
;
1288 tegra_dsi_writel(dsi
, value
, DSI_HOST_CONTROL
);
1291 value
= DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE
;
1292 tegra_dsi_writel(dsi
, value
, DSI_CONTROL
);
1294 /* write packet header, ECC is generated by hardware */
1295 value
= header
[2] << 16 | header
[1] << 8 | header
[0];
1296 tegra_dsi_writel(dsi
, value
, DSI_WR_DATA
);
1298 /* write payload (if any) */
1299 if (packet
.payload_length
> 0)
1300 tegra_dsi_writesl(dsi
, DSI_WR_DATA
, packet
.payload
,
1301 packet
.payload_length
);
1303 err
= tegra_dsi_transmit(dsi
, 250);
1307 if ((msg
->flags
& MIPI_DSI_MSG_REQ_ACK
) ||
1308 (msg
->rx_buf
&& msg
->rx_len
> 0)) {
1309 err
= tegra_dsi_wait_for_response(dsi
, 250);
1315 value
= tegra_dsi_readl(dsi
, DSI_RD_DATA
);
1319 dev_dbg(dsi->dev, "ACK\n");
1325 dev_dbg(dsi->dev, "ESCAPE\n");
1330 dev_err(dsi
->dev
, "unknown status: %08x\n", value
);
1335 err
= tegra_dsi_read_response(dsi
, msg
, count
);
1338 "failed to parse response: %zd\n",
1342 * For read commands, return the number of
1343 * bytes returned by the peripheral.
1350 * For write commands, we have transmitted the 4-byte header
1351 * plus the variable-length payload.
1353 count
= 4 + packet
.payload_length
;
1359 static int tegra_dsi_ganged_setup(struct tegra_dsi
*dsi
)
1364 /* make sure both DSI controllers share the same PLL */
1365 parent
= clk_get_parent(dsi
->slave
->clk
);
1369 err
= clk_set_parent(parent
, dsi
->clk_parent
);
1376 static int tegra_dsi_host_attach(struct mipi_dsi_host
*host
,
1377 struct mipi_dsi_device
*device
)
1379 struct tegra_dsi
*dsi
= host_to_tegra(host
);
1381 dsi
->flags
= device
->mode_flags
;
1382 dsi
->format
= device
->format
;
1383 dsi
->lanes
= device
->lanes
;
1388 dev_dbg(dsi
->dev
, "attaching dual-channel device %s\n",
1389 dev_name(&device
->dev
));
1391 err
= tegra_dsi_ganged_setup(dsi
);
1393 dev_err(dsi
->dev
, "failed to set up ganged mode: %d\n",
1400 * Slaves don't have a panel associated with them, so they provide
1401 * merely the second channel.
1404 struct tegra_output
*output
= &dsi
->output
;
1406 output
->panel
= of_drm_find_panel(device
->dev
.of_node
);
1407 if (output
->panel
&& output
->connector
.dev
) {
1408 drm_panel_attach(output
->panel
, &output
->connector
);
1409 drm_helper_hpd_irq_event(output
->connector
.dev
);
1416 static int tegra_dsi_host_detach(struct mipi_dsi_host
*host
,
1417 struct mipi_dsi_device
*device
)
1419 struct tegra_dsi
*dsi
= host_to_tegra(host
);
1420 struct tegra_output
*output
= &dsi
->output
;
1422 if (output
->panel
&& &device
->dev
== output
->panel
->dev
) {
1423 output
->panel
= NULL
;
1425 if (output
->connector
.dev
)
1426 drm_helper_hpd_irq_event(output
->connector
.dev
);
1432 static const struct mipi_dsi_host_ops tegra_dsi_host_ops
= {
1433 .attach
= tegra_dsi_host_attach
,
1434 .detach
= tegra_dsi_host_detach
,
1435 .transfer
= tegra_dsi_host_transfer
,
1438 static int tegra_dsi_ganged_probe(struct tegra_dsi
*dsi
)
1440 struct device_node
*np
;
1442 np
= of_parse_phandle(dsi
->dev
->of_node
, "nvidia,ganged-mode", 0);
1444 struct platform_device
*gangster
= of_find_device_by_node(np
);
1446 dsi
->slave
= platform_get_drvdata(gangster
);
1450 return -EPROBE_DEFER
;
1452 dsi
->slave
->master
= dsi
;
1458 static int tegra_dsi_probe(struct platform_device
*pdev
)
1460 struct tegra_dsi
*dsi
;
1461 struct resource
*regs
;
1464 dsi
= devm_kzalloc(&pdev
->dev
, sizeof(*dsi
), GFP_KERNEL
);
1468 dsi
->output
.dev
= dsi
->dev
= &pdev
->dev
;
1469 dsi
->video_fifo_depth
= 1920;
1470 dsi
->host_fifo_depth
= 64;
1472 err
= tegra_dsi_ganged_probe(dsi
);
1476 err
= tegra_output_probe(&dsi
->output
);
1480 dsi
->output
.connector
.polled
= DRM_CONNECTOR_POLL_HPD
;
1483 * Assume these values by default. When a DSI peripheral driver
1484 * attaches to the DSI host, the parameters will be taken from
1485 * the attached device.
1487 dsi
->flags
= MIPI_DSI_MODE_VIDEO
;
1488 dsi
->format
= MIPI_DSI_FMT_RGB888
;
1491 if (!pdev
->dev
.pm_domain
) {
1492 dsi
->rst
= devm_reset_control_get(&pdev
->dev
, "dsi");
1493 if (IS_ERR(dsi
->rst
))
1494 return PTR_ERR(dsi
->rst
);
1497 dsi
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1498 if (IS_ERR(dsi
->clk
)) {
1499 dev_err(&pdev
->dev
, "cannot get DSI clock\n");
1500 return PTR_ERR(dsi
->clk
);
1503 dsi
->clk_lp
= devm_clk_get(&pdev
->dev
, "lp");
1504 if (IS_ERR(dsi
->clk_lp
)) {
1505 dev_err(&pdev
->dev
, "cannot get low-power clock\n");
1506 return PTR_ERR(dsi
->clk_lp
);
1509 dsi
->clk_parent
= devm_clk_get(&pdev
->dev
, "parent");
1510 if (IS_ERR(dsi
->clk_parent
)) {
1511 dev_err(&pdev
->dev
, "cannot get parent clock\n");
1512 return PTR_ERR(dsi
->clk_parent
);
1515 dsi
->vdd
= devm_regulator_get(&pdev
->dev
, "avdd-dsi-csi");
1516 if (IS_ERR(dsi
->vdd
)) {
1517 dev_err(&pdev
->dev
, "cannot get VDD supply\n");
1518 return PTR_ERR(dsi
->vdd
);
1521 err
= tegra_dsi_setup_clocks(dsi
);
1523 dev_err(&pdev
->dev
, "cannot setup clocks\n");
1527 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1528 dsi
->regs
= devm_ioremap_resource(&pdev
->dev
, regs
);
1529 if (IS_ERR(dsi
->regs
))
1530 return PTR_ERR(dsi
->regs
);
1532 dsi
->mipi
= tegra_mipi_request(&pdev
->dev
);
1533 if (IS_ERR(dsi
->mipi
))
1534 return PTR_ERR(dsi
->mipi
);
1536 dsi
->host
.ops
= &tegra_dsi_host_ops
;
1537 dsi
->host
.dev
= &pdev
->dev
;
1539 err
= mipi_dsi_host_register(&dsi
->host
);
1541 dev_err(&pdev
->dev
, "failed to register DSI host: %d\n", err
);
1545 platform_set_drvdata(pdev
, dsi
);
1546 pm_runtime_enable(&pdev
->dev
);
1548 INIT_LIST_HEAD(&dsi
->client
.list
);
1549 dsi
->client
.ops
= &dsi_client_ops
;
1550 dsi
->client
.dev
= &pdev
->dev
;
1552 err
= host1x_client_register(&dsi
->client
);
1554 dev_err(&pdev
->dev
, "failed to register host1x client: %d\n",
1562 mipi_dsi_host_unregister(&dsi
->host
);
1564 tegra_mipi_free(dsi
->mipi
);
1568 static int tegra_dsi_remove(struct platform_device
*pdev
)
1570 struct tegra_dsi
*dsi
= platform_get_drvdata(pdev
);
1573 pm_runtime_disable(&pdev
->dev
);
1575 err
= host1x_client_unregister(&dsi
->client
);
1577 dev_err(&pdev
->dev
, "failed to unregister host1x client: %d\n",
1582 tegra_output_remove(&dsi
->output
);
1584 mipi_dsi_host_unregister(&dsi
->host
);
1585 tegra_mipi_free(dsi
->mipi
);
1591 static int tegra_dsi_suspend(struct device
*dev
)
1593 struct tegra_dsi
*dsi
= dev_get_drvdata(dev
);
1597 err
= reset_control_assert(dsi
->rst
);
1599 dev_err(dev
, "failed to assert reset: %d\n", err
);
1604 usleep_range(1000, 2000);
1606 clk_disable_unprepare(dsi
->clk_lp
);
1607 clk_disable_unprepare(dsi
->clk
);
1609 regulator_disable(dsi
->vdd
);
1614 static int tegra_dsi_resume(struct device
*dev
)
1616 struct tegra_dsi
*dsi
= dev_get_drvdata(dev
);
1619 err
= regulator_enable(dsi
->vdd
);
1621 dev_err(dsi
->dev
, "failed to enable VDD supply: %d\n", err
);
1625 err
= clk_prepare_enable(dsi
->clk
);
1627 dev_err(dev
, "cannot enable DSI clock: %d\n", err
);
1631 err
= clk_prepare_enable(dsi
->clk_lp
);
1633 dev_err(dev
, "cannot enable low-power clock: %d\n", err
);
1637 usleep_range(1000, 2000);
1640 err
= reset_control_deassert(dsi
->rst
);
1642 dev_err(dev
, "cannot assert reset: %d\n", err
);
1643 goto disable_clk_lp
;
1650 clk_disable_unprepare(dsi
->clk_lp
);
1652 clk_disable_unprepare(dsi
->clk
);
1654 regulator_disable(dsi
->vdd
);
1659 static const struct dev_pm_ops tegra_dsi_pm_ops
= {
1660 SET_RUNTIME_PM_OPS(tegra_dsi_suspend
, tegra_dsi_resume
, NULL
)
1663 static const struct of_device_id tegra_dsi_of_match
[] = {
1664 { .compatible
= "nvidia,tegra210-dsi", },
1665 { .compatible
= "nvidia,tegra132-dsi", },
1666 { .compatible
= "nvidia,tegra124-dsi", },
1667 { .compatible
= "nvidia,tegra114-dsi", },
1670 MODULE_DEVICE_TABLE(of
, tegra_dsi_of_match
);
1672 struct platform_driver tegra_dsi_driver
= {
1674 .name
= "tegra-dsi",
1675 .of_match_table
= tegra_dsi_of_match
,
1676 .pm
= &tegra_dsi_pm_ops
,
1678 .probe
= tegra_dsi_probe
,
1679 .remove
= tegra_dsi_remove
,