2 * Copyright (C) 2013 NVIDIA Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/debugfs.h>
11 #include <linux/host1x.h>
12 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/reset.h>
17 #include <linux/regulator/consumer.h>
19 #include <drm/drm_mipi_dsi.h>
20 #include <drm/drm_panel.h>
22 #include <video/mipi_display.h>
30 struct host1x_client client
;
31 struct tegra_output output
;
36 struct reset_control
*rst
;
37 struct clk
*clk_parent
;
41 struct drm_info_list
*debugfs_files
;
42 struct drm_minor
*minor
;
43 struct dentry
*debugfs
;
46 enum mipi_dsi_pixel_format format
;
49 struct tegra_mipi_device
*mipi
;
50 struct mipi_dsi_host host
;
52 struct regulator
*vdd
;
55 unsigned int video_fifo_depth
;
56 unsigned int host_fifo_depth
;
59 static inline struct tegra_dsi
*
60 host1x_client_to_dsi(struct host1x_client
*client
)
62 return container_of(client
, struct tegra_dsi
, client
);
65 static inline struct tegra_dsi
*host_to_tegra(struct mipi_dsi_host
*host
)
67 return container_of(host
, struct tegra_dsi
, host
);
70 static inline struct tegra_dsi
*to_dsi(struct tegra_output
*output
)
72 return container_of(output
, struct tegra_dsi
, output
);
75 static inline unsigned long tegra_dsi_readl(struct tegra_dsi
*dsi
,
78 return readl(dsi
->regs
+ (reg
<< 2));
81 static inline void tegra_dsi_writel(struct tegra_dsi
*dsi
, unsigned long value
,
84 writel(value
, dsi
->regs
+ (reg
<< 2));
87 static int tegra_dsi_show_regs(struct seq_file
*s
, void *data
)
89 struct drm_info_node
*node
= s
->private;
90 struct tegra_dsi
*dsi
= node
->info_ent
->data
;
92 #define DUMP_REG(name) \
93 seq_printf(s, "%-32s %#05x %08lx\n", #name, name, \
94 tegra_dsi_readl(dsi, name))
96 DUMP_REG(DSI_INCR_SYNCPT
);
97 DUMP_REG(DSI_INCR_SYNCPT_CONTROL
);
98 DUMP_REG(DSI_INCR_SYNCPT_ERROR
);
100 DUMP_REG(DSI_RD_DATA
);
101 DUMP_REG(DSI_WR_DATA
);
102 DUMP_REG(DSI_POWER_CONTROL
);
103 DUMP_REG(DSI_INT_ENABLE
);
104 DUMP_REG(DSI_INT_STATUS
);
105 DUMP_REG(DSI_INT_MASK
);
106 DUMP_REG(DSI_HOST_CONTROL
);
107 DUMP_REG(DSI_CONTROL
);
108 DUMP_REG(DSI_SOL_DELAY
);
109 DUMP_REG(DSI_MAX_THRESHOLD
);
110 DUMP_REG(DSI_TRIGGER
);
111 DUMP_REG(DSI_TX_CRC
);
112 DUMP_REG(DSI_STATUS
);
114 DUMP_REG(DSI_INIT_SEQ_CONTROL
);
115 DUMP_REG(DSI_INIT_SEQ_DATA_0
);
116 DUMP_REG(DSI_INIT_SEQ_DATA_1
);
117 DUMP_REG(DSI_INIT_SEQ_DATA_2
);
118 DUMP_REG(DSI_INIT_SEQ_DATA_3
);
119 DUMP_REG(DSI_INIT_SEQ_DATA_4
);
120 DUMP_REG(DSI_INIT_SEQ_DATA_5
);
121 DUMP_REG(DSI_INIT_SEQ_DATA_6
);
122 DUMP_REG(DSI_INIT_SEQ_DATA_7
);
124 DUMP_REG(DSI_PKT_SEQ_0_LO
);
125 DUMP_REG(DSI_PKT_SEQ_0_HI
);
126 DUMP_REG(DSI_PKT_SEQ_1_LO
);
127 DUMP_REG(DSI_PKT_SEQ_1_HI
);
128 DUMP_REG(DSI_PKT_SEQ_2_LO
);
129 DUMP_REG(DSI_PKT_SEQ_2_HI
);
130 DUMP_REG(DSI_PKT_SEQ_3_LO
);
131 DUMP_REG(DSI_PKT_SEQ_3_HI
);
132 DUMP_REG(DSI_PKT_SEQ_4_LO
);
133 DUMP_REG(DSI_PKT_SEQ_4_HI
);
134 DUMP_REG(DSI_PKT_SEQ_5_LO
);
135 DUMP_REG(DSI_PKT_SEQ_5_HI
);
137 DUMP_REG(DSI_DCS_CMDS
);
139 DUMP_REG(DSI_PKT_LEN_0_1
);
140 DUMP_REG(DSI_PKT_LEN_2_3
);
141 DUMP_REG(DSI_PKT_LEN_4_5
);
142 DUMP_REG(DSI_PKT_LEN_6_7
);
144 DUMP_REG(DSI_PHY_TIMING_0
);
145 DUMP_REG(DSI_PHY_TIMING_1
);
146 DUMP_REG(DSI_PHY_TIMING_2
);
147 DUMP_REG(DSI_BTA_TIMING
);
149 DUMP_REG(DSI_TIMEOUT_0
);
150 DUMP_REG(DSI_TIMEOUT_1
);
151 DUMP_REG(DSI_TO_TALLY
);
153 DUMP_REG(DSI_PAD_CONTROL_0
);
154 DUMP_REG(DSI_PAD_CONTROL_CD
);
155 DUMP_REG(DSI_PAD_CD_STATUS
);
156 DUMP_REG(DSI_VIDEO_MODE_CONTROL
);
157 DUMP_REG(DSI_PAD_CONTROL_1
);
158 DUMP_REG(DSI_PAD_CONTROL_2
);
159 DUMP_REG(DSI_PAD_CONTROL_3
);
160 DUMP_REG(DSI_PAD_CONTROL_4
);
162 DUMP_REG(DSI_GANGED_MODE_CONTROL
);
163 DUMP_REG(DSI_GANGED_MODE_START
);
164 DUMP_REG(DSI_GANGED_MODE_SIZE
);
166 DUMP_REG(DSI_RAW_DATA_BYTE_COUNT
);
167 DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL
);
169 DUMP_REG(DSI_INIT_SEQ_DATA_8
);
170 DUMP_REG(DSI_INIT_SEQ_DATA_9
);
171 DUMP_REG(DSI_INIT_SEQ_DATA_10
);
172 DUMP_REG(DSI_INIT_SEQ_DATA_11
);
173 DUMP_REG(DSI_INIT_SEQ_DATA_12
);
174 DUMP_REG(DSI_INIT_SEQ_DATA_13
);
175 DUMP_REG(DSI_INIT_SEQ_DATA_14
);
176 DUMP_REG(DSI_INIT_SEQ_DATA_15
);
183 static struct drm_info_list debugfs_files
[] = {
184 { "regs", tegra_dsi_show_regs
, 0, NULL
},
187 static int tegra_dsi_debugfs_init(struct tegra_dsi
*dsi
,
188 struct drm_minor
*minor
)
190 const char *name
= dev_name(dsi
->dev
);
194 dsi
->debugfs
= debugfs_create_dir(name
, minor
->debugfs_root
);
198 dsi
->debugfs_files
= kmemdup(debugfs_files
, sizeof(debugfs_files
),
200 if (!dsi
->debugfs_files
) {
205 for (i
= 0; i
< ARRAY_SIZE(debugfs_files
); i
++)
206 dsi
->debugfs_files
[i
].data
= dsi
;
208 err
= drm_debugfs_create_files(dsi
->debugfs_files
,
209 ARRAY_SIZE(debugfs_files
),
210 dsi
->debugfs
, minor
);
219 kfree(dsi
->debugfs_files
);
220 dsi
->debugfs_files
= NULL
;
222 debugfs_remove(dsi
->debugfs
);
228 static int tegra_dsi_debugfs_exit(struct tegra_dsi
*dsi
)
230 drm_debugfs_remove_files(dsi
->debugfs_files
, ARRAY_SIZE(debugfs_files
),
234 kfree(dsi
->debugfs_files
);
235 dsi
->debugfs_files
= NULL
;
237 debugfs_remove(dsi
->debugfs
);
243 #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
244 #define PKT_LEN0(len) (((len) & 0x07) << 0)
245 #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
246 #define PKT_LEN1(len) (((len) & 0x07) << 10)
247 #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
248 #define PKT_LEN2(len) (((len) & 0x07) << 20)
250 #define PKT_LP (1 << 30)
251 #define NUM_PKT_SEQ 12
254 * non-burst mode with sync pulses
256 static const u32 pkt_seq_video_non_burst_sync_pulses
[NUM_PKT_SEQ
] = {
257 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START
) | PKT_LEN0(0) |
258 PKT_ID1(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN1(1) |
259 PKT_ID2(MIPI_DSI_H_SYNC_END
) | PKT_LEN2(0) |
262 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END
) | PKT_LEN0(0) |
263 PKT_ID1(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN1(1) |
264 PKT_ID2(MIPI_DSI_H_SYNC_END
) | PKT_LEN2(0) |
267 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START
) | PKT_LEN0(0) |
268 PKT_ID1(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN1(1) |
269 PKT_ID2(MIPI_DSI_H_SYNC_END
) | PKT_LEN2(0) |
272 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START
) | PKT_LEN0(0) |
273 PKT_ID1(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN1(1) |
274 PKT_ID2(MIPI_DSI_H_SYNC_END
) | PKT_LEN2(0),
275 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN0(2) |
276 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24
) | PKT_LEN1(3) |
277 PKT_ID2(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN2(4),
278 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START
) | PKT_LEN0(0) |
279 PKT_ID1(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN1(1) |
280 PKT_ID2(MIPI_DSI_H_SYNC_END
) | PKT_LEN2(0) |
283 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START
) | PKT_LEN0(0) |
284 PKT_ID1(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN1(1) |
285 PKT_ID2(MIPI_DSI_H_SYNC_END
) | PKT_LEN2(0),
286 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN0(2) |
287 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24
) | PKT_LEN1(3) |
288 PKT_ID2(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN2(4),
292 * non-burst mode with sync events
294 static const u32 pkt_seq_video_non_burst_sync_events
[NUM_PKT_SEQ
] = {
295 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START
) | PKT_LEN0(0) |
296 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION
) | PKT_LEN1(7) |
299 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START
) | PKT_LEN0(0) |
300 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION
) | PKT_LEN1(7) |
303 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START
) | PKT_LEN0(0) |
304 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION
) | PKT_LEN1(7) |
307 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START
) | PKT_LEN0(0) |
308 PKT_ID1(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN1(2) |
309 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24
) | PKT_LEN2(3),
310 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN0(4),
311 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START
) | PKT_LEN0(0) |
312 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION
) | PKT_LEN1(7) |
315 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START
) | PKT_LEN0(0) |
316 PKT_ID1(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN1(2) |
317 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24
) | PKT_LEN2(3),
318 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET
) | PKT_LEN0(4),
321 static int tegra_dsi_set_phy_timing(struct tegra_dsi
*dsi
)
323 struct mipi_dphy_timing timing
;
324 unsigned long value
, period
;
328 rate
= clk_get_rate(dsi
->clk
);
332 period
= DIV_ROUND_CLOSEST(1000000000UL, rate
* 2);
334 err
= mipi_dphy_timing_get_default(&timing
, period
);
338 err
= mipi_dphy_timing_validate(&timing
, period
);
340 dev_err(dsi
->dev
, "failed to validate D-PHY timing: %d\n", err
);
345 * The D-PHY timing fields below are expressed in byte-clock cycles,
346 * so multiply the period by 8.
350 value
= DSI_TIMING_FIELD(timing
.hsexit
, period
, 1) << 24 |
351 DSI_TIMING_FIELD(timing
.hstrail
, period
, 0) << 16 |
352 DSI_TIMING_FIELD(timing
.hszero
, period
, 3) << 8 |
353 DSI_TIMING_FIELD(timing
.hsprepare
, period
, 1);
354 tegra_dsi_writel(dsi
, value
, DSI_PHY_TIMING_0
);
356 value
= DSI_TIMING_FIELD(timing
.clktrail
, period
, 1) << 24 |
357 DSI_TIMING_FIELD(timing
.clkpost
, period
, 1) << 16 |
358 DSI_TIMING_FIELD(timing
.clkzero
, period
, 1) << 8 |
359 DSI_TIMING_FIELD(timing
.lpx
, period
, 1);
360 tegra_dsi_writel(dsi
, value
, DSI_PHY_TIMING_1
);
362 value
= DSI_TIMING_FIELD(timing
.clkprepare
, period
, 1) << 16 |
363 DSI_TIMING_FIELD(timing
.clkpre
, period
, 1) << 8 |
364 DSI_TIMING_FIELD(0xff * period
, period
, 0) << 0;
365 tegra_dsi_writel(dsi
, value
, DSI_PHY_TIMING_2
);
367 value
= DSI_TIMING_FIELD(timing
.taget
, period
, 1) << 16 |
368 DSI_TIMING_FIELD(timing
.tasure
, period
, 1) << 8 |
369 DSI_TIMING_FIELD(timing
.tago
, period
, 1);
370 tegra_dsi_writel(dsi
, value
, DSI_BTA_TIMING
);
375 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format
,
376 unsigned int *mulp
, unsigned int *divp
)
379 case MIPI_DSI_FMT_RGB666_PACKED
:
380 case MIPI_DSI_FMT_RGB888
:
385 case MIPI_DSI_FMT_RGB565
:
390 case MIPI_DSI_FMT_RGB666
:
402 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format
,
403 enum tegra_dsi_format
*fmt
)
406 case MIPI_DSI_FMT_RGB888
:
407 *fmt
= TEGRA_DSI_FORMAT_24P
;
410 case MIPI_DSI_FMT_RGB666
:
411 *fmt
= TEGRA_DSI_FORMAT_18NP
;
414 case MIPI_DSI_FMT_RGB666_PACKED
:
415 *fmt
= TEGRA_DSI_FORMAT_18P
;
418 case MIPI_DSI_FMT_RGB565
:
419 *fmt
= TEGRA_DSI_FORMAT_16P
;
429 static int tegra_output_dsi_enable(struct tegra_output
*output
)
431 struct tegra_dc
*dc
= to_tegra_dc(output
->encoder
.crtc
);
432 struct drm_display_mode
*mode
= &dc
->base
.mode
;
433 unsigned int hact
, hsw
, hbp
, hfp
, i
, mul
, div
;
434 struct tegra_dsi
*dsi
= to_dsi(output
);
435 enum tegra_dsi_format format
;
443 if (dsi
->flags
& MIPI_DSI_MODE_VIDEO_SYNC_PULSE
) {
444 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
445 pkt_seq
= pkt_seq_video_non_burst_sync_pulses
;
447 DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
448 pkt_seq
= pkt_seq_video_non_burst_sync_events
;
451 err
= tegra_dsi_get_muldiv(dsi
->format
, &mul
, &div
);
455 err
= tegra_dsi_get_format(dsi
->format
, &format
);
459 value
= DSI_CONTROL_CHANNEL(0) | DSI_CONTROL_FORMAT(format
) |
460 DSI_CONTROL_LANES(dsi
->lanes
- 1) |
461 DSI_CONTROL_SOURCE(dc
->pipe
);
462 tegra_dsi_writel(dsi
, value
, DSI_CONTROL
);
464 tegra_dsi_writel(dsi
, dsi
->video_fifo_depth
, DSI_MAX_THRESHOLD
);
466 value
= DSI_HOST_CONTROL_HS
| DSI_HOST_CONTROL_CS
|
467 DSI_HOST_CONTROL_ECC
;
468 tegra_dsi_writel(dsi
, value
, DSI_HOST_CONTROL
);
470 value
= tegra_dsi_readl(dsi
, DSI_CONTROL
);
471 if (dsi
->flags
& MIPI_DSI_CLOCK_NON_CONTINUOUS
)
472 value
|= DSI_CONTROL_HS_CLK_CTRL
;
473 value
&= ~DSI_CONTROL_TX_TRIG(3);
474 value
&= ~DSI_CONTROL_DCS_ENABLE
;
475 value
|= DSI_CONTROL_VIDEO_ENABLE
;
476 value
&= ~DSI_CONTROL_HOST_ENABLE
;
477 tegra_dsi_writel(dsi
, value
, DSI_CONTROL
);
479 err
= tegra_dsi_set_phy_timing(dsi
);
483 for (i
= 0; i
< NUM_PKT_SEQ
; i
++)
484 tegra_dsi_writel(dsi
, pkt_seq
[i
], DSI_PKT_SEQ_0_LO
+ i
);
486 /* horizontal active pixels */
487 hact
= mode
->hdisplay
* mul
/ div
;
489 /* horizontal sync width */
490 hsw
= (mode
->hsync_end
- mode
->hsync_start
) * mul
/ div
;
493 /* horizontal back porch */
494 hbp
= (mode
->htotal
- mode
->hsync_end
) * mul
/ div
;
497 /* horizontal front porch */
498 hfp
= (mode
->hsync_start
- mode
->hdisplay
) * mul
/ div
;
501 tegra_dsi_writel(dsi
, hsw
<< 16 | 0, DSI_PKT_LEN_0_1
);
502 tegra_dsi_writel(dsi
, hact
<< 16 | hbp
, DSI_PKT_LEN_2_3
);
503 tegra_dsi_writel(dsi
, hfp
, DSI_PKT_LEN_4_5
);
504 tegra_dsi_writel(dsi
, 0x0f0f << 16, DSI_PKT_LEN_6_7
);
507 tegra_dsi_writel(dsi
, 8 * mul
/ div
, DSI_SOL_DELAY
);
509 /* enable display controller */
510 value
= tegra_dc_readl(dc
, DC_DISP_DISP_WIN_OPTIONS
);
512 tegra_dc_writel(dc
, value
, DC_DISP_DISP_WIN_OPTIONS
);
514 value
= tegra_dc_readl(dc
, DC_CMD_DISPLAY_COMMAND
);
515 value
&= ~DISP_CTRL_MODE_MASK
;
516 value
|= DISP_CTRL_MODE_C_DISPLAY
;
517 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_COMMAND
);
519 value
= tegra_dc_readl(dc
, DC_CMD_DISPLAY_POWER_CONTROL
);
520 value
|= PW0_ENABLE
| PW1_ENABLE
| PW2_ENABLE
| PW3_ENABLE
|
521 PW4_ENABLE
| PM0_ENABLE
| PM1_ENABLE
;
522 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_POWER_CONTROL
);
524 tegra_dc_writel(dc
, GENERAL_ACT_REQ
<< 8, DC_CMD_STATE_CONTROL
);
525 tegra_dc_writel(dc
, GENERAL_ACT_REQ
, DC_CMD_STATE_CONTROL
);
527 /* enable DSI controller */
528 value
= tegra_dsi_readl(dsi
, DSI_POWER_CONTROL
);
529 value
|= DSI_POWER_CONTROL_ENABLE
;
530 tegra_dsi_writel(dsi
, value
, DSI_POWER_CONTROL
);
537 static int tegra_output_dsi_disable(struct tegra_output
*output
)
539 struct tegra_dc
*dc
= to_tegra_dc(output
->encoder
.crtc
);
540 struct tegra_dsi
*dsi
= to_dsi(output
);
546 /* disable DSI controller */
547 value
= tegra_dsi_readl(dsi
, DSI_POWER_CONTROL
);
548 value
&= ~DSI_POWER_CONTROL_ENABLE
;
549 tegra_dsi_writel(dsi
, value
, DSI_POWER_CONTROL
);
552 * The following accesses registers of the display controller, so make
553 * sure it's only executed when the output is attached to one.
556 value
= tegra_dc_readl(dc
, DC_CMD_DISPLAY_POWER_CONTROL
);
557 value
&= ~(PW0_ENABLE
| PW1_ENABLE
| PW2_ENABLE
| PW3_ENABLE
|
558 PW4_ENABLE
| PM0_ENABLE
| PM1_ENABLE
);
559 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_POWER_CONTROL
);
561 value
= tegra_dc_readl(dc
, DC_CMD_DISPLAY_COMMAND
);
562 value
&= ~DISP_CTRL_MODE_MASK
;
563 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_COMMAND
);
565 value
= tegra_dc_readl(dc
, DC_DISP_DISP_WIN_OPTIONS
);
566 value
&= ~DSI_ENABLE
;
567 tegra_dc_writel(dc
, value
, DC_DISP_DISP_WIN_OPTIONS
);
569 tegra_dc_writel(dc
, GENERAL_ACT_REQ
<< 8, DC_CMD_STATE_CONTROL
);
570 tegra_dc_writel(dc
, GENERAL_ACT_REQ
, DC_CMD_STATE_CONTROL
);
573 dsi
->enabled
= false;
578 static int tegra_output_dsi_setup_clock(struct tegra_output
*output
,
579 struct clk
*clk
, unsigned long pclk
,
582 struct tegra_dc
*dc
= to_tegra_dc(output
->encoder
.crtc
);
583 struct drm_display_mode
*mode
= &dc
->base
.mode
;
584 unsigned int timeout
, mul
, div
, vrefresh
;
585 struct tegra_dsi
*dsi
= to_dsi(output
);
586 unsigned long bclk
, plld
, value
;
589 err
= tegra_dsi_get_muldiv(dsi
->format
, &mul
, &div
);
593 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", mul
, div
, dsi
->lanes
);
594 vrefresh
= drm_mode_vrefresh(mode
);
595 DRM_DEBUG_KMS("vrefresh: %u\n", vrefresh
);
597 /* compute byte clock */
598 bclk
= (pclk
* mul
) / (div
* dsi
->lanes
);
601 * Compute bit clock and round up to the next MHz.
603 plld
= DIV_ROUND_UP(bclk
* 8, 1000000) * 1000000;
606 * We divide the frequency by two here, but we make up for that by
607 * setting the shift clock divider (further below) to half of the
612 err
= clk_set_parent(clk
, dsi
->clk_parent
);
614 dev_err(dsi
->dev
, "failed to set parent clock: %d\n", err
);
618 err
= clk_set_rate(dsi
->clk_parent
, plld
);
620 dev_err(dsi
->dev
, "failed to set base clock rate to %lu Hz\n",
626 * Derive pixel clock from bit clock using the shift clock divider.
627 * Note that this is only half of what we would expect, but we need
628 * that to make up for the fact that we divided the bit clock by a
629 * factor of two above.
631 * It's not clear exactly why this is necessary, but the display is
632 * not working properly otherwise. Perhaps the PLLs cannot generate
633 * frequencies sufficiently high.
635 *divp
= ((8 * mul
) / (div
* dsi
->lanes
)) - 2;
638 * XXX: Move the below somewhere else so that we don't need to have
639 * access to the vrefresh in this function?
642 /* one frame high-speed transmission timeout */
643 timeout
= (bclk
/ vrefresh
) / 512;
644 value
= DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout
);
645 tegra_dsi_writel(dsi
, value
, DSI_TIMEOUT_0
);
647 /* 2 ms peripheral timeout for panel */
648 timeout
= 2 * bclk
/ 512 * 1000;
649 value
= DSI_TIMEOUT_PR(timeout
) | DSI_TIMEOUT_TA(0x2000);
650 tegra_dsi_writel(dsi
, value
, DSI_TIMEOUT_1
);
652 value
= DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
653 tegra_dsi_writel(dsi
, value
, DSI_TO_TALLY
);
658 static int tegra_output_dsi_check_mode(struct tegra_output
*output
,
659 struct drm_display_mode
*mode
,
660 enum drm_mode_status
*status
)
663 * FIXME: For now, always assume that the mode is okay.
671 static const struct tegra_output_ops dsi_ops
= {
672 .enable
= tegra_output_dsi_enable
,
673 .disable
= tegra_output_dsi_disable
,
674 .setup_clock
= tegra_output_dsi_setup_clock
,
675 .check_mode
= tegra_output_dsi_check_mode
,
678 static int tegra_dsi_pad_enable(struct tegra_dsi
*dsi
)
682 value
= DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
683 tegra_dsi_writel(dsi
, value
, DSI_PAD_CONTROL_0
);
688 static int tegra_dsi_pad_calibrate(struct tegra_dsi
*dsi
)
692 tegra_dsi_writel(dsi
, 0, DSI_PAD_CONTROL_0
);
693 tegra_dsi_writel(dsi
, 0, DSI_PAD_CONTROL_1
);
694 tegra_dsi_writel(dsi
, 0, DSI_PAD_CONTROL_2
);
695 tegra_dsi_writel(dsi
, 0, DSI_PAD_CONTROL_3
);
696 tegra_dsi_writel(dsi
, 0, DSI_PAD_CONTROL_4
);
698 /* start calibration */
699 tegra_dsi_pad_enable(dsi
);
701 value
= DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
702 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
703 DSI_PAD_OUT_CLK(0x0);
704 tegra_dsi_writel(dsi
, value
, DSI_PAD_CONTROL_2
);
706 return tegra_mipi_calibrate(dsi
->mipi
);
709 static int tegra_dsi_init(struct host1x_client
*client
)
711 struct drm_device
*drm
= dev_get_drvdata(client
->parent
);
712 struct tegra_dsi
*dsi
= host1x_client_to_dsi(client
);
715 dsi
->output
.type
= TEGRA_OUTPUT_DSI
;
716 dsi
->output
.dev
= client
->dev
;
717 dsi
->output
.ops
= &dsi_ops
;
719 err
= tegra_output_init(drm
, &dsi
->output
);
721 dev_err(client
->dev
, "output setup failed: %d\n", err
);
725 if (IS_ENABLED(CONFIG_DEBUG_FS
)) {
726 err
= tegra_dsi_debugfs_init(dsi
, drm
->primary
);
728 dev_err(dsi
->dev
, "debugfs setup failed: %d\n", err
);
734 static int tegra_dsi_exit(struct host1x_client
*client
)
736 struct tegra_dsi
*dsi
= host1x_client_to_dsi(client
);
739 if (IS_ENABLED(CONFIG_DEBUG_FS
)) {
740 err
= tegra_dsi_debugfs_exit(dsi
);
742 dev_err(dsi
->dev
, "debugfs cleanup failed: %d\n", err
);
745 err
= tegra_output_disable(&dsi
->output
);
747 dev_err(client
->dev
, "output failed to disable: %d\n", err
);
751 err
= tegra_output_exit(&dsi
->output
);
753 dev_err(client
->dev
, "output cleanup failed: %d\n", err
);
760 static const struct host1x_client_ops dsi_client_ops
= {
761 .init
= tegra_dsi_init
,
762 .exit
= tegra_dsi_exit
,
765 static int tegra_dsi_setup_clocks(struct tegra_dsi
*dsi
)
770 parent
= clk_get_parent(dsi
->clk
);
774 err
= clk_set_parent(parent
, dsi
->clk_parent
);
781 static int tegra_dsi_host_attach(struct mipi_dsi_host
*host
,
782 struct mipi_dsi_device
*device
)
784 struct tegra_dsi
*dsi
= host_to_tegra(host
);
785 struct tegra_output
*output
= &dsi
->output
;
787 dsi
->flags
= device
->mode_flags
;
788 dsi
->format
= device
->format
;
789 dsi
->lanes
= device
->lanes
;
791 output
->panel
= of_drm_find_panel(device
->dev
.of_node
);
793 if (output
->connector
.dev
)
794 drm_helper_hpd_irq_event(output
->connector
.dev
);
800 static int tegra_dsi_host_detach(struct mipi_dsi_host
*host
,
801 struct mipi_dsi_device
*device
)
803 struct tegra_dsi
*dsi
= host_to_tegra(host
);
804 struct tegra_output
*output
= &dsi
->output
;
806 if (output
->panel
&& &device
->dev
== output
->panel
->dev
) {
807 output
->panel
= NULL
;
809 if (output
->connector
.dev
)
810 drm_helper_hpd_irq_event(output
->connector
.dev
);
816 static const struct mipi_dsi_host_ops tegra_dsi_host_ops
= {
817 .attach
= tegra_dsi_host_attach
,
818 .detach
= tegra_dsi_host_detach
,
821 static int tegra_dsi_probe(struct platform_device
*pdev
)
823 struct tegra_dsi
*dsi
;
824 struct resource
*regs
;
827 dsi
= devm_kzalloc(&pdev
->dev
, sizeof(*dsi
), GFP_KERNEL
);
831 dsi
->output
.dev
= dsi
->dev
= &pdev
->dev
;
832 dsi
->video_fifo_depth
= 1920;
833 dsi
->host_fifo_depth
= 64;
835 err
= tegra_output_probe(&dsi
->output
);
839 dsi
->output
.connector
.polled
= DRM_CONNECTOR_POLL_HPD
;
842 * Assume these values by default. When a DSI peripheral driver
843 * attaches to the DSI host, the parameters will be taken from
844 * the attached device.
846 dsi
->flags
= MIPI_DSI_MODE_VIDEO
;
847 dsi
->format
= MIPI_DSI_FMT_RGB888
;
850 dsi
->rst
= devm_reset_control_get(&pdev
->dev
, "dsi");
851 if (IS_ERR(dsi
->rst
))
852 return PTR_ERR(dsi
->rst
);
854 err
= reset_control_deassert(dsi
->rst
);
856 dev_err(&pdev
->dev
, "failed to bring DSI out of reset: %d\n",
861 dsi
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
862 if (IS_ERR(dsi
->clk
)) {
863 dev_err(&pdev
->dev
, "cannot get DSI clock\n");
864 err
= PTR_ERR(dsi
->clk
);
868 err
= clk_prepare_enable(dsi
->clk
);
870 dev_err(&pdev
->dev
, "cannot enable DSI clock\n");
874 dsi
->clk_lp
= devm_clk_get(&pdev
->dev
, "lp");
875 if (IS_ERR(dsi
->clk_lp
)) {
876 dev_err(&pdev
->dev
, "cannot get low-power clock\n");
877 err
= PTR_ERR(dsi
->clk_lp
);
881 err
= clk_prepare_enable(dsi
->clk_lp
);
883 dev_err(&pdev
->dev
, "cannot enable low-power clock\n");
887 dsi
->clk_parent
= devm_clk_get(&pdev
->dev
, "parent");
888 if (IS_ERR(dsi
->clk_parent
)) {
889 dev_err(&pdev
->dev
, "cannot get parent clock\n");
890 err
= PTR_ERR(dsi
->clk_parent
);
894 dsi
->vdd
= devm_regulator_get(&pdev
->dev
, "avdd-dsi-csi");
895 if (IS_ERR(dsi
->vdd
)) {
896 dev_err(&pdev
->dev
, "cannot get VDD supply\n");
897 err
= PTR_ERR(dsi
->vdd
);
901 err
= regulator_enable(dsi
->vdd
);
903 dev_err(&pdev
->dev
, "cannot enable VDD supply\n");
907 err
= tegra_dsi_setup_clocks(dsi
);
909 dev_err(&pdev
->dev
, "cannot setup clocks\n");
913 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
914 dsi
->regs
= devm_ioremap_resource(&pdev
->dev
, regs
);
915 if (IS_ERR(dsi
->regs
)) {
916 err
= PTR_ERR(dsi
->regs
);
920 dsi
->mipi
= tegra_mipi_request(&pdev
->dev
);
921 if (IS_ERR(dsi
->mipi
)) {
922 err
= PTR_ERR(dsi
->mipi
);
926 err
= tegra_dsi_pad_calibrate(dsi
);
928 dev_err(dsi
->dev
, "MIPI calibration failed: %d\n", err
);
932 dsi
->host
.ops
= &tegra_dsi_host_ops
;
933 dsi
->host
.dev
= &pdev
->dev
;
935 err
= mipi_dsi_host_register(&dsi
->host
);
937 dev_err(&pdev
->dev
, "failed to register DSI host: %d\n", err
);
941 INIT_LIST_HEAD(&dsi
->client
.list
);
942 dsi
->client
.ops
= &dsi_client_ops
;
943 dsi
->client
.dev
= &pdev
->dev
;
945 err
= host1x_client_register(&dsi
->client
);
947 dev_err(&pdev
->dev
, "failed to register host1x client: %d\n",
952 platform_set_drvdata(pdev
, dsi
);
957 mipi_dsi_host_unregister(&dsi
->host
);
959 tegra_mipi_free(dsi
->mipi
);
961 regulator_disable(dsi
->vdd
);
963 clk_disable_unprepare(dsi
->clk_lp
);
965 clk_disable_unprepare(dsi
->clk
);
967 reset_control_assert(dsi
->rst
);
971 static int tegra_dsi_remove(struct platform_device
*pdev
)
973 struct tegra_dsi
*dsi
= platform_get_drvdata(pdev
);
976 err
= host1x_client_unregister(&dsi
->client
);
978 dev_err(&pdev
->dev
, "failed to unregister host1x client: %d\n",
983 mipi_dsi_host_unregister(&dsi
->host
);
984 tegra_mipi_free(dsi
->mipi
);
986 regulator_disable(dsi
->vdd
);
987 clk_disable_unprepare(dsi
->clk_lp
);
988 clk_disable_unprepare(dsi
->clk
);
989 reset_control_assert(dsi
->rst
);
991 err
= tegra_output_remove(&dsi
->output
);
993 dev_err(&pdev
->dev
, "failed to remove output: %d\n", err
);
1000 static const struct of_device_id tegra_dsi_of_match
[] = {
1001 { .compatible
= "nvidia,tegra114-dsi", },
1004 MODULE_DEVICE_TABLE(of
, tegra_dsi_of_match
);
1006 struct platform_driver tegra_dsi_driver
= {
1008 .name
= "tegra-dsi",
1009 .of_match_table
= tegra_dsi_of_match
,
1011 .probe
= tegra_dsi_probe
,
1012 .remove
= tegra_dsi_remove
,