projects / deliverable / linux.git / blob
? search:


e67083e510a0690d6db68b405738f7c6c1709375
[deliverable/linux.git] / drivers / gpu / drm / tegra / hdmi.c
1 /*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/hdmi.h>
13 #include <linux/regulator/consumer.h>
14 #include <linux/reset.h>
15
16 #include "hdmi.h"
17 #include "drm.h"
18 #include "dc.h"
19
20 struct tmds_config {
21 unsigned int pclk;
22 u32 pll0;
23 u32 pll1;
24 u32 pe_current;
25 u32 drive_current;
26 u32 peak_current;
27 };
28
29 struct tegra_hdmi_config {
30 const struct tmds_config *tmds;
31 unsigned int num_tmds;
32
33 unsigned long fuse_override_offset;
34 unsigned long fuse_override_value;
35
36 bool has_sor_io_peak_current;
37 };
38
39 struct tegra_hdmi {
40 struct host1x_client client;
41 struct tegra_output output;
42 struct device *dev;
43 bool enabled;
44
45 struct regulator *hdmi;
46 struct regulator *pll;
47 struct regulator *vdd;
48
49 void __iomem *regs;
50 unsigned int irq;
51
52 struct clk *clk_parent;
53 struct clk *clk;
54 struct reset_control *rst;
55
56 const struct tegra_hdmi_config *config;
57
58 unsigned int audio_source;
59 unsigned int audio_freq;
60 bool stereo;
61 bool dvi;
62
63 struct drm_info_list *debugfs_files;
64 struct drm_minor *minor;
65 struct dentry *debugfs;
66 };
67
68 static inline struct tegra_hdmi *
69 host1x_client_to_hdmi(struct host1x_client *client)
70 {
71 return container_of(client, struct tegra_hdmi, client);
72 }
73
74 static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
75 {
76 return container_of(output, struct tegra_hdmi, output);
77 }
78
79 #define HDMI_AUDIOCLK_FREQ 216000000
80 #define HDMI_REKEY_DEFAULT 56
81
82 enum {
83 AUTO = 0,
84 SPDIF,
85 HDA,
86 };
87
88 static inline unsigned long tegra_hdmi_readl(struct tegra_hdmi *hdmi,
89 unsigned long reg)
90 {
91 return readl(hdmi->regs + (reg << 2));
92 }
93
94 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, unsigned long val,
95 unsigned long reg)
96 {
97 writel(val, hdmi->regs + (reg << 2));
98 }
99
100 struct tegra_hdmi_audio_config {
101 unsigned int pclk;
102 unsigned int n;
103 unsigned int cts;
104 unsigned int aval;
105 };
106
107 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
108 { 25200000, 4096, 25200, 24000 },
109 { 27000000, 4096, 27000, 24000 },
110 { 74250000, 4096, 74250, 24000 },
111 { 148500000, 4096, 148500, 24000 },
112 { 0, 0, 0, 0 },
113 };
114
115 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
116 { 25200000, 5880, 26250, 25000 },
117 { 27000000, 5880, 28125, 25000 },
118 { 74250000, 4704, 61875, 20000 },
119 { 148500000, 4704, 123750, 20000 },
120 { 0, 0, 0, 0 },
121 };
122
123 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
124 { 25200000, 6144, 25200, 24000 },
125 { 27000000, 6144, 27000, 24000 },
126 { 74250000, 6144, 74250, 24000 },
127 { 148500000, 6144, 148500, 24000 },
128 { 0, 0, 0, 0 },
129 };
130
131 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
132 { 25200000, 11760, 26250, 25000 },
133 { 27000000, 11760, 28125, 25000 },
134 { 74250000, 9408, 61875, 20000 },
135 { 148500000, 9408, 123750, 20000 },
136 { 0, 0, 0, 0 },
137 };
138
139 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
140 { 25200000, 12288, 25200, 24000 },
141 { 27000000, 12288, 27000, 24000 },
142 { 74250000, 12288, 74250, 24000 },
143 { 148500000, 12288, 148500, 24000 },
144 { 0, 0, 0, 0 },
145 };
146
147 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
148 { 25200000, 23520, 26250, 25000 },
149 { 27000000, 23520, 28125, 25000 },
150 { 74250000, 18816, 61875, 20000 },
151 { 148500000, 18816, 123750, 20000 },
152 { 0, 0, 0, 0 },
153 };
154
155 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
156 { 25200000, 24576, 25200, 24000 },
157 { 27000000, 24576, 27000, 24000 },
158 { 74250000, 24576, 74250, 24000 },
159 { 148500000, 24576, 148500, 24000 },
160 { 0, 0, 0, 0 },
161 };
162
163 static const struct tmds_config tegra20_tmds_config[] = {
164 { /* slow pixel clock modes */
165 .pclk = 27000000,
166 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
167 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
168 SOR_PLL_TX_REG_LOAD(3),
169 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
170 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
171 PE_CURRENT1(PE_CURRENT_0_0_mA) |
172 PE_CURRENT2(PE_CURRENT_0_0_mA) |
173 PE_CURRENT3(PE_CURRENT_0_0_mA),
174 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
175 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
176 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
177 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
178 },
179 { /* high pixel clock modes */
180 .pclk = UINT_MAX,
181 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
182 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
183 SOR_PLL_TX_REG_LOAD(3),
184 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
185 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
186 PE_CURRENT1(PE_CURRENT_6_0_mA) |
187 PE_CURRENT2(PE_CURRENT_6_0_mA) |
188 PE_CURRENT3(PE_CURRENT_6_0_mA),
189 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
190 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
191 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
192 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
193 },
194 };
195
196 static const struct tmds_config tegra30_tmds_config[] = {
197 { /* 480p modes */
198 .pclk = 27000000,
199 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
200 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
201 SOR_PLL_TX_REG_LOAD(0),
202 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
203 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
204 PE_CURRENT1(PE_CURRENT_0_0_mA) |
205 PE_CURRENT2(PE_CURRENT_0_0_mA) |
206 PE_CURRENT3(PE_CURRENT_0_0_mA),
207 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
208 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
209 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
210 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
211 }, { /* 720p modes */
212 .pclk = 74250000,
213 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
214 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
215 SOR_PLL_TX_REG_LOAD(0),
216 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
217 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
218 PE_CURRENT1(PE_CURRENT_5_0_mA) |
219 PE_CURRENT2(PE_CURRENT_5_0_mA) |
220 PE_CURRENT3(PE_CURRENT_5_0_mA),
221 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
222 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
223 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
224 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
225 }, { /* 1080p modes */
226 .pclk = UINT_MAX,
227 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
228 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
229 SOR_PLL_TX_REG_LOAD(0),
230 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
231 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
232 PE_CURRENT1(PE_CURRENT_5_0_mA) |
233 PE_CURRENT2(PE_CURRENT_5_0_mA) |
234 PE_CURRENT3(PE_CURRENT_5_0_mA),
235 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
236 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
237 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
238 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
239 },
240 };
241
242 static const struct tmds_config tegra114_tmds_config[] = {
243 { /* 480p/576p / 25.2MHz/27MHz modes */
244 .pclk = 27000000,
245 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
246 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
247 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
248 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
249 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
250 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
251 PE_CURRENT3(PE_CURRENT_0_mA_T114),
252 .drive_current =
253 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
254 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
255 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
256 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
257 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
258 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
259 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
260 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
261 }, { /* 720p / 74.25MHz modes */
262 .pclk = 74250000,
263 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
264 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
265 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
266 SOR_PLL_TMDS_TERMADJ(0),
267 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
268 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
269 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
270 PE_CURRENT3(PE_CURRENT_15_mA_T114),
271 .drive_current =
272 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
273 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
274 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
275 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
276 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
277 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
278 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
279 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
280 }, { /* 1080p / 148.5MHz modes */
281 .pclk = 148500000,
282 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
283 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
284 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
285 SOR_PLL_TMDS_TERMADJ(0),
286 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
287 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
288 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
289 PE_CURRENT3(PE_CURRENT_10_mA_T114),
290 .drive_current =
291 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
292 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
293 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
294 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
295 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
296 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
297 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
298 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
299 }, { /* 225/297MHz modes */
300 .pclk = UINT_MAX,
301 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
302 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
303 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
304 | SOR_PLL_TMDS_TERM_ENABLE,
305 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
306 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
307 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
308 PE_CURRENT3(PE_CURRENT_0_mA_T114),
309 .drive_current =
310 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
311 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
312 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
313 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
314 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
315 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
316 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
317 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
318 },
319 };
320
321 static const struct tegra_hdmi_audio_config *
322 tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk)
323 {
324 const struct tegra_hdmi_audio_config *table;
325
326 switch (audio_freq) {
327 case 32000:
328 table = tegra_hdmi_audio_32k;
329 break;
330
331 case 44100:
332 table = tegra_hdmi_audio_44_1k;
333 break;
334
335 case 48000:
336 table = tegra_hdmi_audio_48k;
337 break;
338
339 case 88200:
340 table = tegra_hdmi_audio_88_2k;
341 break;
342
343 case 96000:
344 table = tegra_hdmi_audio_96k;
345 break;
346
347 case 176400:
348 table = tegra_hdmi_audio_176_4k;
349 break;
350
351 case 192000:
352 table = tegra_hdmi_audio_192k;
353 break;
354
355 default:
356 return NULL;
357 }
358
359 while (table->pclk) {
360 if (table->pclk == pclk)
361 return table;
362
363 table++;
364 }
365
366 return NULL;
367 }
368
369 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
370 {
371 const unsigned int freqs[] = {
372 32000, 44100, 48000, 88200, 96000, 176400, 192000
373 };
374 unsigned int i;
375
376 for (i = 0; i < ARRAY_SIZE(freqs); i++) {
377 unsigned int f = freqs[i];
378 unsigned int eight_half;
379 unsigned long value;
380 unsigned int delta;
381
382 if (f > 96000)
383 delta = 2;
384 else if (f > 48000)
385 delta = 6;
386 else
387 delta = 9;
388
389 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
390 value = AUDIO_FS_LOW(eight_half - delta) |
391 AUDIO_FS_HIGH(eight_half + delta);
392 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
393 }
394 }
395
396 static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi, unsigned int pclk)
397 {
398 struct device_node *node = hdmi->dev->of_node;
399 const struct tegra_hdmi_audio_config *config;
400 unsigned int offset = 0;
401 unsigned long value;
402
403 switch (hdmi->audio_source) {
404 case HDA:
405 value = AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
406 break;
407
408 case SPDIF:
409 value = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
410 break;
411
412 default:
413 value = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
414 break;
415 }
416
417 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
418 value |= AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
419 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
420 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
421 } else {
422 value |= AUDIO_CNTRL0_INJECT_NULLSMPL;
423 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
424
425 value = AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
426 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
427 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
428 }
429
430 config = tegra_hdmi_get_audio_config(hdmi->audio_freq, pclk);
431 if (!config) {
432 dev_err(hdmi->dev, "cannot set audio to %u at %u pclk\n",
433 hdmi->audio_freq, pclk);
434 return -EINVAL;
435 }
436
437 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
438
439 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
440 AUDIO_N_VALUE(config->n - 1);
441 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
442
443 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
444 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
445
446 value = ACR_SUBPACK_CTS(config->cts);
447 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
448
449 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
450 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
451
452 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
453 value &= ~AUDIO_N_RESETF;
454 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
455
456 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
457 switch (hdmi->audio_freq) {
458 case 32000:
459 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320;
460 break;
461
462 case 44100:
463 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441;
464 break;
465
466 case 48000:
467 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480;
468 break;
469
470 case 88200:
471 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882;
472 break;
473
474 case 96000:
475 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960;
476 break;
477
478 case 176400:
479 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764;
480 break;
481
482 case 192000:
483 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920;
484 break;
485 }
486
487 tegra_hdmi_writel(hdmi, config->aval, offset);
488 }
489
490 tegra_hdmi_setup_audio_fs_tables(hdmi);
491
492 return 0;
493 }
494
495 static inline unsigned long tegra_hdmi_subpack(const u8 *ptr, size_t size)
496 {
497 unsigned long value = 0;
498 size_t i;
499
500 for (i = size; i > 0; i--)
501 value = (value << 8) | ptr[i - 1];
502
503 return value;
504 }
505
506 static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
507 size_t size)
508 {
509 const u8 *ptr = data;
510 unsigned long offset;
511 unsigned long value;
512 size_t i, j;
513
514 switch (ptr[0]) {
515 case HDMI_INFOFRAME_TYPE_AVI:
516 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
517 break;
518
519 case HDMI_INFOFRAME_TYPE_AUDIO:
520 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
521 break;
522
523 case HDMI_INFOFRAME_TYPE_VENDOR:
524 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
525 break;
526
527 default:
528 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
529 ptr[0]);
530 return;
531 }
532
533 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
534 INFOFRAME_HEADER_VERSION(ptr[1]) |
535 INFOFRAME_HEADER_LEN(ptr[2]);
536 tegra_hdmi_writel(hdmi, value, offset);
537 offset++;
538
539 /*
540 * Each subpack contains 7 bytes, divided into:
541 * - subpack_low: bytes 0 - 3
542 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
543 */
544 for (i = 3, j = 0; i < size; i += 7, j += 8) {
545 size_t rem = size - i, num = min_t(size_t, rem, 4);
546
547 value = tegra_hdmi_subpack(&ptr[i], num);
548 tegra_hdmi_writel(hdmi, value, offset++);
549
550 num = min_t(size_t, rem - num, 3);
551
552 value = tegra_hdmi_subpack(&ptr[i + 4], num);
553 tegra_hdmi_writel(hdmi, value, offset++);
554 }
555 }
556
557 static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
558 struct drm_display_mode *mode)
559 {
560 struct hdmi_avi_infoframe frame;
561 u8 buffer[17];
562 ssize_t err;
563
564 if (hdmi->dvi) {
565 tegra_hdmi_writel(hdmi, 0,
566 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
567 return;
568 }
569
570 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
571 if (err < 0) {
572 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
573 return;
574 }
575
576 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
577 if (err < 0) {
578 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
579 return;
580 }
581
582 tegra_hdmi_write_infopack(hdmi, buffer, err);
583
584 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
585 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
586 }
587
588 static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
589 {
590 struct hdmi_audio_infoframe frame;
591 u8 buffer[14];
592 ssize_t err;
593
594 if (hdmi->dvi) {
595 tegra_hdmi_writel(hdmi, 0,
596 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
597 return;
598 }
599
600 err = hdmi_audio_infoframe_init(&frame);
601 if (err < 0) {
602 dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n",
603 err);
604 return;
605 }
606
607 frame.channels = 2;
608
609 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
610 if (err < 0) {
611 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
612 err);
613 return;
614 }
615
616 /*
617 * The audio infoframe has only one set of subpack registers, so the
618 * infoframe needs to be truncated. One set of subpack registers can
619 * contain 7 bytes. Including the 3 byte header only the first 10
620 * bytes can be programmed.
621 */
622 tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err));
623
624 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
625 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
626 }
627
628 static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
629 {
630 struct hdmi_vendor_infoframe frame;
631 unsigned long value;
632 u8 buffer[10];
633 ssize_t err;
634
635 if (!hdmi->stereo) {
636 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
637 value &= ~GENERIC_CTRL_ENABLE;
638 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
639 return;
640 }
641
642 hdmi_vendor_infoframe_init(&frame);
643 frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
644
645 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
646 if (err < 0) {
647 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
648 err);
649 return;
650 }
651
652 tegra_hdmi_write_infopack(hdmi, buffer, err);
653
654 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
655 value |= GENERIC_CTRL_ENABLE;
656 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
657 }
658
659 static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
660 const struct tmds_config *tmds)
661 {
662 unsigned long value;
663
664 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
665 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
666 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
667
668 tegra_hdmi_writel(hdmi, tmds->drive_current,
669 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
670
671 value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
672 value |= hdmi->config->fuse_override_value;
673 tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
674
675 if (hdmi->config->has_sor_io_peak_current)
676 tegra_hdmi_writel(hdmi, tmds->peak_current,
677 HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
678 }
679
680 static bool tegra_output_is_hdmi(struct tegra_output *output)
681 {
682 struct edid *edid;
683
684 if (!output->connector.edid_blob_ptr)
685 return false;
686
687 edid = (struct edid *)output->connector.edid_blob_ptr->data;
688
689 return drm_detect_hdmi_monitor(edid);
690 }
691
692 static int tegra_output_hdmi_enable(struct tegra_output *output)
693 {
694 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
695 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
696 struct drm_display_mode *mode = &dc->base.mode;
697 struct tegra_hdmi *hdmi = to_hdmi(output);
698 struct device_node *node = hdmi->dev->of_node;
699 unsigned int pulse_start, div82, pclk;
700 unsigned long value;
701 int retries = 1000;
702 int err;
703
704 if (hdmi->enabled)
705 return 0;
706
707 hdmi->dvi = !tegra_output_is_hdmi(output);
708
709 pclk = mode->clock * 1000;
710 h_sync_width = mode->hsync_end - mode->hsync_start;
711 h_back_porch = mode->htotal - mode->hsync_end;
712 h_front_porch = mode->hsync_start - mode->hdisplay;
713
714 err = regulator_enable(hdmi->pll);
715 if (err < 0) {
716 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
717 return err;
718 }
719
720 err = regulator_enable(hdmi->vdd);
721 if (err < 0) {
722 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
723 return err;
724 }
725
726 err = clk_set_rate(hdmi->clk, pclk);
727 if (err < 0)
728 return err;
729
730 err = clk_prepare_enable(hdmi->clk);
731 if (err < 0) {
732 dev_err(hdmi->dev, "failed to enable clock: %d\n", err);
733 return err;
734 }
735
736 reset_control_assert(hdmi->rst);
737 usleep_range(1000, 2000);
738 reset_control_deassert(hdmi->rst);
739
740 /* power up sequence */
741 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
742 value &= ~SOR_PLL_PDBG;
743 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
744
745 usleep_range(10, 20);
746
747 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
748 value &= ~SOR_PLL_PWR;
749 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
750
751 tegra_dc_writel(dc, VSYNC_H_POSITION(1),
752 DC_DISP_DISP_TIMING_OPTIONS);
753 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888,
754 DC_DISP_DISP_COLOR_CONTROL);
755
756 /* video_preamble uses h_pulse2 */
757 pulse_start = 1 + h_sync_width + h_back_porch - 10;
758
759 tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
760
761 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
762 PULSE_LAST_END_A;
763 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
764
765 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
766 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
767
768 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
769 VSYNC_WINDOW_ENABLE;
770 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
771
772 if (dc->pipe)
773 value = HDMI_SRC_DISPLAYB;
774 else
775 value = HDMI_SRC_DISPLAYA;
776
777 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
778 (mode->vdisplay == 576)))
779 tegra_hdmi_writel(hdmi,
780 value | ARM_VIDEO_RANGE_FULL,
781 HDMI_NV_PDISP_INPUT_CONTROL);
782 else
783 tegra_hdmi_writel(hdmi,
784 value | ARM_VIDEO_RANGE_LIMITED,
785 HDMI_NV_PDISP_INPUT_CONTROL);
786
787 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
788 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
789 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
790
791 if (!hdmi->dvi) {
792 err = tegra_hdmi_setup_audio(hdmi, pclk);
793 if (err < 0)
794 hdmi->dvi = true;
795 }
796
797 if (of_device_is_compatible(node, "nvidia,tegra20-hdmi")) {
798 /*
799 * TODO: add ELD support
800 */
801 }
802
803 rekey = HDMI_REKEY_DEFAULT;
804 value = HDMI_CTRL_REKEY(rekey);
805 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
806 h_front_porch - rekey - 18) / 32);
807
808 if (!hdmi->dvi)
809 value |= HDMI_CTRL_ENABLE;
810
811 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
812
813 if (hdmi->dvi)
814 tegra_hdmi_writel(hdmi, 0x0,
815 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
816 else
817 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
818 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
819
820 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
821 tegra_hdmi_setup_audio_infoframe(hdmi);
822 tegra_hdmi_setup_stereo_infoframe(hdmi);
823
824 /* TMDS CONFIG */
825 for (i = 0; i < hdmi->config->num_tmds; i++) {
826 if (pclk <= hdmi->config->tmds[i].pclk) {
827 tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]);
828 break;
829 }
830 }
831
832 tegra_hdmi_writel(hdmi,
833 SOR_SEQ_CTL_PU_PC(0) |
834 SOR_SEQ_PU_PC_ALT(0) |
835 SOR_SEQ_PD_PC(8) |
836 SOR_SEQ_PD_PC_ALT(8),
837 HDMI_NV_PDISP_SOR_SEQ_CTL);
838
839 value = SOR_SEQ_INST_WAIT_TIME(1) |
840 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
841 SOR_SEQ_INST_HALT |
842 SOR_SEQ_INST_PIN_A_LOW |
843 SOR_SEQ_INST_PIN_B_LOW |
844 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
845
846 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
847 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
848
849 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
850 value &= ~SOR_CSTM_ROTCLK(~0);
851 value |= SOR_CSTM_ROTCLK(2);
852 value |= SOR_CSTM_PLLDIV;
853 value &= ~SOR_CSTM_LVDS_ENABLE;
854 value &= ~SOR_CSTM_MODE_MASK;
855 value |= SOR_CSTM_MODE_TMDS;
856 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
857
858 /* start SOR */
859 tegra_hdmi_writel(hdmi,
860 SOR_PWR_NORMAL_STATE_PU |
861 SOR_PWR_NORMAL_START_NORMAL |
862 SOR_PWR_SAFE_STATE_PD |
863 SOR_PWR_SETTING_NEW_TRIGGER,
864 HDMI_NV_PDISP_SOR_PWR);
865 tegra_hdmi_writel(hdmi,
866 SOR_PWR_NORMAL_STATE_PU |
867 SOR_PWR_NORMAL_START_NORMAL |
868 SOR_PWR_SAFE_STATE_PD |
869 SOR_PWR_SETTING_NEW_DONE,
870 HDMI_NV_PDISP_SOR_PWR);
871
872 do {
873 BUG_ON(--retries < 0);
874 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
875 } while (value & SOR_PWR_SETTING_NEW_PENDING);
876
877 value = SOR_STATE_ASY_CRCMODE_COMPLETE |
878 SOR_STATE_ASY_OWNER_HEAD0 |
879 SOR_STATE_ASY_SUBOWNER_BOTH |
880 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
881 SOR_STATE_ASY_DEPOL_POS;
882
883 /* setup sync polarities */
884 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
885 value |= SOR_STATE_ASY_HSYNCPOL_POS;
886
887 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
888 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
889
890 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
891 value |= SOR_STATE_ASY_VSYNCPOL_POS;
892
893 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
894 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
895
896 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
897
898 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
899 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
900
901 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
902 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
903 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
904 HDMI_NV_PDISP_SOR_STATE1);
905 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
906
907 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
908 value |= HDMI_ENABLE;
909 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
910
911 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
912 value &= ~DISP_CTRL_MODE_MASK;
913 value |= DISP_CTRL_MODE_C_DISPLAY;
914 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
915
916 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
917 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
918 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
919 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
920
921 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
922 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
923
924 /* TODO: add HDCP support */
925
926 hdmi->enabled = true;
927
928 return 0;
929 }
930
931 static int tegra_output_hdmi_disable(struct tegra_output *output)
932 {
933 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
934 struct tegra_hdmi *hdmi = to_hdmi(output);
935 unsigned long value;
936
937 if (!hdmi->enabled)
938 return 0;
939
940 /*
941 * The following accesses registers of the display controller, so make
942 * sure it's only executed when the output is attached to one.
943 */
944 if (dc) {
945 /*
946 * XXX: We can't do this here because it causes HDMI to go
947 * into an erroneous state with the result that HDMI won't
948 * properly work once disabled. See also a similar symptom
949 * for the SOR output.
950 */
951 /*
952 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
953 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
954 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
955 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
956 */
957
958 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
959 value &= ~DISP_CTRL_MODE_MASK;
960 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
961
962 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
963 value &= ~HDMI_ENABLE;
964 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
965
966 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
967 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
968 }
969
970 clk_disable_unprepare(hdmi->clk);
971 reset_control_assert(hdmi->rst);
972 regulator_disable(hdmi->vdd);
973 regulator_disable(hdmi->pll);
974
975 hdmi->enabled = false;
976
977 return 0;
978 }
979
980 static int tegra_output_hdmi_setup_clock(struct tegra_output *output,
981 struct clk *clk, unsigned long pclk,
982 unsigned int *div)
983 {
984 struct tegra_hdmi *hdmi = to_hdmi(output);
985 int err;
986
987 err = clk_set_parent(clk, hdmi->clk_parent);
988 if (err < 0) {
989 dev_err(output->dev, "failed to set parent: %d\n", err);
990 return err;
991 }
992
993 err = clk_set_rate(hdmi->clk_parent, pclk);
994 if (err < 0)
995 dev_err(output->dev, "failed to set clock rate to %lu Hz\n",
996 pclk);
997
998 *div = 0;
999
1000 return 0;
1001 }
1002
1003 static int tegra_output_hdmi_check_mode(struct tegra_output *output,
1004 struct drm_display_mode *mode,
1005 enum drm_mode_status *status)
1006 {
1007 struct tegra_hdmi *hdmi = to_hdmi(output);
1008 unsigned long pclk = mode->clock * 1000;
1009 struct clk *parent;
1010 long err;
1011
1012 parent = clk_get_parent(hdmi->clk_parent);
1013
1014 err = clk_round_rate(parent, pclk * 4);
1015 if (err <= 0)
1016 *status = MODE_NOCLOCK;
1017 else
1018 *status = MODE_OK;
1019
1020 return 0;
1021 }
1022
1023 static const struct tegra_output_ops hdmi_ops = {
1024 .enable = tegra_output_hdmi_enable,
1025 .disable = tegra_output_hdmi_disable,
1026 .setup_clock = tegra_output_hdmi_setup_clock,
1027 .check_mode = tegra_output_hdmi_check_mode,
1028 };
1029
1030 static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
1031 {
1032 struct drm_info_node *node = s->private;
1033 struct tegra_hdmi *hdmi = node->info_ent->data;
1034 int err;
1035
1036 err = clk_prepare_enable(hdmi->clk);
1037 if (err)
1038 return err;
1039
1040 #define DUMP_REG(name) \
1041 seq_printf(s, "%-56s %#05x %08lx\n", #name, name, \
1042 tegra_hdmi_readl(hdmi, name))
1043
1044 DUMP_REG(HDMI_CTXSW);
1045 DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
1046 DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
1047 DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
1048 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
1049 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
1050 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
1051 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
1052 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
1053 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
1054 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
1055 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
1056 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
1057 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
1058 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
1059 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
1060 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
1061 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
1062 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
1063 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
1064 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
1065 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
1066 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
1067 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
1068 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
1069 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
1070 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
1071 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
1072 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
1073 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
1074 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
1075 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
1076 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
1077 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
1078 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
1079 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
1080 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
1081 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
1082 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
1083 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
1084 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
1085 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
1086 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1087 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
1088 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
1089 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
1090 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
1091 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
1092 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
1093 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
1094 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
1095 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
1096 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
1097 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
1098 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
1099 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
1100 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
1101 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
1102 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
1103 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
1104 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
1105 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
1106 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
1107 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
1108 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
1109 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
1110 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
1111 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
1112 DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
1113 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
1114 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1115 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
1116 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
1117 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
1118 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
1119 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
1120 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
1121 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
1122 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
1123 DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
1124 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
1125 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
1126 DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL);
1127 DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
1128 DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
1129 DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
1130 DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
1131 DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
1132 DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
1133 DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
1134 DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
1135 DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
1136 DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
1137 DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
1138 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
1139 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0));
1140 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1));
1141 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2));
1142 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3));
1143 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4));
1144 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5));
1145 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6));
1146 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7));
1147 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8));
1148 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9));
1149 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10));
1150 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11));
1151 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12));
1152 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13));
1153 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14));
1154 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15));
1155 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
1156 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
1157 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
1158 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
1159 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
1160 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
1161 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
1162 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
1163 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
1164 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
1165 DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
1166 DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
1167 DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1168 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
1169 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
1170 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
1171 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
1172 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
1173 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
1174 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
1175 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
1176 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
1177 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
1178 DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
1179 DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
1180 DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
1181 DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
1182 DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
1183 DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
1184 DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
1185 DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
1186 DUMP_REG(HDMI_NV_PDISP_SCRATCH);
1187 DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
1188 DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
1189 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
1190 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
1191 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
1192 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
1193 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
1194 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
1195 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
1196 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
1197 DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
1198 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
1199 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
1200 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
1201 DUMP_REG(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
1202
1203 #undef DUMP_REG
1204
1205 clk_disable_unprepare(hdmi->clk);
1206
1207 return 0;
1208 }
1209
1210 static struct drm_info_list debugfs_files[] = {
1211 { "regs", tegra_hdmi_show_regs, 0, NULL },
1212 };
1213
1214 static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi,
1215 struct drm_minor *minor)
1216 {
1217 unsigned int i;
1218 int err;
1219
1220 hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root);
1221 if (!hdmi->debugfs)
1222 return -ENOMEM;
1223
1224 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1225 GFP_KERNEL);
1226 if (!hdmi->debugfs_files) {
1227 err = -ENOMEM;
1228 goto remove;
1229 }
1230
1231 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1232 hdmi->debugfs_files[i].data = hdmi;
1233
1234 err = drm_debugfs_create_files(hdmi->debugfs_files,
1235 ARRAY_SIZE(debugfs_files),
1236 hdmi->debugfs, minor);
1237 if (err < 0)
1238 goto free;
1239
1240 hdmi->minor = minor;
1241
1242 return 0;
1243
1244 free:
1245 kfree(hdmi->debugfs_files);
1246 hdmi->debugfs_files = NULL;
1247 remove:
1248 debugfs_remove(hdmi->debugfs);
1249 hdmi->debugfs = NULL;
1250
1251 return err;
1252 }
1253
1254 static int tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi)
1255 {
1256 drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files),
1257 hdmi->minor);
1258 hdmi->minor = NULL;
1259
1260 kfree(hdmi->debugfs_files);
1261 hdmi->debugfs_files = NULL;
1262
1263 debugfs_remove(hdmi->debugfs);
1264 hdmi->debugfs = NULL;
1265
1266 return 0;
1267 }
1268
1269 static int tegra_hdmi_init(struct host1x_client *client)
1270 {
1271 struct tegra_drm *tegra = dev_get_drvdata(client->parent);
1272 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1273 int err;
1274
1275 hdmi->output.type = TEGRA_OUTPUT_HDMI;
1276 hdmi->output.dev = client->dev;
1277 hdmi->output.ops = &hdmi_ops;
1278
1279 err = tegra_output_init(tegra->drm, &hdmi->output);
1280 if (err < 0) {
1281 dev_err(client->dev, "output setup failed: %d\n", err);
1282 return err;
1283 }
1284
1285 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1286 err = tegra_hdmi_debugfs_init(hdmi, tegra->drm->primary);
1287 if (err < 0)
1288 dev_err(client->dev, "debugfs setup failed: %d\n", err);
1289 }
1290
1291 err = regulator_enable(hdmi->hdmi);
1292 if (err < 0) {
1293 dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
1294 err);
1295 return err;
1296 }
1297
1298 return 0;
1299 }
1300
1301 static int tegra_hdmi_exit(struct host1x_client *client)
1302 {
1303 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1304 int err;
1305
1306 regulator_disable(hdmi->hdmi);
1307
1308 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1309 err = tegra_hdmi_debugfs_exit(hdmi);
1310 if (err < 0)
1311 dev_err(client->dev, "debugfs cleanup failed: %d\n",
1312 err);
1313 }
1314
1315 err = tegra_output_disable(&hdmi->output);
1316 if (err < 0) {
1317 dev_err(client->dev, "output failed to disable: %d\n", err);
1318 return err;
1319 }
1320
1321 err = tegra_output_exit(&hdmi->output);
1322 if (err < 0) {
1323 dev_err(client->dev, "output cleanup failed: %d\n", err);
1324 return err;
1325 }
1326
1327 return 0;
1328 }
1329
1330 static const struct host1x_client_ops hdmi_client_ops = {
1331 .init = tegra_hdmi_init,
1332 .exit = tegra_hdmi_exit,
1333 };
1334
1335 static const struct tegra_hdmi_config tegra20_hdmi_config = {
1336 .tmds = tegra20_tmds_config,
1337 .num_tmds = ARRAY_SIZE(tegra20_tmds_config),
1338 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1339 .fuse_override_value = 1 << 31,
1340 .has_sor_io_peak_current = false,
1341 };
1342
1343 static const struct tegra_hdmi_config tegra30_hdmi_config = {
1344 .tmds = tegra30_tmds_config,
1345 .num_tmds = ARRAY_SIZE(tegra30_tmds_config),
1346 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1347 .fuse_override_value = 1 << 31,
1348 .has_sor_io_peak_current = false,
1349 };
1350
1351 static const struct tegra_hdmi_config tegra114_hdmi_config = {
1352 .tmds = tegra114_tmds_config,
1353 .num_tmds = ARRAY_SIZE(tegra114_tmds_config),
1354 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1355 .fuse_override_value = 1 << 31,
1356 .has_sor_io_peak_current = true,
1357 };
1358
1359 static const struct of_device_id tegra_hdmi_of_match[] = {
1360 { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
1361 { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
1362 { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
1363 { },
1364 };
1365
1366 static int tegra_hdmi_probe(struct platform_device *pdev)
1367 {
1368 const struct of_device_id *match;
1369 struct tegra_hdmi *hdmi;
1370 struct resource *regs;
1371 int err;
1372
1373 match = of_match_node(tegra_hdmi_of_match, pdev->dev.of_node);
1374 if (!match)
1375 return -ENODEV;
1376
1377 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1378 if (!hdmi)
1379 return -ENOMEM;
1380
1381 hdmi->config = match->data;
1382 hdmi->dev = &pdev->dev;
1383 hdmi->audio_source = AUTO;
1384 hdmi->audio_freq = 44100;
1385 hdmi->stereo = false;
1386 hdmi->dvi = false;
1387
1388 hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1389 if (IS_ERR(hdmi->clk)) {
1390 dev_err(&pdev->dev, "failed to get clock\n");
1391 return PTR_ERR(hdmi->clk);
1392 }
1393
1394 hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
1395 if (IS_ERR(hdmi->rst)) {
1396 dev_err(&pdev->dev, "failed to get reset\n");
1397 return PTR_ERR(hdmi->rst);
1398 }
1399
1400 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1401 if (IS_ERR(hdmi->clk_parent))
1402 return PTR_ERR(hdmi->clk_parent);
1403
1404 err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1405 if (err < 0) {
1406 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1407 return err;
1408 }
1409
1410 hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi");
1411 if (IS_ERR(hdmi->hdmi)) {
1412 dev_err(&pdev->dev, "failed to get HDMI regulator\n");
1413 return PTR_ERR(hdmi->hdmi);
1414 }
1415
1416 hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1417 if (IS_ERR(hdmi->pll)) {
1418 dev_err(&pdev->dev, "failed to get PLL regulator\n");
1419 return PTR_ERR(hdmi->pll);
1420 }
1421
1422 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1423 if (IS_ERR(hdmi->vdd)) {
1424 dev_err(&pdev->dev, "failed to get VDD regulator\n");
1425 return PTR_ERR(hdmi->vdd);
1426 }
1427
1428 hdmi->output.dev = &pdev->dev;
1429
1430 err = tegra_output_probe(&hdmi->output);
1431 if (err < 0)
1432 return err;
1433
1434 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1435 hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
1436 if (IS_ERR(hdmi->regs))
1437 return PTR_ERR(hdmi->regs);
1438
1439 err = platform_get_irq(pdev, 0);
1440 if (err < 0)
1441 return err;
1442
1443 hdmi->irq = err;
1444
1445 INIT_LIST_HEAD(&hdmi->client.list);
1446 hdmi->client.ops = &hdmi_client_ops;
1447 hdmi->client.dev = &pdev->dev;
1448
1449 err = host1x_client_register(&hdmi->client);
1450 if (err < 0) {
1451 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1452 err);
1453 return err;
1454 }
1455
1456 platform_set_drvdata(pdev, hdmi);
1457
1458 return 0;
1459 }
1460
1461 static int tegra_hdmi_remove(struct platform_device *pdev)
1462 {
1463 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1464 int err;
1465
1466 err = host1x_client_unregister(&hdmi->client);
1467 if (err < 0) {
1468 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1469 err);
1470 return err;
1471 }
1472
1473 err = tegra_output_remove(&hdmi->output);
1474 if (err < 0) {
1475 dev_err(&pdev->dev, "failed to remove output: %d\n", err);
1476 return err;
1477 }
1478
1479 clk_disable_unprepare(hdmi->clk_parent);
1480 clk_disable_unprepare(hdmi->clk);
1481
1482 return 0;
1483 }
1484
1485 struct platform_driver tegra_hdmi_driver = {
1486 .driver = {
1487 .name = "tegra-hdmi",
1488 .owner = THIS_MODULE,
1489 .of_match_table = tegra_hdmi_of_match,
1490 },
1491 .probe = tegra_hdmi_probe,
1492 .remove = tegra_hdmi_remove,
1493 };
Linux kernel - Deliverables
This page took 0.061645 seconds and 4 git commands to generate.