2 * Copyright (C) 2013 NVIDIA Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/debugfs.h>
12 #include <linux/platform_device.h>
13 #include <linux/reset.h>
15 #include <soc/tegra/pmc.h>
17 #include <drm/drm_dp_helper.h>
24 struct host1x_client client
;
25 struct tegra_output output
;
30 struct reset_control
*rst
;
31 struct clk
*clk_parent
;
36 struct tegra_dpaux
*dpaux
;
41 struct dentry
*debugfs
;
44 struct tegra_sor_config
{
57 static inline struct tegra_sor
*
58 host1x_client_to_sor(struct host1x_client
*client
)
60 return container_of(client
, struct tegra_sor
, client
);
63 static inline struct tegra_sor
*to_sor(struct tegra_output
*output
)
65 return container_of(output
, struct tegra_sor
, output
);
68 static inline unsigned long tegra_sor_readl(struct tegra_sor
*sor
,
71 return readl(sor
->regs
+ (offset
<< 2));
74 static inline void tegra_sor_writel(struct tegra_sor
*sor
, unsigned long value
,
77 writel(value
, sor
->regs
+ (offset
<< 2));
80 static int tegra_sor_dp_train_fast(struct tegra_sor
*sor
,
81 struct drm_dp_link
*link
)
88 /* setup lane parameters */
89 value
= SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
90 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
91 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
92 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
93 tegra_sor_writel(sor
, value
, SOR_LANE_DRIVE_CURRENT_0
);
95 value
= SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
96 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
97 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
98 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
99 tegra_sor_writel(sor
, value
, SOR_LANE_PREEMPHASIS_0
);
101 value
= SOR_LANE_POST_CURSOR_LANE3(0x00) |
102 SOR_LANE_POST_CURSOR_LANE2(0x00) |
103 SOR_LANE_POST_CURSOR_LANE1(0x00) |
104 SOR_LANE_POST_CURSOR_LANE0(0x00);
105 tegra_sor_writel(sor
, value
, SOR_LANE_POST_CURSOR_0
);
107 /* disable LVDS mode */
108 tegra_sor_writel(sor
, 0, SOR_LVDS
);
110 value
= tegra_sor_readl(sor
, SOR_DP_PADCTL_0
);
111 value
|= SOR_DP_PADCTL_TX_PU_ENABLE
;
112 value
&= ~SOR_DP_PADCTL_TX_PU_MASK
;
113 value
|= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
114 tegra_sor_writel(sor
, value
, SOR_DP_PADCTL_0
);
116 value
= tegra_sor_readl(sor
, SOR_DP_PADCTL_0
);
117 value
|= SOR_DP_PADCTL_CM_TXD_3
| SOR_DP_PADCTL_CM_TXD_2
|
118 SOR_DP_PADCTL_CM_TXD_1
| SOR_DP_PADCTL_CM_TXD_0
;
119 tegra_sor_writel(sor
, value
, SOR_DP_PADCTL_0
);
121 usleep_range(10, 100);
123 value
= tegra_sor_readl(sor
, SOR_DP_PADCTL_0
);
124 value
&= ~(SOR_DP_PADCTL_CM_TXD_3
| SOR_DP_PADCTL_CM_TXD_2
|
125 SOR_DP_PADCTL_CM_TXD_1
| SOR_DP_PADCTL_CM_TXD_0
);
126 tegra_sor_writel(sor
, value
, SOR_DP_PADCTL_0
);
128 err
= tegra_dpaux_prepare(sor
->dpaux
, DP_SET_ANSI_8B10B
);
132 for (i
= 0, value
= 0; i
< link
->num_lanes
; i
++) {
133 unsigned long lane
= SOR_DP_TPG_CHANNEL_CODING
|
134 SOR_DP_TPG_SCRAMBLER_NONE
|
135 SOR_DP_TPG_PATTERN_TRAIN1
;
136 value
= (value
<< 8) | lane
;
139 tegra_sor_writel(sor
, value
, SOR_DP_TPG
);
141 pattern
= DP_TRAINING_PATTERN_1
;
143 err
= tegra_dpaux_train(sor
->dpaux
, link
, pattern
);
147 value
= tegra_sor_readl(sor
, SOR_DP_SPARE_0
);
148 value
|= SOR_DP_SPARE_SEQ_ENABLE
;
149 value
&= ~SOR_DP_SPARE_PANEL_INTERNAL
;
150 value
|= SOR_DP_SPARE_MACRO_SOR_CLK
;
151 tegra_sor_writel(sor
, value
, SOR_DP_SPARE_0
);
153 for (i
= 0, value
= 0; i
< link
->num_lanes
; i
++) {
154 unsigned long lane
= SOR_DP_TPG_CHANNEL_CODING
|
155 SOR_DP_TPG_SCRAMBLER_NONE
|
156 SOR_DP_TPG_PATTERN_TRAIN2
;
157 value
= (value
<< 8) | lane
;
160 tegra_sor_writel(sor
, value
, SOR_DP_TPG
);
162 pattern
= DP_LINK_SCRAMBLING_DISABLE
| DP_TRAINING_PATTERN_2
;
164 err
= tegra_dpaux_train(sor
->dpaux
, link
, pattern
);
168 for (i
= 0, value
= 0; i
< link
->num_lanes
; i
++) {
169 unsigned long lane
= SOR_DP_TPG_CHANNEL_CODING
|
170 SOR_DP_TPG_SCRAMBLER_GALIOS
|
171 SOR_DP_TPG_PATTERN_NONE
;
172 value
= (value
<< 8) | lane
;
175 tegra_sor_writel(sor
, value
, SOR_DP_TPG
);
177 pattern
= DP_TRAINING_PATTERN_DISABLE
;
179 err
= tegra_dpaux_train(sor
->dpaux
, link
, pattern
);
186 static void tegra_sor_super_update(struct tegra_sor
*sor
)
188 tegra_sor_writel(sor
, 0, SOR_SUPER_STATE_0
);
189 tegra_sor_writel(sor
, 1, SOR_SUPER_STATE_0
);
190 tegra_sor_writel(sor
, 0, SOR_SUPER_STATE_0
);
193 static void tegra_sor_update(struct tegra_sor
*sor
)
195 tegra_sor_writel(sor
, 0, SOR_STATE_0
);
196 tegra_sor_writel(sor
, 1, SOR_STATE_0
);
197 tegra_sor_writel(sor
, 0, SOR_STATE_0
);
200 static int tegra_sor_setup_pwm(struct tegra_sor
*sor
, unsigned long timeout
)
204 value
= tegra_sor_readl(sor
, SOR_PWM_DIV
);
205 value
&= ~SOR_PWM_DIV_MASK
;
206 value
|= 0x400; /* period */
207 tegra_sor_writel(sor
, value
, SOR_PWM_DIV
);
209 value
= tegra_sor_readl(sor
, SOR_PWM_CTL
);
210 value
&= ~SOR_PWM_CTL_DUTY_CYCLE_MASK
;
211 value
|= 0x400; /* duty cycle */
212 value
&= ~SOR_PWM_CTL_CLK_SEL
; /* clock source: PCLK */
213 value
|= SOR_PWM_CTL_TRIGGER
;
214 tegra_sor_writel(sor
, value
, SOR_PWM_CTL
);
216 timeout
= jiffies
+ msecs_to_jiffies(timeout
);
218 while (time_before(jiffies
, timeout
)) {
219 value
= tegra_sor_readl(sor
, SOR_PWM_CTL
);
220 if ((value
& SOR_PWM_CTL_TRIGGER
) == 0)
223 usleep_range(25, 100);
229 static int tegra_sor_attach(struct tegra_sor
*sor
)
231 unsigned long value
, timeout
;
233 /* wake up in normal mode */
234 value
= tegra_sor_readl(sor
, SOR_SUPER_STATE_1
);
235 value
|= SOR_SUPER_STATE_HEAD_MODE_AWAKE
;
236 value
|= SOR_SUPER_STATE_MODE_NORMAL
;
237 tegra_sor_writel(sor
, value
, SOR_SUPER_STATE_1
);
238 tegra_sor_super_update(sor
);
241 value
= tegra_sor_readl(sor
, SOR_SUPER_STATE_1
);
242 value
|= SOR_SUPER_STATE_ATTACHED
;
243 tegra_sor_writel(sor
, value
, SOR_SUPER_STATE_1
);
244 tegra_sor_super_update(sor
);
246 timeout
= jiffies
+ msecs_to_jiffies(250);
248 while (time_before(jiffies
, timeout
)) {
249 value
= tegra_sor_readl(sor
, SOR_TEST
);
250 if ((value
& SOR_TEST_ATTACHED
) != 0)
253 usleep_range(25, 100);
259 static int tegra_sor_wakeup(struct tegra_sor
*sor
)
261 struct tegra_dc
*dc
= to_tegra_dc(sor
->output
.encoder
.crtc
);
262 unsigned long value
, timeout
;
264 /* enable display controller outputs */
265 value
= tegra_dc_readl(dc
, DC_CMD_DISPLAY_POWER_CONTROL
);
266 value
|= PW0_ENABLE
| PW1_ENABLE
| PW2_ENABLE
| PW3_ENABLE
|
267 PW4_ENABLE
| PM0_ENABLE
| PM1_ENABLE
;
268 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_POWER_CONTROL
);
270 tegra_dc_writel(dc
, GENERAL_ACT_REQ
<< 8, DC_CMD_STATE_CONTROL
);
271 tegra_dc_writel(dc
, GENERAL_ACT_REQ
, DC_CMD_STATE_CONTROL
);
273 timeout
= jiffies
+ msecs_to_jiffies(250);
275 /* wait for head to wake up */
276 while (time_before(jiffies
, timeout
)) {
277 value
= tegra_sor_readl(sor
, SOR_TEST
);
278 value
&= SOR_TEST_HEAD_MODE_MASK
;
280 if (value
== SOR_TEST_HEAD_MODE_AWAKE
)
283 usleep_range(25, 100);
289 static int tegra_sor_power_up(struct tegra_sor
*sor
, unsigned long timeout
)
293 value
= tegra_sor_readl(sor
, SOR_PWR
);
294 value
|= SOR_PWR_TRIGGER
| SOR_PWR_NORMAL_STATE_PU
;
295 tegra_sor_writel(sor
, value
, SOR_PWR
);
297 timeout
= jiffies
+ msecs_to_jiffies(timeout
);
299 while (time_before(jiffies
, timeout
)) {
300 value
= tegra_sor_readl(sor
, SOR_PWR
);
301 if ((value
& SOR_PWR_TRIGGER
) == 0)
304 usleep_range(25, 100);
310 struct tegra_sor_params
{
311 /* number of link clocks per line */
312 unsigned int num_clocks
;
313 /* ratio between input and output */
315 /* precision factor */
318 unsigned int active_polarity
;
319 unsigned int active_count
;
320 unsigned int active_frac
;
321 unsigned int tu_size
;
325 static int tegra_sor_compute_params(struct tegra_sor
*sor
,
326 struct tegra_sor_params
*params
,
327 unsigned int tu_size
)
329 u64 active_sym
, active_count
, frac
, approx
;
330 u32 active_polarity
, active_frac
= 0;
331 const u64 f
= params
->precision
;
334 active_sym
= params
->ratio
* tu_size
;
335 active_count
= div_u64(active_sym
, f
) * f
;
336 frac
= active_sym
- active_count
;
339 if (frac
>= (f
/ 2)) {
347 frac
= div_u64(f
* f
, frac
); /* 1/fraction */
348 if (frac
<= (15 * f
)) {
349 active_frac
= div_u64(frac
, f
);
355 active_frac
= active_polarity
? 1 : 15;
359 if (active_frac
== 1)
362 if (active_polarity
== 1) {
364 approx
= active_count
+ (active_frac
* (f
- 1)) * f
;
365 approx
= div_u64(approx
, active_frac
* f
);
367 approx
= active_count
+ f
;
371 approx
= active_count
+ div_u64(f
, active_frac
);
373 approx
= active_count
;
376 error
= div_s64(active_sym
- approx
, tu_size
);
377 error
*= params
->num_clocks
;
379 if (error
<= 0 && abs64(error
) < params
->error
) {
380 params
->active_count
= div_u64(active_count
, f
);
381 params
->active_polarity
= active_polarity
;
382 params
->active_frac
= active_frac
;
383 params
->error
= abs64(error
);
384 params
->tu_size
= tu_size
;
393 static int tegra_sor_calc_config(struct tegra_sor
*sor
,
394 struct drm_display_mode
*mode
,
395 struct tegra_sor_config
*config
,
396 struct drm_dp_link
*link
)
398 const u64 f
= 100000, link_rate
= link
->rate
* 1000;
399 const u64 pclk
= mode
->clock
* 1000;
400 u64 input
, output
, watermark
, num
;
401 struct tegra_sor_params params
;
402 u32 num_syms_per_line
;
405 if (!link_rate
|| !link
->num_lanes
|| !pclk
|| !config
->bits_per_pixel
)
408 output
= link_rate
* 8 * link
->num_lanes
;
409 input
= pclk
* config
->bits_per_pixel
;
414 memset(¶ms
, 0, sizeof(params
));
415 params
.ratio
= div64_u64(input
* f
, output
);
416 params
.num_clocks
= div_u64(link_rate
* mode
->hdisplay
, pclk
);
417 params
.precision
= f
;
418 params
.error
= 64 * f
;
421 for (i
= params
.tu_size
; i
>= 32; i
--)
422 if (tegra_sor_compute_params(sor
, ¶ms
, i
))
425 if (params
.active_frac
== 0) {
426 config
->active_polarity
= 0;
427 config
->active_count
= params
.active_count
;
429 if (!params
.active_polarity
)
430 config
->active_count
--;
432 config
->tu_size
= params
.tu_size
;
433 config
->active_frac
= 1;
435 config
->active_polarity
= params
.active_polarity
;
436 config
->active_count
= params
.active_count
;
437 config
->active_frac
= params
.active_frac
;
438 config
->tu_size
= params
.tu_size
;
442 "polarity: %d active count: %d tu size: %d active frac: %d\n",
443 config
->active_polarity
, config
->active_count
,
444 config
->tu_size
, config
->active_frac
);
446 watermark
= params
.ratio
* config
->tu_size
* (f
- params
.ratio
);
447 watermark
= div_u64(watermark
, f
);
449 watermark
= div_u64(watermark
+ params
.error
, f
);
450 config
->watermark
= watermark
+ (config
->bits_per_pixel
/ 8) + 2;
451 num_syms_per_line
= (mode
->hdisplay
* config
->bits_per_pixel
) *
452 (link
->num_lanes
* 8);
454 if (config
->watermark
> 30) {
455 config
->watermark
= 30;
457 "unable to compute TU size, forcing watermark to %u\n",
459 } else if (config
->watermark
> num_syms_per_line
) {
460 config
->watermark
= num_syms_per_line
;
461 dev_err(sor
->dev
, "watermark too high, forcing to %u\n",
465 /* compute the number of symbols per horizontal blanking interval */
466 num
= ((mode
->htotal
- mode
->hdisplay
) - 7) * link_rate
;
467 config
->hblank_symbols
= div_u64(num
, pclk
);
469 if (link
->capabilities
& DP_LINK_CAP_ENHANCED_FRAMING
)
470 config
->hblank_symbols
-= 3;
472 config
->hblank_symbols
-= 12 / link
->num_lanes
;
474 /* compute the number of symbols per vertical blanking interval */
475 num
= (mode
->hdisplay
- 25) * link_rate
;
476 config
->vblank_symbols
= div_u64(num
, pclk
);
477 config
->vblank_symbols
-= 36 / link
->num_lanes
+ 4;
479 dev_dbg(sor
->dev
, "blank symbols: H:%u V:%u\n", config
->hblank_symbols
,
480 config
->vblank_symbols
);
485 static int tegra_output_sor_enable(struct tegra_output
*output
)
487 struct tegra_dc
*dc
= to_tegra_dc(output
->encoder
.crtc
);
488 struct drm_display_mode
*mode
= &dc
->base
.mode
;
489 unsigned int vbe
, vse
, hbe
, hse
, vbs
, hbs
, i
;
490 struct tegra_sor
*sor
= to_sor(output
);
491 struct tegra_sor_config config
;
492 struct drm_dp_link link
;
493 struct drm_dp_aux
*aux
;
497 mutex_lock(&sor
->lock
);
502 err
= clk_prepare_enable(sor
->clk
);
506 reset_control_deassert(sor
->rst
);
508 /* FIXME: properly convert to struct drm_dp_aux */
509 aux
= (struct drm_dp_aux
*)sor
->dpaux
;
512 err
= tegra_dpaux_enable(sor
->dpaux
);
514 dev_err(sor
->dev
, "failed to enable DP: %d\n", err
);
516 err
= drm_dp_link_probe(aux
, &link
);
518 dev_err(sor
->dev
, "failed to probe eDP link: %d\n",
524 err
= clk_set_parent(sor
->clk
, sor
->clk_safe
);
526 dev_err(sor
->dev
, "failed to set safe parent clock: %d\n", err
);
528 memset(&config
, 0, sizeof(config
));
529 config
.bits_per_pixel
= output
->connector
.display_info
.bpc
* 3;
531 err
= tegra_sor_calc_config(sor
, mode
, &config
, &link
);
533 dev_err(sor
->dev
, "failed to compute link configuration: %d\n",
536 value
= tegra_sor_readl(sor
, SOR_CLK_CNTRL
);
537 value
&= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK
;
538 value
|= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK
;
539 tegra_sor_writel(sor
, value
, SOR_CLK_CNTRL
);
541 value
= tegra_sor_readl(sor
, SOR_PLL_2
);
542 value
&= ~SOR_PLL_2_BANDGAP_POWERDOWN
;
543 tegra_sor_writel(sor
, value
, SOR_PLL_2
);
544 usleep_range(20, 100);
546 value
= tegra_sor_readl(sor
, SOR_PLL_3
);
547 value
|= SOR_PLL_3_PLL_VDD_MODE_V3_3
;
548 tegra_sor_writel(sor
, value
, SOR_PLL_3
);
550 value
= SOR_PLL_0_ICHPMP(0xf) | SOR_PLL_0_VCOCAP_RST
|
551 SOR_PLL_0_PLLREG_LEVEL_V45
| SOR_PLL_0_RESISTOR_EXT
;
552 tegra_sor_writel(sor
, value
, SOR_PLL_0
);
554 value
= tegra_sor_readl(sor
, SOR_PLL_2
);
555 value
|= SOR_PLL_2_SEQ_PLLCAPPD
;
556 value
&= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE
;
557 value
|= SOR_PLL_2_LVDS_ENABLE
;
558 tegra_sor_writel(sor
, value
, SOR_PLL_2
);
560 value
= SOR_PLL_1_TERM_COMPOUT
| SOR_PLL_1_TMDS_TERM
;
561 tegra_sor_writel(sor
, value
, SOR_PLL_1
);
564 value
= tegra_sor_readl(sor
, SOR_PLL_2
);
565 if ((value
& SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE
) == 0)
568 usleep_range(250, 1000);
571 value
= tegra_sor_readl(sor
, SOR_PLL_2
);
572 value
&= ~SOR_PLL_2_POWERDOWN_OVERRIDE
;
573 value
&= ~SOR_PLL_2_PORT_POWERDOWN
;
574 tegra_sor_writel(sor
, value
, SOR_PLL_2
);
580 /* set safe link bandwidth (1.62 Gbps) */
581 value
= tegra_sor_readl(sor
, SOR_CLK_CNTRL
);
582 value
&= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK
;
583 value
|= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62
;
584 tegra_sor_writel(sor
, value
, SOR_CLK_CNTRL
);
587 value
= tegra_sor_readl(sor
, SOR_PLL_2
);
588 value
|= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE
| SOR_PLL_2_PORT_POWERDOWN
|
589 SOR_PLL_2_BANDGAP_POWERDOWN
;
590 tegra_sor_writel(sor
, value
, SOR_PLL_2
);
592 value
= tegra_sor_readl(sor
, SOR_PLL_0
);
593 value
|= SOR_PLL_0_VCOPD
| SOR_PLL_0_POWER_OFF
;
594 tegra_sor_writel(sor
, value
, SOR_PLL_0
);
596 value
= tegra_sor_readl(sor
, SOR_DP_PADCTL_0
);
597 value
&= ~SOR_DP_PADCTL_PAD_CAL_PD
;
598 tegra_sor_writel(sor
, value
, SOR_DP_PADCTL_0
);
601 err
= tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS
);
603 dev_err(sor
->dev
, "failed to power on I/O rail: %d\n", err
);
607 usleep_range(5, 100);
610 value
= tegra_sor_readl(sor
, SOR_PLL_2
);
611 value
&= ~SOR_PLL_2_BANDGAP_POWERDOWN
;
612 tegra_sor_writel(sor
, value
, SOR_PLL_2
);
614 usleep_range(20, 100);
617 value
= tegra_sor_readl(sor
, SOR_PLL_0
);
618 value
&= ~SOR_PLL_0_POWER_OFF
;
619 value
&= ~SOR_PLL_0_VCOPD
;
620 tegra_sor_writel(sor
, value
, SOR_PLL_0
);
622 value
= tegra_sor_readl(sor
, SOR_PLL_2
);
623 value
&= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE
;
624 tegra_sor_writel(sor
, value
, SOR_PLL_2
);
626 usleep_range(200, 1000);
629 value
= tegra_sor_readl(sor
, SOR_PLL_2
);
630 value
&= ~SOR_PLL_2_PORT_POWERDOWN
;
631 tegra_sor_writel(sor
, value
, SOR_PLL_2
);
633 /* switch to DP clock */
634 err
= clk_set_parent(sor
->clk
, sor
->clk_dp
);
636 dev_err(sor
->dev
, "failed to set DP parent clock: %d\n", err
);
639 value
= tegra_sor_readl(sor
, SOR_DP_PADCTL_0
);
641 if (link
.num_lanes
<= 2)
642 value
&= ~(SOR_DP_PADCTL_PD_TXD_3
| SOR_DP_PADCTL_PD_TXD_2
);
644 value
|= SOR_DP_PADCTL_PD_TXD_3
| SOR_DP_PADCTL_PD_TXD_2
;
646 if (link
.num_lanes
<= 1)
647 value
&= ~SOR_DP_PADCTL_PD_TXD_1
;
649 value
|= SOR_DP_PADCTL_PD_TXD_1
;
651 if (link
.num_lanes
== 0)
652 value
&= ~SOR_DP_PADCTL_PD_TXD_0
;
654 value
|= SOR_DP_PADCTL_PD_TXD_0
;
656 tegra_sor_writel(sor
, value
, SOR_DP_PADCTL_0
);
658 value
= tegra_sor_readl(sor
, SOR_DP_LINKCTL_0
);
659 value
&= ~SOR_DP_LINKCTL_LANE_COUNT_MASK
;
660 value
|= SOR_DP_LINKCTL_LANE_COUNT(link
.num_lanes
);
661 tegra_sor_writel(sor
, value
, SOR_DP_LINKCTL_0
);
663 /* start lane sequencer */
664 value
= SOR_LANE_SEQ_CTL_TRIGGER
| SOR_LANE_SEQ_CTL_SEQUENCE_DOWN
|
665 SOR_LANE_SEQ_CTL_POWER_STATE_UP
;
666 tegra_sor_writel(sor
, value
, SOR_LANE_SEQ_CTL
);
669 value
= tegra_sor_readl(sor
, SOR_LANE_SEQ_CTL
);
670 if ((value
& SOR_LANE_SEQ_CTL_TRIGGER
) == 0)
673 usleep_range(250, 1000);
676 /* set link bandwidth */
677 value
= tegra_sor_readl(sor
, SOR_CLK_CNTRL
);
678 value
&= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK
;
679 value
|= drm_dp_link_rate_to_bw_code(link
.rate
) << 2;
680 tegra_sor_writel(sor
, value
, SOR_CLK_CNTRL
);
683 value
= tegra_sor_readl(sor
, SOR_DP_LINKCTL_0
);
684 value
|= SOR_DP_LINKCTL_ENABLE
;
686 value
&= ~SOR_DP_LINKCTL_TU_SIZE_MASK
;
687 value
|= SOR_DP_LINKCTL_TU_SIZE(config
.tu_size
);
689 value
|= SOR_DP_LINKCTL_ENHANCED_FRAME
;
690 tegra_sor_writel(sor
, value
, SOR_DP_LINKCTL_0
);
692 for (i
= 0, value
= 0; i
< 4; i
++) {
693 unsigned long lane
= SOR_DP_TPG_CHANNEL_CODING
|
694 SOR_DP_TPG_SCRAMBLER_GALIOS
|
695 SOR_DP_TPG_PATTERN_NONE
;
696 value
= (value
<< 8) | lane
;
699 tegra_sor_writel(sor
, value
, SOR_DP_TPG
);
701 value
= tegra_sor_readl(sor
, SOR_DP_CONFIG_0
);
702 value
&= ~SOR_DP_CONFIG_WATERMARK_MASK
;
703 value
|= SOR_DP_CONFIG_WATERMARK(config
.watermark
);
705 value
&= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK
;
706 value
|= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config
.active_count
);
708 value
&= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK
;
709 value
|= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config
.active_frac
);
711 if (config
.active_polarity
)
712 value
|= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY
;
714 value
&= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY
;
716 value
|= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE
;
717 value
|= SOR_DP_CONFIG_DISPARITY_NEGATIVE
;
718 tegra_sor_writel(sor
, value
, SOR_DP_CONFIG_0
);
720 value
= tegra_sor_readl(sor
, SOR_DP_AUDIO_HBLANK_SYMBOLS
);
721 value
&= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK
;
722 value
|= config
.hblank_symbols
& 0xffff;
723 tegra_sor_writel(sor
, value
, SOR_DP_AUDIO_HBLANK_SYMBOLS
);
725 value
= tegra_sor_readl(sor
, SOR_DP_AUDIO_VBLANK_SYMBOLS
);
726 value
&= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK
;
727 value
|= config
.vblank_symbols
& 0xffff;
728 tegra_sor_writel(sor
, value
, SOR_DP_AUDIO_VBLANK_SYMBOLS
);
730 /* enable pad calibration logic */
731 value
= tegra_sor_readl(sor
, SOR_DP_PADCTL_0
);
732 value
|= SOR_DP_PADCTL_PAD_CAL_PD
;
733 tegra_sor_writel(sor
, value
, SOR_DP_PADCTL_0
);
738 err
= drm_dp_link_probe(aux
, &link
);
740 dev_err(sor
->dev
, "failed to probe eDP link: %d\n",
745 err
= drm_dp_link_power_up(aux
, &link
);
747 dev_err(sor
->dev
, "failed to power up eDP link: %d\n",
752 err
= drm_dp_link_configure(aux
, &link
);
754 dev_err(sor
->dev
, "failed to configure eDP link: %d\n",
759 rate
= drm_dp_link_rate_to_bw_code(link
.rate
);
760 lanes
= link
.num_lanes
;
762 value
= tegra_sor_readl(sor
, SOR_CLK_CNTRL
);
763 value
&= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK
;
764 value
|= SOR_CLK_CNTRL_DP_LINK_SPEED(rate
);
765 tegra_sor_writel(sor
, value
, SOR_CLK_CNTRL
);
767 value
= tegra_sor_readl(sor
, SOR_DP_LINKCTL_0
);
768 value
&= ~SOR_DP_LINKCTL_LANE_COUNT_MASK
;
769 value
|= SOR_DP_LINKCTL_LANE_COUNT(lanes
);
771 if (link
.capabilities
& DP_LINK_CAP_ENHANCED_FRAMING
)
772 value
|= SOR_DP_LINKCTL_ENHANCED_FRAME
;
774 tegra_sor_writel(sor
, value
, SOR_DP_LINKCTL_0
);
776 /* disable training pattern generator */
778 for (i
= 0; i
< link
.num_lanes
; i
++) {
779 unsigned long lane
= SOR_DP_TPG_CHANNEL_CODING
|
780 SOR_DP_TPG_SCRAMBLER_GALIOS
|
781 SOR_DP_TPG_PATTERN_NONE
;
782 value
= (value
<< 8) | lane
;
785 tegra_sor_writel(sor
, value
, SOR_DP_TPG
);
787 err
= tegra_sor_dp_train_fast(sor
, &link
);
789 dev_err(sor
->dev
, "DP fast link training failed: %d\n",
794 dev_dbg(sor
->dev
, "fast link training succeeded\n");
797 err
= tegra_sor_power_up(sor
, 250);
799 dev_err(sor
->dev
, "failed to power up SOR: %d\n", err
);
803 /* start display controller in continuous mode */
804 value
= tegra_dc_readl(dc
, DC_CMD_STATE_ACCESS
);
806 tegra_dc_writel(dc
, value
, DC_CMD_STATE_ACCESS
);
808 tegra_dc_writel(dc
, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS
);
809 tegra_dc_writel(dc
, DISP_CTRL_MODE_C_DISPLAY
, DC_CMD_DISPLAY_COMMAND
);
811 value
= tegra_dc_readl(dc
, DC_CMD_STATE_ACCESS
);
813 tegra_dc_writel(dc
, value
, DC_CMD_STATE_ACCESS
);
816 * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete
817 * raster, associate with display controller)
819 value
= SOR_STATE_ASY_PROTOCOL_DP_A
|
820 SOR_STATE_ASY_CRC_MODE_COMPLETE
|
821 SOR_STATE_ASY_OWNER(dc
->pipe
+ 1);
823 if (mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
824 value
&= ~SOR_STATE_ASY_HSYNCPOL
;
826 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
827 value
|= SOR_STATE_ASY_HSYNCPOL
;
829 if (mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
830 value
&= ~SOR_STATE_ASY_VSYNCPOL
;
832 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
833 value
|= SOR_STATE_ASY_VSYNCPOL
;
835 switch (config
.bits_per_pixel
) {
837 value
|= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444
;
841 value
|= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444
;
849 tegra_sor_writel(sor
, value
, SOR_STATE_1
);
852 * TODO: The video timing programming below doesn't seem to match the
853 * register definitions.
856 value
= ((mode
->vtotal
& 0x7fff) << 16) | (mode
->htotal
& 0x7fff);
857 tegra_sor_writel(sor
, value
, SOR_HEAD_STATE_1(0));
859 vse
= mode
->vsync_end
- mode
->vsync_start
- 1;
860 hse
= mode
->hsync_end
- mode
->hsync_start
- 1;
862 value
= ((vse
& 0x7fff) << 16) | (hse
& 0x7fff);
863 tegra_sor_writel(sor
, value
, SOR_HEAD_STATE_2(0));
865 vbe
= vse
+ (mode
->vsync_start
- mode
->vdisplay
);
866 hbe
= hse
+ (mode
->hsync_start
- mode
->hdisplay
);
868 value
= ((vbe
& 0x7fff) << 16) | (hbe
& 0x7fff);
869 tegra_sor_writel(sor
, value
, SOR_HEAD_STATE_3(0));
871 vbs
= vbe
+ mode
->vdisplay
;
872 hbs
= hbe
+ mode
->hdisplay
;
874 value
= ((vbs
& 0x7fff) << 16) | (hbs
& 0x7fff);
875 tegra_sor_writel(sor
, value
, SOR_HEAD_STATE_4(0));
877 /* CSTM (LVDS, link A/B, upper) */
878 value
= SOR_CSTM_LVDS
| SOR_CSTM_LINK_ACT_A
| SOR_CSTM_LINK_ACT_B
|
880 tegra_sor_writel(sor
, value
, SOR_CSTM
);
883 err
= tegra_sor_setup_pwm(sor
, 250);
885 dev_err(sor
->dev
, "failed to setup PWM: %d\n", err
);
889 value
= tegra_dc_readl(dc
, DC_DISP_DISP_WIN_OPTIONS
);
891 tegra_dc_writel(dc
, value
, DC_DISP_DISP_WIN_OPTIONS
);
893 tegra_sor_update(sor
);
895 err
= tegra_sor_attach(sor
);
897 dev_err(sor
->dev
, "failed to attach SOR: %d\n", err
);
901 err
= tegra_sor_wakeup(sor
);
903 dev_err(sor
->dev
, "failed to enable DC: %d\n", err
);
910 mutex_unlock(&sor
->lock
);
914 static int tegra_sor_detach(struct tegra_sor
*sor
)
916 unsigned long value
, timeout
;
918 /* switch to safe mode */
919 value
= tegra_sor_readl(sor
, SOR_SUPER_STATE_1
);
920 value
&= ~SOR_SUPER_STATE_MODE_NORMAL
;
921 tegra_sor_writel(sor
, value
, SOR_SUPER_STATE_1
);
922 tegra_sor_super_update(sor
);
924 timeout
= jiffies
+ msecs_to_jiffies(250);
926 while (time_before(jiffies
, timeout
)) {
927 value
= tegra_sor_readl(sor
, SOR_PWR
);
928 if (value
& SOR_PWR_MODE_SAFE
)
932 if ((value
& SOR_PWR_MODE_SAFE
) == 0)
936 value
= tegra_sor_readl(sor
, SOR_SUPER_STATE_1
);
937 value
&= ~SOR_SUPER_STATE_HEAD_MODE_MASK
;
938 tegra_sor_writel(sor
, value
, SOR_SUPER_STATE_1
);
939 tegra_sor_super_update(sor
);
942 value
= tegra_sor_readl(sor
, SOR_SUPER_STATE_1
);
943 value
&= ~SOR_SUPER_STATE_ATTACHED
;
944 tegra_sor_writel(sor
, value
, SOR_SUPER_STATE_1
);
945 tegra_sor_super_update(sor
);
947 timeout
= jiffies
+ msecs_to_jiffies(250);
949 while (time_before(jiffies
, timeout
)) {
950 value
= tegra_sor_readl(sor
, SOR_TEST
);
951 if ((value
& SOR_TEST_ATTACHED
) == 0)
954 usleep_range(25, 100);
957 if ((value
& SOR_TEST_ATTACHED
) != 0)
963 static int tegra_sor_power_down(struct tegra_sor
*sor
)
965 unsigned long value
, timeout
;
968 value
= tegra_sor_readl(sor
, SOR_PWR
);
969 value
&= ~SOR_PWR_NORMAL_STATE_PU
;
970 value
|= SOR_PWR_TRIGGER
;
971 tegra_sor_writel(sor
, value
, SOR_PWR
);
973 timeout
= jiffies
+ msecs_to_jiffies(250);
975 while (time_before(jiffies
, timeout
)) {
976 value
= tegra_sor_readl(sor
, SOR_PWR
);
977 if ((value
& SOR_PWR_TRIGGER
) == 0)
980 usleep_range(25, 100);
983 if ((value
& SOR_PWR_TRIGGER
) != 0)
986 err
= clk_set_parent(sor
->clk
, sor
->clk_safe
);
988 dev_err(sor
->dev
, "failed to set safe parent clock: %d\n", err
);
990 value
= tegra_sor_readl(sor
, SOR_DP_PADCTL_0
);
991 value
&= ~(SOR_DP_PADCTL_PD_TXD_3
| SOR_DP_PADCTL_PD_TXD_0
|
992 SOR_DP_PADCTL_PD_TXD_1
| SOR_DP_PADCTL_PD_TXD_2
);
993 tegra_sor_writel(sor
, value
, SOR_DP_PADCTL_0
);
995 /* stop lane sequencer */
996 value
= SOR_LANE_SEQ_CTL_TRIGGER
| SOR_LANE_SEQ_CTL_SEQUENCE_UP
|
997 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN
;
998 tegra_sor_writel(sor
, value
, SOR_LANE_SEQ_CTL
);
1000 timeout
= jiffies
+ msecs_to_jiffies(250);
1002 while (time_before(jiffies
, timeout
)) {
1003 value
= tegra_sor_readl(sor
, SOR_LANE_SEQ_CTL
);
1004 if ((value
& SOR_LANE_SEQ_CTL_TRIGGER
) == 0)
1007 usleep_range(25, 100);
1010 if ((value
& SOR_LANE_SEQ_CTL_TRIGGER
) != 0)
1013 value
= tegra_sor_readl(sor
, SOR_PLL_2
);
1014 value
|= SOR_PLL_2_PORT_POWERDOWN
;
1015 tegra_sor_writel(sor
, value
, SOR_PLL_2
);
1017 usleep_range(20, 100);
1019 value
= tegra_sor_readl(sor
, SOR_PLL_0
);
1020 value
|= SOR_PLL_0_POWER_OFF
;
1021 value
|= SOR_PLL_0_VCOPD
;
1022 tegra_sor_writel(sor
, value
, SOR_PLL_0
);
1024 value
= tegra_sor_readl(sor
, SOR_PLL_2
);
1025 value
|= SOR_PLL_2_SEQ_PLLCAPPD
;
1026 value
|= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE
;
1027 tegra_sor_writel(sor
, value
, SOR_PLL_2
);
1029 usleep_range(20, 100);
1034 static int tegra_output_sor_disable(struct tegra_output
*output
)
1036 struct tegra_dc
*dc
= to_tegra_dc(output
->encoder
.crtc
);
1037 struct tegra_sor
*sor
= to_sor(output
);
1038 unsigned long value
;
1041 mutex_lock(&sor
->lock
);
1046 err
= tegra_sor_detach(sor
);
1048 dev_err(sor
->dev
, "failed to detach SOR: %d\n", err
);
1052 tegra_sor_writel(sor
, 0, SOR_STATE_1
);
1053 tegra_sor_update(sor
);
1056 * The following accesses registers of the display controller, so make
1057 * sure it's only executed when the output is attached to one.
1061 * XXX: We can't do this here because it causes the SOR to go
1062 * into an erroneous state and the output will look scrambled
1063 * the next time it is enabled. Presumably this is because we
1064 * should be doing this only on the next VBLANK. A possible
1065 * solution would be to queue a "power-off" event to trigger
1066 * this code to be run during the next VBLANK.
1069 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1070 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1071 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1072 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1075 value
= tegra_dc_readl(dc
, DC_CMD_DISPLAY_COMMAND
);
1076 value
&= ~DISP_CTRL_MODE_MASK
;
1077 tegra_dc_writel(dc
, value
, DC_CMD_DISPLAY_COMMAND
);
1079 value
= tegra_dc_readl(dc
, DC_DISP_DISP_WIN_OPTIONS
);
1080 value
&= ~SOR_ENABLE
;
1081 tegra_dc_writel(dc
, value
, DC_DISP_DISP_WIN_OPTIONS
);
1083 tegra_dc_writel(dc
, GENERAL_ACT_REQ
<< 8, DC_CMD_STATE_CONTROL
);
1084 tegra_dc_writel(dc
, GENERAL_ACT_REQ
, DC_CMD_STATE_CONTROL
);
1087 err
= tegra_sor_power_down(sor
);
1089 dev_err(sor
->dev
, "failed to power down SOR: %d\n", err
);
1094 err
= tegra_dpaux_disable(sor
->dpaux
);
1096 dev_err(sor
->dev
, "failed to disable DP: %d\n", err
);
1101 err
= tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS
);
1103 dev_err(sor
->dev
, "failed to power off I/O rail: %d\n", err
);
1107 reset_control_assert(sor
->rst
);
1108 clk_disable_unprepare(sor
->clk
);
1110 sor
->enabled
= false;
1113 mutex_unlock(&sor
->lock
);
1117 static int tegra_output_sor_setup_clock(struct tegra_output
*output
,
1118 struct clk
*clk
, unsigned long pclk
,
1121 struct tegra_sor
*sor
= to_sor(output
);
1124 err
= clk_set_parent(clk
, sor
->clk_parent
);
1126 dev_err(sor
->dev
, "failed to set parent clock: %d\n", err
);
1130 err
= clk_set_rate(sor
->clk_parent
, pclk
);
1132 dev_err(sor
->dev
, "failed to set clock rate to %lu Hz\n", pclk
);
1141 static int tegra_output_sor_check_mode(struct tegra_output
*output
,
1142 struct drm_display_mode
*mode
,
1143 enum drm_mode_status
*status
)
1146 * FIXME: For now, always assume that the mode is okay.
1154 static enum drm_connector_status
1155 tegra_output_sor_detect(struct tegra_output
*output
)
1157 struct tegra_sor
*sor
= to_sor(output
);
1160 return tegra_dpaux_detect(sor
->dpaux
);
1162 return connector_status_unknown
;
1165 static const struct tegra_output_ops sor_ops
= {
1166 .enable
= tegra_output_sor_enable
,
1167 .disable
= tegra_output_sor_disable
,
1168 .setup_clock
= tegra_output_sor_setup_clock
,
1169 .check_mode
= tegra_output_sor_check_mode
,
1170 .detect
= tegra_output_sor_detect
,
1173 static int tegra_sor_crc_open(struct inode
*inode
, struct file
*file
)
1175 file
->private_data
= inode
->i_private
;
1180 static int tegra_sor_crc_release(struct inode
*inode
, struct file
*file
)
1185 static int tegra_sor_crc_wait(struct tegra_sor
*sor
, unsigned long timeout
)
1189 timeout
= jiffies
+ msecs_to_jiffies(timeout
);
1191 while (time_before(jiffies
, timeout
)) {
1192 value
= tegra_sor_readl(sor
, SOR_CRC_A
);
1193 if (value
& SOR_CRC_A_VALID
)
1196 usleep_range(100, 200);
1202 static ssize_t
tegra_sor_crc_read(struct file
*file
, char __user
*buffer
,
1203 size_t size
, loff_t
*ppos
)
1205 struct tegra_sor
*sor
= file
->private_data
;
1210 mutex_lock(&sor
->lock
);
1212 if (!sor
->enabled
) {
1217 value
= tegra_sor_readl(sor
, SOR_STATE_1
);
1218 value
&= ~SOR_STATE_ASY_CRC_MODE_MASK
;
1219 tegra_sor_writel(sor
, value
, SOR_STATE_1
);
1221 value
= tegra_sor_readl(sor
, SOR_CRC_CNTRL
);
1222 value
|= SOR_CRC_CNTRL_ENABLE
;
1223 tegra_sor_writel(sor
, value
, SOR_CRC_CNTRL
);
1225 value
= tegra_sor_readl(sor
, SOR_TEST
);
1226 value
&= ~SOR_TEST_CRC_POST_SERIALIZE
;
1227 tegra_sor_writel(sor
, value
, SOR_TEST
);
1229 err
= tegra_sor_crc_wait(sor
, 100);
1233 tegra_sor_writel(sor
, SOR_CRC_A_RESET
, SOR_CRC_A
);
1234 value
= tegra_sor_readl(sor
, SOR_CRC_B
);
1236 num
= scnprintf(buf
, sizeof(buf
), "%08x\n", value
);
1238 err
= simple_read_from_buffer(buffer
, size
, ppos
, buf
, num
);
1241 mutex_unlock(&sor
->lock
);
1245 static const struct file_operations tegra_sor_crc_fops
= {
1246 .owner
= THIS_MODULE
,
1247 .open
= tegra_sor_crc_open
,
1248 .read
= tegra_sor_crc_read
,
1249 .release
= tegra_sor_crc_release
,
1252 static int tegra_sor_debugfs_init(struct tegra_sor
*sor
,
1253 struct drm_minor
*minor
)
1255 struct dentry
*entry
;
1258 sor
->debugfs
= debugfs_create_dir("sor", minor
->debugfs_root
);
1262 entry
= debugfs_create_file("crc", 0644, sor
->debugfs
, sor
,
1263 &tegra_sor_crc_fops
);
1266 "cannot create /sys/kernel/debug/dri/%s/sor/crc\n",
1267 minor
->debugfs_root
->d_name
.name
);
1275 debugfs_remove(sor
->debugfs
);
1276 sor
->debugfs
= NULL
;
1280 static int tegra_sor_debugfs_exit(struct tegra_sor
*sor
)
1282 debugfs_remove_recursive(sor
->debugfs
);
1283 sor
->debugfs
= NULL
;
1288 static int tegra_sor_init(struct host1x_client
*client
)
1290 struct drm_device
*drm
= dev_get_drvdata(client
->parent
);
1291 struct tegra_sor
*sor
= host1x_client_to_sor(client
);
1297 sor
->output
.type
= TEGRA_OUTPUT_EDP
;
1299 sor
->output
.dev
= sor
->dev
;
1300 sor
->output
.ops
= &sor_ops
;
1302 err
= tegra_output_init(drm
, &sor
->output
);
1304 dev_err(sor
->dev
, "output setup failed: %d\n", err
);
1308 if (IS_ENABLED(CONFIG_DEBUG_FS
)) {
1309 err
= tegra_sor_debugfs_init(sor
, drm
->primary
);
1311 dev_err(sor
->dev
, "debugfs setup failed: %d\n", err
);
1315 err
= tegra_dpaux_attach(sor
->dpaux
, &sor
->output
);
1317 dev_err(sor
->dev
, "failed to attach DP: %d\n", err
);
1325 static int tegra_sor_exit(struct host1x_client
*client
)
1327 struct tegra_sor
*sor
= host1x_client_to_sor(client
);
1330 err
= tegra_output_disable(&sor
->output
);
1332 dev_err(sor
->dev
, "output failed to disable: %d\n", err
);
1337 err
= tegra_dpaux_detach(sor
->dpaux
);
1339 dev_err(sor
->dev
, "failed to detach DP: %d\n", err
);
1344 if (IS_ENABLED(CONFIG_DEBUG_FS
)) {
1345 err
= tegra_sor_debugfs_exit(sor
);
1347 dev_err(sor
->dev
, "debugfs cleanup failed: %d\n", err
);
1350 err
= tegra_output_exit(&sor
->output
);
1352 dev_err(sor
->dev
, "output cleanup failed: %d\n", err
);
1359 static const struct host1x_client_ops sor_client_ops
= {
1360 .init
= tegra_sor_init
,
1361 .exit
= tegra_sor_exit
,
1364 static int tegra_sor_probe(struct platform_device
*pdev
)
1366 struct device_node
*np
;
1367 struct tegra_sor
*sor
;
1368 struct resource
*regs
;
1371 sor
= devm_kzalloc(&pdev
->dev
, sizeof(*sor
), GFP_KERNEL
);
1375 sor
->output
.dev
= sor
->dev
= &pdev
->dev
;
1377 np
= of_parse_phandle(pdev
->dev
.of_node
, "nvidia,dpaux", 0);
1379 sor
->dpaux
= tegra_dpaux_find_by_of_node(np
);
1383 return -EPROBE_DEFER
;
1386 err
= tegra_output_probe(&sor
->output
);
1390 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1391 sor
->regs
= devm_ioremap_resource(&pdev
->dev
, regs
);
1392 if (IS_ERR(sor
->regs
))
1393 return PTR_ERR(sor
->regs
);
1395 sor
->rst
= devm_reset_control_get(&pdev
->dev
, "sor");
1396 if (IS_ERR(sor
->rst
))
1397 return PTR_ERR(sor
->rst
);
1399 sor
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1400 if (IS_ERR(sor
->clk
))
1401 return PTR_ERR(sor
->clk
);
1403 sor
->clk_parent
= devm_clk_get(&pdev
->dev
, "parent");
1404 if (IS_ERR(sor
->clk_parent
))
1405 return PTR_ERR(sor
->clk_parent
);
1407 err
= clk_prepare_enable(sor
->clk_parent
);
1411 sor
->clk_safe
= devm_clk_get(&pdev
->dev
, "safe");
1412 if (IS_ERR(sor
->clk_safe
))
1413 return PTR_ERR(sor
->clk_safe
);
1415 err
= clk_prepare_enable(sor
->clk_safe
);
1419 sor
->clk_dp
= devm_clk_get(&pdev
->dev
, "dp");
1420 if (IS_ERR(sor
->clk_dp
))
1421 return PTR_ERR(sor
->clk_dp
);
1423 err
= clk_prepare_enable(sor
->clk_dp
);
1427 INIT_LIST_HEAD(&sor
->client
.list
);
1428 sor
->client
.ops
= &sor_client_ops
;
1429 sor
->client
.dev
= &pdev
->dev
;
1431 mutex_init(&sor
->lock
);
1433 err
= host1x_client_register(&sor
->client
);
1435 dev_err(&pdev
->dev
, "failed to register host1x client: %d\n",
1440 platform_set_drvdata(pdev
, sor
);
1445 static int tegra_sor_remove(struct platform_device
*pdev
)
1447 struct tegra_sor
*sor
= platform_get_drvdata(pdev
);
1450 err
= host1x_client_unregister(&sor
->client
);
1452 dev_err(&pdev
->dev
, "failed to unregister host1x client: %d\n",
1457 clk_disable_unprepare(sor
->clk_parent
);
1458 clk_disable_unprepare(sor
->clk_safe
);
1459 clk_disable_unprepare(sor
->clk_dp
);
1460 clk_disable_unprepare(sor
->clk
);
1465 static const struct of_device_id tegra_sor_of_match
[] = {
1466 { .compatible
= "nvidia,tegra124-sor", },
1469 MODULE_DEVICE_TABLE(of
, tegra_sor_of_match
);
1471 struct platform_driver tegra_sor_driver
= {
1473 .name
= "tegra-sor",
1474 .of_match_table
= tegra_sor_of_match
,
1476 .probe
= tegra_sor_probe
,
1477 .remove
= tegra_sor_remove
,