2 * Copyright (C) 2015 Broadcom
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 * DOC: VC4 CRTC module
12 * In VC4, the Pixel Valve is what most closely corresponds to the
13 * DRM's concept of a CRTC. The PV generates video timings from the
14 * output's clock plus its configuration. It pulls scaled pixels from
15 * the HVS at that timing, and feeds it to the encoder.
17 * However, the DRM CRTC also collects the configuration of all the
18 * DRM planes attached to it. As a result, this file also manages
19 * setup of the VC4 HVS's display elements on the CRTC.
21 * The 2835 has 3 different pixel valves. pv0 in the audio power
22 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
23 * image domain can feed either HDMI or the SDTV controller. The
24 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
25 * SDTV, etc.) according to which output type is chosen in the mux.
27 * For power management, the pixel valve's registers are all clocked
28 * by the AXI clock, while the timings and FIFOs make use of the
29 * output-specific clock. Since the encoders also directly consume
30 * the CPRMAN clocks, and know what timings they need, they are the
31 * ones that set the clock.
34 #include "drm_atomic.h"
35 #include "drm_atomic_helper.h"
36 #include "drm_crtc_helper.h"
37 #include "linux/clk.h"
38 #include "drm_fb_cma_helper.h"
39 #include "linux/component.h"
40 #include "linux/of_device.h"
46 const struct vc4_crtc_data
*data
;
49 /* Timestamp at start of vblank irq - unaffected by lock delays. */
52 /* Which HVS channel we're using for our CRTC. */
58 /* Size in pixels of the COB memory allocated to this CRTC. */
61 struct drm_pending_vblank_event
*event
;
64 struct vc4_crtc_state
{
65 struct drm_crtc_state base
;
66 /* Dlist area for this CRTC configuration. */
67 struct drm_mm_node mm
;
70 static inline struct vc4_crtc
*
71 to_vc4_crtc(struct drm_crtc
*crtc
)
73 return (struct vc4_crtc
*)crtc
;
76 static inline struct vc4_crtc_state
*
77 to_vc4_crtc_state(struct drm_crtc_state
*crtc_state
)
79 return (struct vc4_crtc_state
*)crtc_state
;
82 struct vc4_crtc_data
{
83 /* Which channel of the HVS this pixelvalve sources from. */
86 enum vc4_encoder_type encoder0_type
;
87 enum vc4_encoder_type encoder1_type
;
90 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
91 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
93 #define CRTC_REG(reg) { reg, #reg }
99 CRTC_REG(PV_V_CONTROL
),
100 CRTC_REG(PV_VSYNCD_EVEN
),
105 CRTC_REG(PV_VERTA_EVEN
),
106 CRTC_REG(PV_VERTB_EVEN
),
108 CRTC_REG(PV_INTSTAT
),
110 CRTC_REG(PV_HACT_ACT
),
113 static void vc4_crtc_dump_regs(struct vc4_crtc
*vc4_crtc
)
117 for (i
= 0; i
< ARRAY_SIZE(crtc_regs
); i
++) {
118 DRM_INFO("0x%04x (%s): 0x%08x\n",
119 crtc_regs
[i
].reg
, crtc_regs
[i
].name
,
120 CRTC_READ(crtc_regs
[i
].reg
));
124 #ifdef CONFIG_DEBUG_FS
125 int vc4_crtc_debugfs_regs(struct seq_file
*m
, void *unused
)
127 struct drm_info_node
*node
= (struct drm_info_node
*)m
->private;
128 struct drm_device
*dev
= node
->minor
->dev
;
129 int crtc_index
= (uintptr_t)node
->info_ent
->data
;
130 struct drm_crtc
*crtc
;
131 struct vc4_crtc
*vc4_crtc
;
135 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
142 vc4_crtc
= to_vc4_crtc(crtc
);
144 for (i
= 0; i
< ARRAY_SIZE(crtc_regs
); i
++) {
145 seq_printf(m
, "%s (0x%04x): 0x%08x\n",
146 crtc_regs
[i
].name
, crtc_regs
[i
].reg
,
147 CRTC_READ(crtc_regs
[i
].reg
));
154 int vc4_crtc_get_scanoutpos(struct drm_device
*dev
, unsigned int crtc_id
,
155 unsigned int flags
, int *vpos
, int *hpos
,
156 ktime_t
*stime
, ktime_t
*etime
,
157 const struct drm_display_mode
*mode
)
159 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
160 struct vc4_crtc
*vc4_crtc
= vc4
->crtc
[crtc_id
];
167 * XXX Doesn't work well in interlaced mode yet, partially due
168 * to problems in vc4 kms or drm core interlaced mode handling,
169 * so disable for now in interlaced mode.
171 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
174 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
176 /* Get optional system timestamp before query. */
178 *stime
= ktime_get();
181 * Read vertical scanline which is currently composed for our
182 * pixelvalve by the HVS, and also the scaler status.
184 val
= HVS_READ(SCALER_DISPSTATX(vc4_crtc
->channel
));
186 /* Get optional system timestamp after query. */
188 *etime
= ktime_get();
190 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
192 /* Vertical position of hvs composed scanline. */
193 *vpos
= VC4_GET_FIELD(val
, SCALER_DISPSTATX_LINE
);
195 /* No hpos info available. */
199 /* This is the offset we need for translating hvs -> pv scanout pos. */
200 fifo_lines
= vc4_crtc
->cob_size
/ mode
->crtc_hdisplay
;
203 ret
|= DRM_SCANOUTPOS_VALID
;
205 /* HVS more than fifo_lines into frame for compositing? */
206 if (*vpos
> fifo_lines
) {
208 * We are in active scanout and can get some meaningful results
209 * from HVS. The actual PV scanout can not trail behind more
210 * than fifo_lines as that is the fifo's capacity. Assume that
211 * in active scanout the HVS and PV work in lockstep wrt. HVS
212 * refilling the fifo and PV consuming from the fifo, ie.
213 * whenever the PV consumes and frees up a scanline in the
214 * fifo, the HVS will immediately refill it, therefore
215 * incrementing vpos. Therefore we choose HVS read position -
216 * fifo size in scanlines as a estimate of the real scanout
217 * position of the PV.
219 *vpos
-= fifo_lines
+ 1;
220 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
223 ret
|= DRM_SCANOUTPOS_ACCURATE
;
228 * Less: This happens when we are in vblank and the HVS, after getting
229 * the VSTART restart signal from the PV, just started refilling its
230 * fifo with new lines from the top-most lines of the new framebuffers.
231 * The PV does not scan out in vblank, so does not remove lines from
232 * the fifo, so the fifo will be full quickly and the HVS has to pause.
233 * We can't get meaningful readings wrt. scanline position of the PV
234 * and need to make things up in a approximative but consistent way.
236 ret
|= DRM_SCANOUTPOS_IN_VBLANK
;
237 vblank_lines
= mode
->crtc_vtotal
- mode
->crtc_vdisplay
;
239 if (flags
& DRM_CALLED_FROM_VBLIRQ
) {
241 * Assume the irq handler got called close to first
242 * line of vblank, so PV has about a full vblank
243 * scanlines to go, and as a base timestamp use the
244 * one taken at entry into vblank irq handler, so it
245 * is not affected by random delays due to lock
246 * contention on event_lock or vblank_time lock in
249 *vpos
= -vblank_lines
;
252 *stime
= vc4_crtc
->t_vblank
;
254 *etime
= vc4_crtc
->t_vblank
;
257 * If the HVS fifo is not yet full then we know for certain
258 * we are at the very beginning of vblank, as the hvs just
259 * started refilling, and the stime and etime timestamps
260 * truly correspond to start of vblank.
262 if ((val
& SCALER_DISPSTATX_FULL
) != SCALER_DISPSTATX_FULL
)
263 ret
|= DRM_SCANOUTPOS_ACCURATE
;
266 * No clue where we are inside vblank. Return a vpos of zero,
267 * which will cause calling code to just return the etime
268 * timestamp uncorrected. At least this is no worse than the
277 int vc4_crtc_get_vblank_timestamp(struct drm_device
*dev
, unsigned int crtc_id
,
278 int *max_error
, struct timeval
*vblank_time
,
281 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
282 struct vc4_crtc
*vc4_crtc
= vc4
->crtc
[crtc_id
];
283 struct drm_crtc
*crtc
= &vc4_crtc
->base
;
284 struct drm_crtc_state
*state
= crtc
->state
;
286 /* Helper routine in DRM core does all the work: */
287 return drm_calc_vbltimestamp_from_scanoutpos(dev
, crtc_id
, max_error
,
289 &state
->adjusted_mode
);
292 static void vc4_crtc_destroy(struct drm_crtc
*crtc
)
294 drm_crtc_cleanup(crtc
);
298 vc4_crtc_lut_load(struct drm_crtc
*crtc
)
300 struct drm_device
*dev
= crtc
->dev
;
301 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
302 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
305 /* The LUT memory is laid out with each HVS channel in order,
306 * each of which takes 256 writes for R, 256 for G, then 256
309 HVS_WRITE(SCALER_GAMADDR
,
310 SCALER_GAMADDR_AUTOINC
|
311 (vc4_crtc
->channel
* 3 * crtc
->gamma_size
));
313 for (i
= 0; i
< crtc
->gamma_size
; i
++)
314 HVS_WRITE(SCALER_GAMDATA
, vc4_crtc
->lut_r
[i
]);
315 for (i
= 0; i
< crtc
->gamma_size
; i
++)
316 HVS_WRITE(SCALER_GAMDATA
, vc4_crtc
->lut_g
[i
]);
317 for (i
= 0; i
< crtc
->gamma_size
; i
++)
318 HVS_WRITE(SCALER_GAMDATA
, vc4_crtc
->lut_b
[i
]);
322 vc4_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*r
, u16
*g
, u16
*b
,
325 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
328 for (i
= 0; i
< size
; i
++) {
329 vc4_crtc
->lut_r
[i
] = r
[i
] >> 8;
330 vc4_crtc
->lut_g
[i
] = g
[i
] >> 8;
331 vc4_crtc
->lut_b
[i
] = b
[i
] >> 8;
334 vc4_crtc_lut_load(crtc
);
339 static u32
vc4_get_fifo_full_level(u32 format
)
341 static const u32 fifo_len_bytes
= 64;
342 static const u32 hvs_latency_pix
= 6;
345 case PV_CONTROL_FORMAT_DSIV_16
:
346 case PV_CONTROL_FORMAT_DSIC_16
:
347 return fifo_len_bytes
- 2 * hvs_latency_pix
;
348 case PV_CONTROL_FORMAT_DSIV_18
:
349 return fifo_len_bytes
- 14;
350 case PV_CONTROL_FORMAT_24
:
351 case PV_CONTROL_FORMAT_DSIV_24
:
353 return fifo_len_bytes
- 3 * hvs_latency_pix
;
358 * Returns the clock select bit for the connector attached to the
361 static int vc4_get_clock_select(struct drm_crtc
*crtc
)
363 struct drm_connector
*connector
;
365 drm_for_each_connector(connector
, crtc
->dev
) {
366 if (connector
->state
->crtc
== crtc
) {
367 struct drm_encoder
*encoder
= connector
->encoder
;
368 struct vc4_encoder
*vc4_encoder
=
369 to_vc4_encoder(encoder
);
371 return vc4_encoder
->clock_select
;
378 static void vc4_crtc_mode_set_nofb(struct drm_crtc
*crtc
)
380 struct drm_device
*dev
= crtc
->dev
;
381 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
382 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
383 struct drm_crtc_state
*state
= crtc
->state
;
384 struct drm_display_mode
*mode
= &state
->adjusted_mode
;
385 bool interlace
= mode
->flags
& DRM_MODE_FLAG_INTERLACE
;
386 u32 vactive
= (mode
->vdisplay
>> (interlace
? 1 : 0));
387 u32 format
= PV_CONTROL_FORMAT_24
;
388 bool debug_dump_regs
= false;
389 int clock_select
= vc4_get_clock_select(crtc
);
391 if (debug_dump_regs
) {
392 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc
));
393 vc4_crtc_dump_regs(vc4_crtc
);
396 /* Reset the PV fifo. */
397 CRTC_WRITE(PV_CONTROL
, 0);
398 CRTC_WRITE(PV_CONTROL
, PV_CONTROL_FIFO_CLR
| PV_CONTROL_EN
);
399 CRTC_WRITE(PV_CONTROL
, 0);
402 VC4_SET_FIELD(mode
->htotal
- mode
->hsync_end
,
404 VC4_SET_FIELD(mode
->hsync_end
- mode
->hsync_start
,
407 VC4_SET_FIELD(mode
->hsync_start
- mode
->hdisplay
,
409 VC4_SET_FIELD(mode
->hdisplay
, PV_HORZB_HACTIVE
));
412 VC4_SET_FIELD(mode
->vtotal
- mode
->vsync_end
,
414 VC4_SET_FIELD(mode
->vsync_end
- mode
->vsync_start
,
417 VC4_SET_FIELD(mode
->vsync_start
- mode
->vdisplay
,
419 VC4_SET_FIELD(vactive
, PV_VERTB_VACTIVE
));
422 CRTC_WRITE(PV_VERTA_EVEN
,
423 VC4_SET_FIELD(mode
->vtotal
- mode
->vsync_end
- 1,
425 VC4_SET_FIELD(mode
->vsync_end
- mode
->vsync_start
,
427 CRTC_WRITE(PV_VERTB_EVEN
,
428 VC4_SET_FIELD(mode
->vsync_start
- mode
->vdisplay
,
430 VC4_SET_FIELD(vactive
, PV_VERTB_VACTIVE
));
433 CRTC_WRITE(PV_HACT_ACT
, mode
->hdisplay
);
435 CRTC_WRITE(PV_V_CONTROL
,
436 PV_VCONTROL_CONTINUOUS
|
437 (interlace
? PV_VCONTROL_INTERLACE
: 0));
439 CRTC_WRITE(PV_CONTROL
,
440 VC4_SET_FIELD(format
, PV_CONTROL_FORMAT
) |
441 VC4_SET_FIELD(vc4_get_fifo_full_level(format
),
442 PV_CONTROL_FIFO_LEVEL
) |
443 PV_CONTROL_CLR_AT_START
|
444 PV_CONTROL_TRIGGER_UNDERFLOW
|
445 PV_CONTROL_WAIT_HSTART
|
446 VC4_SET_FIELD(clock_select
, PV_CONTROL_CLK_SELECT
) |
447 PV_CONTROL_FIFO_CLR
|
450 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc
->channel
),
451 SCALER_DISPBKGND_AUTOHS
|
452 SCALER_DISPBKGND_GAMMA
|
453 (interlace
? SCALER_DISPBKGND_INTERLACE
: 0));
455 /* Reload the LUT, since the SRAMs would have been disabled if
456 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
458 vc4_crtc_lut_load(crtc
);
460 if (debug_dump_regs
) {
461 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc
));
462 vc4_crtc_dump_regs(vc4_crtc
);
466 static void require_hvs_enabled(struct drm_device
*dev
)
468 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
470 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL
) & SCALER_DISPCTRL_ENABLE
) !=
471 SCALER_DISPCTRL_ENABLE
);
474 static void vc4_crtc_disable(struct drm_crtc
*crtc
)
476 struct drm_device
*dev
= crtc
->dev
;
477 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
478 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
479 u32 chan
= vc4_crtc
->channel
;
481 require_hvs_enabled(dev
);
483 CRTC_WRITE(PV_V_CONTROL
,
484 CRTC_READ(PV_V_CONTROL
) & ~PV_VCONTROL_VIDEN
);
485 ret
= wait_for(!(CRTC_READ(PV_V_CONTROL
) & PV_VCONTROL_VIDEN
), 1);
486 WARN_ONCE(ret
, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
488 if (HVS_READ(SCALER_DISPCTRLX(chan
)) &
489 SCALER_DISPCTRLX_ENABLE
) {
490 HVS_WRITE(SCALER_DISPCTRLX(chan
),
491 SCALER_DISPCTRLX_RESET
);
493 /* While the docs say that reset is self-clearing, it
494 * seems it doesn't actually.
496 HVS_WRITE(SCALER_DISPCTRLX(chan
), 0);
499 /* Once we leave, the scaler should be disabled and its fifo empty. */
501 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan
)) & SCALER_DISPCTRLX_RESET
);
503 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan
)),
504 SCALER_DISPSTATX_MODE
) !=
505 SCALER_DISPSTATX_MODE_DISABLED
);
507 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan
)) &
508 (SCALER_DISPSTATX_FULL
| SCALER_DISPSTATX_EMPTY
)) !=
509 SCALER_DISPSTATX_EMPTY
);
512 static void vc4_crtc_enable(struct drm_crtc
*crtc
)
514 struct drm_device
*dev
= crtc
->dev
;
515 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
516 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
517 struct drm_crtc_state
*state
= crtc
->state
;
518 struct drm_display_mode
*mode
= &state
->adjusted_mode
;
520 require_hvs_enabled(dev
);
522 /* Turn on the scaler, which will wait for vstart to start
525 HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc
->channel
),
526 VC4_SET_FIELD(mode
->hdisplay
, SCALER_DISPCTRLX_WIDTH
) |
527 VC4_SET_FIELD(mode
->vdisplay
, SCALER_DISPCTRLX_HEIGHT
) |
528 SCALER_DISPCTRLX_ENABLE
);
530 /* Turn on the pixel valve, which will emit the vstart signal. */
531 CRTC_WRITE(PV_V_CONTROL
,
532 CRTC_READ(PV_V_CONTROL
) | PV_VCONTROL_VIDEN
);
535 static int vc4_crtc_atomic_check(struct drm_crtc
*crtc
,
536 struct drm_crtc_state
*state
)
538 struct vc4_crtc_state
*vc4_state
= to_vc4_crtc_state(state
);
539 struct drm_device
*dev
= crtc
->dev
;
540 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
541 struct drm_plane
*plane
;
543 const struct drm_plane_state
*plane_state
;
547 /* The pixelvalve can only feed one encoder (and encoders are
548 * 1:1 with connectors.)
550 if (hweight32(state
->connector_mask
) > 1)
553 drm_atomic_crtc_state_for_each_plane_state(plane
, plane_state
, state
)
554 dlist_count
+= vc4_plane_dlist_size(plane_state
);
556 dlist_count
++; /* Account for SCALER_CTL0_END. */
558 spin_lock_irqsave(&vc4
->hvs
->mm_lock
, flags
);
559 ret
= drm_mm_insert_node(&vc4
->hvs
->dlist_mm
, &vc4_state
->mm
,
561 spin_unlock_irqrestore(&vc4
->hvs
->mm_lock
, flags
);
568 static void vc4_crtc_atomic_flush(struct drm_crtc
*crtc
,
569 struct drm_crtc_state
*old_state
)
571 struct drm_device
*dev
= crtc
->dev
;
572 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
573 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
574 struct vc4_crtc_state
*vc4_state
= to_vc4_crtc_state(crtc
->state
);
575 struct drm_plane
*plane
;
576 bool debug_dump_regs
= false;
577 u32 __iomem
*dlist_start
= vc4
->hvs
->dlist
+ vc4_state
->mm
.start
;
578 u32 __iomem
*dlist_next
= dlist_start
;
580 if (debug_dump_regs
) {
581 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc
));
582 vc4_hvs_dump_state(dev
);
585 /* Copy all the active planes' dlist contents to the hardware dlist. */
586 drm_atomic_crtc_for_each_plane(plane
, crtc
) {
587 dlist_next
+= vc4_plane_write_dlist(plane
, dlist_next
);
590 writel(SCALER_CTL0_END
, dlist_next
);
593 WARN_ON_ONCE(dlist_next
- dlist_start
!= vc4_state
->mm
.size
);
595 if (crtc
->state
->event
) {
598 crtc
->state
->event
->pipe
= drm_crtc_index(crtc
);
600 WARN_ON(drm_crtc_vblank_get(crtc
) != 0);
602 spin_lock_irqsave(&dev
->event_lock
, flags
);
603 vc4_crtc
->event
= crtc
->state
->event
;
604 crtc
->state
->event
= NULL
;
606 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc
->channel
),
607 vc4_state
->mm
.start
);
609 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
611 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc
->channel
),
612 vc4_state
->mm
.start
);
615 if (debug_dump_regs
) {
616 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc
));
617 vc4_hvs_dump_state(dev
);
621 int vc4_enable_vblank(struct drm_device
*dev
, unsigned int crtc_id
)
623 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
624 struct vc4_crtc
*vc4_crtc
= vc4
->crtc
[crtc_id
];
626 CRTC_WRITE(PV_INTEN
, PV_INT_VFP_START
);
631 void vc4_disable_vblank(struct drm_device
*dev
, unsigned int crtc_id
)
633 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
634 struct vc4_crtc
*vc4_crtc
= vc4
->crtc
[crtc_id
];
636 CRTC_WRITE(PV_INTEN
, 0);
639 static void vc4_crtc_handle_page_flip(struct vc4_crtc
*vc4_crtc
)
641 struct drm_crtc
*crtc
= &vc4_crtc
->base
;
642 struct drm_device
*dev
= crtc
->dev
;
643 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
644 struct vc4_crtc_state
*vc4_state
= to_vc4_crtc_state(crtc
->state
);
645 u32 chan
= vc4_crtc
->channel
;
648 spin_lock_irqsave(&dev
->event_lock
, flags
);
649 if (vc4_crtc
->event
&&
650 (vc4_state
->mm
.start
== HVS_READ(SCALER_DISPLACTX(chan
)))) {
651 drm_crtc_send_vblank_event(crtc
, vc4_crtc
->event
);
652 vc4_crtc
->event
= NULL
;
653 drm_crtc_vblank_put(crtc
);
655 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
658 static irqreturn_t
vc4_crtc_irq_handler(int irq
, void *data
)
660 struct vc4_crtc
*vc4_crtc
= data
;
661 u32 stat
= CRTC_READ(PV_INTSTAT
);
662 irqreturn_t ret
= IRQ_NONE
;
664 if (stat
& PV_INT_VFP_START
) {
665 vc4_crtc
->t_vblank
= ktime_get();
666 CRTC_WRITE(PV_INTSTAT
, PV_INT_VFP_START
);
667 drm_crtc_handle_vblank(&vc4_crtc
->base
);
668 vc4_crtc_handle_page_flip(vc4_crtc
);
675 struct vc4_async_flip_state
{
676 struct drm_crtc
*crtc
;
677 struct drm_framebuffer
*fb
;
678 struct drm_pending_vblank_event
*event
;
680 struct vc4_seqno_cb cb
;
683 /* Called when the V3D execution for the BO being flipped to is done, so that
684 * we can actually update the plane's address to point to it.
687 vc4_async_page_flip_complete(struct vc4_seqno_cb
*cb
)
689 struct vc4_async_flip_state
*flip_state
=
690 container_of(cb
, struct vc4_async_flip_state
, cb
);
691 struct drm_crtc
*crtc
= flip_state
->crtc
;
692 struct drm_device
*dev
= crtc
->dev
;
693 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
694 struct drm_plane
*plane
= crtc
->primary
;
696 vc4_plane_async_set_fb(plane
, flip_state
->fb
);
697 if (flip_state
->event
) {
700 spin_lock_irqsave(&dev
->event_lock
, flags
);
701 drm_crtc_send_vblank_event(crtc
, flip_state
->event
);
702 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
705 drm_crtc_vblank_put(crtc
);
706 drm_framebuffer_unreference(flip_state
->fb
);
709 up(&vc4
->async_modeset
);
712 /* Implements async (non-vblank-synced) page flips.
714 * The page flip ioctl needs to return immediately, so we grab the
715 * modeset semaphore on the pipe, and queue the address update for
716 * when V3D is done with the BO being flipped to.
718 static int vc4_async_page_flip(struct drm_crtc
*crtc
,
719 struct drm_framebuffer
*fb
,
720 struct drm_pending_vblank_event
*event
,
723 struct drm_device
*dev
= crtc
->dev
;
724 struct vc4_dev
*vc4
= to_vc4_dev(dev
);
725 struct drm_plane
*plane
= crtc
->primary
;
727 struct vc4_async_flip_state
*flip_state
;
728 struct drm_gem_cma_object
*cma_bo
= drm_fb_cma_get_gem_obj(fb
, 0);
729 struct vc4_bo
*bo
= to_vc4_bo(&cma_bo
->base
);
731 flip_state
= kzalloc(sizeof(*flip_state
), GFP_KERNEL
);
735 drm_framebuffer_reference(fb
);
737 flip_state
->crtc
= crtc
;
738 flip_state
->event
= event
;
740 /* Make sure all other async modesetes have landed. */
741 ret
= down_interruptible(&vc4
->async_modeset
);
743 drm_framebuffer_unreference(fb
);
748 WARN_ON(drm_crtc_vblank_get(crtc
) != 0);
750 /* Immediately update the plane's legacy fb pointer, so that later
751 * modeset prep sees the state that will be present when the semaphore
754 drm_atomic_set_fb_for_plane(plane
->state
, fb
);
757 vc4_queue_seqno_cb(dev
, &flip_state
->cb
, bo
->seqno
,
758 vc4_async_page_flip_complete
);
760 /* Driver takes ownership of state on successful async commit. */
764 static int vc4_page_flip(struct drm_crtc
*crtc
,
765 struct drm_framebuffer
*fb
,
766 struct drm_pending_vblank_event
*event
,
769 if (flags
& DRM_MODE_PAGE_FLIP_ASYNC
)
770 return vc4_async_page_flip(crtc
, fb
, event
, flags
);
772 return drm_atomic_helper_page_flip(crtc
, fb
, event
, flags
);
775 static struct drm_crtc_state
*vc4_crtc_duplicate_state(struct drm_crtc
*crtc
)
777 struct vc4_crtc_state
*vc4_state
;
779 vc4_state
= kzalloc(sizeof(*vc4_state
), GFP_KERNEL
);
783 __drm_atomic_helper_crtc_duplicate_state(crtc
, &vc4_state
->base
);
784 return &vc4_state
->base
;
787 static void vc4_crtc_destroy_state(struct drm_crtc
*crtc
,
788 struct drm_crtc_state
*state
)
790 struct vc4_dev
*vc4
= to_vc4_dev(crtc
->dev
);
791 struct vc4_crtc_state
*vc4_state
= to_vc4_crtc_state(state
);
793 if (vc4_state
->mm
.allocated
) {
796 spin_lock_irqsave(&vc4
->hvs
->mm_lock
, flags
);
797 drm_mm_remove_node(&vc4_state
->mm
);
798 spin_unlock_irqrestore(&vc4
->hvs
->mm_lock
, flags
);
802 __drm_atomic_helper_crtc_destroy_state(state
);
805 static const struct drm_crtc_funcs vc4_crtc_funcs
= {
806 .set_config
= drm_atomic_helper_set_config
,
807 .destroy
= vc4_crtc_destroy
,
808 .page_flip
= vc4_page_flip
,
809 .set_property
= NULL
,
810 .cursor_set
= NULL
, /* handled by drm_mode_cursor_universal */
811 .cursor_move
= NULL
, /* handled by drm_mode_cursor_universal */
812 .reset
= drm_atomic_helper_crtc_reset
,
813 .atomic_duplicate_state
= vc4_crtc_duplicate_state
,
814 .atomic_destroy_state
= vc4_crtc_destroy_state
,
815 .gamma_set
= vc4_crtc_gamma_set
,
818 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs
= {
819 .mode_set_nofb
= vc4_crtc_mode_set_nofb
,
820 .disable
= vc4_crtc_disable
,
821 .enable
= vc4_crtc_enable
,
822 .atomic_check
= vc4_crtc_atomic_check
,
823 .atomic_flush
= vc4_crtc_atomic_flush
,
826 static const struct vc4_crtc_data pv0_data
= {
828 .encoder0_type
= VC4_ENCODER_TYPE_DSI0
,
829 .encoder1_type
= VC4_ENCODER_TYPE_DPI
,
832 static const struct vc4_crtc_data pv1_data
= {
834 .encoder0_type
= VC4_ENCODER_TYPE_DSI1
,
835 .encoder1_type
= VC4_ENCODER_TYPE_SMI
,
838 static const struct vc4_crtc_data pv2_data
= {
840 .encoder0_type
= VC4_ENCODER_TYPE_VEC
,
841 .encoder1_type
= VC4_ENCODER_TYPE_HDMI
,
844 static const struct of_device_id vc4_crtc_dt_match
[] = {
845 { .compatible
= "brcm,bcm2835-pixelvalve0", .data
= &pv0_data
},
846 { .compatible
= "brcm,bcm2835-pixelvalve1", .data
= &pv1_data
},
847 { .compatible
= "brcm,bcm2835-pixelvalve2", .data
= &pv2_data
},
851 static void vc4_set_crtc_possible_masks(struct drm_device
*drm
,
852 struct drm_crtc
*crtc
)
854 struct vc4_crtc
*vc4_crtc
= to_vc4_crtc(crtc
);
855 struct drm_encoder
*encoder
;
857 drm_for_each_encoder(encoder
, drm
) {
858 struct vc4_encoder
*vc4_encoder
= to_vc4_encoder(encoder
);
860 if (vc4_encoder
->type
== vc4_crtc
->data
->encoder0_type
) {
861 vc4_encoder
->clock_select
= 0;
862 encoder
->possible_crtcs
|= drm_crtc_mask(crtc
);
863 } else if (vc4_encoder
->type
== vc4_crtc
->data
->encoder1_type
) {
864 vc4_encoder
->clock_select
= 1;
865 encoder
->possible_crtcs
|= drm_crtc_mask(crtc
);
871 vc4_crtc_get_cob_allocation(struct vc4_crtc
*vc4_crtc
)
873 struct drm_device
*drm
= vc4_crtc
->base
.dev
;
874 struct vc4_dev
*vc4
= to_vc4_dev(drm
);
875 u32 dispbase
= HVS_READ(SCALER_DISPBASEX(vc4_crtc
->channel
));
876 /* Top/base are supposed to be 4-pixel aligned, but the
877 * Raspberry Pi firmware fills the low bits (which are
878 * presumably ignored).
880 u32 top
= VC4_GET_FIELD(dispbase
, SCALER_DISPBASEX_TOP
) & ~3;
881 u32 base
= VC4_GET_FIELD(dispbase
, SCALER_DISPBASEX_BASE
) & ~3;
883 vc4_crtc
->cob_size
= top
- base
+ 4;
886 static int vc4_crtc_bind(struct device
*dev
, struct device
*master
, void *data
)
888 struct platform_device
*pdev
= to_platform_device(dev
);
889 struct drm_device
*drm
= dev_get_drvdata(master
);
890 struct vc4_dev
*vc4
= to_vc4_dev(drm
);
891 struct vc4_crtc
*vc4_crtc
;
892 struct drm_crtc
*crtc
;
893 struct drm_plane
*primary_plane
, *cursor_plane
, *destroy_plane
, *temp
;
894 const struct of_device_id
*match
;
897 vc4_crtc
= devm_kzalloc(dev
, sizeof(*vc4_crtc
), GFP_KERNEL
);
900 crtc
= &vc4_crtc
->base
;
902 match
= of_match_device(vc4_crtc_dt_match
, dev
);
905 vc4_crtc
->data
= match
->data
;
907 vc4_crtc
->regs
= vc4_ioremap_regs(pdev
, 0);
908 if (IS_ERR(vc4_crtc
->regs
))
909 return PTR_ERR(vc4_crtc
->regs
);
911 /* For now, we create just the primary and the legacy cursor
912 * planes. We should be able to stack more planes on easily,
913 * but to do that we would need to compute the bandwidth
914 * requirement of the plane configuration, and reject ones
915 * that will take too much.
917 primary_plane
= vc4_plane_init(drm
, DRM_PLANE_TYPE_PRIMARY
);
918 if (IS_ERR(primary_plane
)) {
919 dev_err(dev
, "failed to construct primary plane\n");
920 ret
= PTR_ERR(primary_plane
);
924 drm_crtc_init_with_planes(drm
, crtc
, primary_plane
, NULL
,
925 &vc4_crtc_funcs
, NULL
);
926 drm_crtc_helper_add(crtc
, &vc4_crtc_helper_funcs
);
927 primary_plane
->crtc
= crtc
;
928 vc4
->crtc
[drm_crtc_index(crtc
)] = vc4_crtc
;
929 vc4_crtc
->channel
= vc4_crtc
->data
->hvs_channel
;
930 drm_mode_crtc_set_gamma_size(crtc
, ARRAY_SIZE(vc4_crtc
->lut_r
));
932 /* Set up some arbitrary number of planes. We're not limited
933 * by a set number of physical registers, just the space in
934 * the HVS (16k) and how small an plane can be (28 bytes).
935 * However, each plane we set up takes up some memory, and
936 * increases the cost of looping over planes, which atomic
937 * modesetting does quite a bit. As a result, we pick a
938 * modest number of planes to expose, that should hopefully
939 * still cover any sane usecase.
941 for (i
= 0; i
< 8; i
++) {
942 struct drm_plane
*plane
=
943 vc4_plane_init(drm
, DRM_PLANE_TYPE_OVERLAY
);
948 plane
->possible_crtcs
= 1 << drm_crtc_index(crtc
);
951 /* Set up the legacy cursor after overlay initialization,
952 * since we overlay planes on the CRTC in the order they were
955 cursor_plane
= vc4_plane_init(drm
, DRM_PLANE_TYPE_CURSOR
);
956 if (!IS_ERR(cursor_plane
)) {
957 cursor_plane
->possible_crtcs
= 1 << drm_crtc_index(crtc
);
958 cursor_plane
->crtc
= crtc
;
959 crtc
->cursor
= cursor_plane
;
962 vc4_crtc_get_cob_allocation(vc4_crtc
);
964 CRTC_WRITE(PV_INTEN
, 0);
965 CRTC_WRITE(PV_INTSTAT
, PV_INT_VFP_START
);
966 ret
= devm_request_irq(dev
, platform_get_irq(pdev
, 0),
967 vc4_crtc_irq_handler
, 0, "vc4 crtc", vc4_crtc
);
969 goto err_destroy_planes
;
971 vc4_set_crtc_possible_masks(drm
, crtc
);
973 for (i
= 0; i
< crtc
->gamma_size
; i
++) {
974 vc4_crtc
->lut_r
[i
] = i
;
975 vc4_crtc
->lut_g
[i
] = i
;
976 vc4_crtc
->lut_b
[i
] = i
;
979 platform_set_drvdata(pdev
, vc4_crtc
);
984 list_for_each_entry_safe(destroy_plane
, temp
,
985 &drm
->mode_config
.plane_list
, head
) {
986 if (destroy_plane
->possible_crtcs
== 1 << drm_crtc_index(crtc
))
987 destroy_plane
->funcs
->destroy(destroy_plane
);
993 static void vc4_crtc_unbind(struct device
*dev
, struct device
*master
,
996 struct platform_device
*pdev
= to_platform_device(dev
);
997 struct vc4_crtc
*vc4_crtc
= dev_get_drvdata(dev
);
999 vc4_crtc_destroy(&vc4_crtc
->base
);
1001 CRTC_WRITE(PV_INTEN
, 0);
1003 platform_set_drvdata(pdev
, NULL
);
1006 static const struct component_ops vc4_crtc_ops
= {
1007 .bind
= vc4_crtc_bind
,
1008 .unbind
= vc4_crtc_unbind
,
1011 static int vc4_crtc_dev_probe(struct platform_device
*pdev
)
1013 return component_add(&pdev
->dev
, &vc4_crtc_ops
);
1016 static int vc4_crtc_dev_remove(struct platform_device
*pdev
)
1018 component_del(&pdev
->dev
, &vc4_crtc_ops
);
1022 struct platform_driver vc4_crtc_driver
= {
1023 .probe
= vc4_crtc_dev_probe
,
1024 .remove
= vc4_crtc_dev_remove
,
1027 .of_match_table
= vc4_crtc_dt_match
,