drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

   1 /**************************************************************************
   2  *
   3  * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27 #include <linux/module.h>
  28
  29 #include "drmP.h"
  30 #include "vmwgfx_drv.h"
  31 #include "ttm/ttm_placement.h"
  32 #include "ttm/ttm_bo_driver.h"
  33 #include "ttm/ttm_object.h"
  34 #include "ttm/ttm_module.h"
  35
  36 #define VMWGFX_DRIVER_NAME "vmwgfx"
  37 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
  38 #define VMWGFX_CHIP_SVGAII 0
  39 #define VMW_FB_RESERVATION 0
  40
  41 #define VMW_MIN_INITIAL_WIDTH 800
  42 #define VMW_MIN_INITIAL_HEIGHT 600
  43
  44
  45 /**
  46  * Fully encoded drm commands. Might move to vmw_drm.h
  47  */
  48
  49 #define DRM_IOCTL_VMW_GET_PARAM                                 \
  50         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM,          \
  51                  struct drm_vmw_getparam_arg)
  52 #define DRM_IOCTL_VMW_ALLOC_DMABUF                              \
  53         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF,       \
  54                 union drm_vmw_alloc_dmabuf_arg)
  55 #define DRM_IOCTL_VMW_UNREF_DMABUF                              \
  56         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF,        \
  57                 struct drm_vmw_unref_dmabuf_arg)
  58 #define DRM_IOCTL_VMW_CURSOR_BYPASS                             \
  59         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS,       \
  60                  struct drm_vmw_cursor_bypass_arg)
  61
  62 #define DRM_IOCTL_VMW_CONTROL_STREAM                            \
  63         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM,      \
  64                  struct drm_vmw_control_stream_arg)
  65 #define DRM_IOCTL_VMW_CLAIM_STREAM                              \
  66         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM,        \
  67                  struct drm_vmw_stream_arg)
  68 #define DRM_IOCTL_VMW_UNREF_STREAM                              \
  69         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM,        \
  70                  struct drm_vmw_stream_arg)
  71
  72 #define DRM_IOCTL_VMW_CREATE_CONTEXT                            \
  73         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT,      \
  74                 struct drm_vmw_context_arg)
  75 #define DRM_IOCTL_VMW_UNREF_CONTEXT                             \
  76         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT,       \
  77                 struct drm_vmw_context_arg)
  78 #define DRM_IOCTL_VMW_CREATE_SURFACE                            \
  79         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE,     \
  80                  union drm_vmw_surface_create_arg)
  81 #define DRM_IOCTL_VMW_UNREF_SURFACE                             \
  82         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE,       \
  83                  struct drm_vmw_surface_arg)
  84 #define DRM_IOCTL_VMW_REF_SURFACE                               \
  85         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE,        \
  86                  union drm_vmw_surface_reference_arg)
  87 #define DRM_IOCTL_VMW_EXECBUF                                   \
  88         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF,             \
  89                 struct drm_vmw_execbuf_arg)
  90 #define DRM_IOCTL_VMW_GET_3D_CAP                                \
  91         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP,          \
  92                  struct drm_vmw_get_3d_cap_arg)
  93 #define DRM_IOCTL_VMW_FENCE_WAIT                                \
  94         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT,         \
  95                  struct drm_vmw_fence_wait_arg)
  96 #define DRM_IOCTL_VMW_FENCE_SIGNALED                            \
  97         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED,     \
  98                  struct drm_vmw_fence_signaled_arg)
  99 #define DRM_IOCTL_VMW_FENCE_UNREF                               \
 100         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF,         \
 101                  struct drm_vmw_fence_arg)
 102 #define DRM_IOCTL_VMW_FENCE_EVENT                               \
 103         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT,         \
 104                  struct drm_vmw_fence_event_arg)
 105 #define DRM_IOCTL_VMW_PRESENT                                   \
 106         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT,             \
 107                  struct drm_vmw_present_arg)
 108 #define DRM_IOCTL_VMW_PRESENT_READBACK                          \
 109         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK,    \
 110                  struct drm_vmw_present_readback_arg)
 111 #define DRM_IOCTL_VMW_UPDATE_LAYOUT                             \
 112         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT,       \
 113                  struct drm_vmw_update_layout_arg)
 114
 115 /**
 116  * The core DRM version of this macro doesn't account for
 117  * DRM_COMMAND_BASE.
 118  */
 119
 120 #define VMW_IOCTL_DEF(ioctl, func, flags) \
 121   [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
 122
 123 /**
 124  * Ioctl definitions.
 125  */
 126
 127 static struct drm_ioctl_desc vmw_ioctls[] = {
 128         VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
 129                       DRM_AUTH | DRM_UNLOCKED),
 130         VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
 131                       DRM_AUTH | DRM_UNLOCKED),
 132         VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
 133                       DRM_AUTH | DRM_UNLOCKED),
 134         VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
 135                       vmw_kms_cursor_bypass_ioctl,
 136                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 137
 138         VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
 139                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 140         VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
 141                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 142         VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
 143                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 144
 145         VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
 146                       DRM_AUTH | DRM_UNLOCKED),
 147         VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
 148                       DRM_AUTH | DRM_UNLOCKED),
 149         VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
 150                       DRM_AUTH | DRM_UNLOCKED),
 151         VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
 152                       DRM_AUTH | DRM_UNLOCKED),
 153         VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
 154                       DRM_AUTH | DRM_UNLOCKED),
 155         VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
 156                       DRM_AUTH | DRM_UNLOCKED),
 157         VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
 158                       DRM_AUTH | DRM_UNLOCKED),
 159         VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
 160                       vmw_fence_obj_signaled_ioctl,
 161                       DRM_AUTH | DRM_UNLOCKED),
 162         VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
 163                       DRM_AUTH | DRM_UNLOCKED),
 164         VMW_IOCTL_DEF(VMW_FENCE_EVENT,
 165                       vmw_fence_event_ioctl,
 166                       DRM_AUTH | DRM_UNLOCKED),
 167         VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
 168                       DRM_AUTH | DRM_UNLOCKED),
 169
 170         /* these allow direct access to the framebuffers mark as master only */
 171         VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
 172                       DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
 173         VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
 174                       vmw_present_readback_ioctl,
 175                       DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
 176         VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
 177                       vmw_kms_update_layout_ioctl,
 178                       DRM_MASTER | DRM_UNLOCKED),
 179 };
 180
 181 static struct pci_device_id vmw_pci_id_list[] = {
 182         {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
 183         {0, 0, 0}
 184 };
 185
 186 static int enable_fbdev;
 187
 188 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
 189 static void vmw_master_init(struct vmw_master *);
 190 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
 191                               void *ptr);
 192
 193 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
 194 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
 195
 196 static void vmw_print_capabilities(uint32_t capabilities)
 197 {
 198         DRM_INFO("Capabilities:\n");
 199         if (capabilities & SVGA_CAP_RECT_COPY)
 200                 DRM_INFO("  Rect copy.\n");
 201         if (capabilities & SVGA_CAP_CURSOR)
 202                 DRM_INFO("  Cursor.\n");
 203         if (capabilities & SVGA_CAP_CURSOR_BYPASS)
 204                 DRM_INFO("  Cursor bypass.\n");
 205         if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
 206                 DRM_INFO("  Cursor bypass 2.\n");
 207         if (capabilities & SVGA_CAP_8BIT_EMULATION)
 208                 DRM_INFO("  8bit emulation.\n");
 209         if (capabilities & SVGA_CAP_ALPHA_CURSOR)
 210                 DRM_INFO("  Alpha cursor.\n");
 211         if (capabilities & SVGA_CAP_3D)
 212                 DRM_INFO("  3D.\n");
 213         if (capabilities & SVGA_CAP_EXTENDED_FIFO)
 214                 DRM_INFO("  Extended Fifo.\n");
 215         if (capabilities & SVGA_CAP_MULTIMON)
 216                 DRM_INFO("  Multimon.\n");
 217         if (capabilities & SVGA_CAP_PITCHLOCK)
 218                 DRM_INFO("  Pitchlock.\n");
 219         if (capabilities & SVGA_CAP_IRQMASK)
 220                 DRM_INFO("  Irq mask.\n");
 221         if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
 222                 DRM_INFO("  Display Topology.\n");
 223         if (capabilities & SVGA_CAP_GMR)
 224                 DRM_INFO("  GMR.\n");
 225         if (capabilities & SVGA_CAP_TRACES)
 226                 DRM_INFO("  Traces.\n");
 227         if (capabilities & SVGA_CAP_GMR2)
 228                 DRM_INFO("  GMR2.\n");
 229         if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
 230                 DRM_INFO("  Screen Object 2.\n");
 231 }
 232
 233
 234 /**
 235  * vmw_execbuf_prepare_dummy_query - Initialize a query result structure at
 236  * the start of a buffer object.
 237  *
 238  * @dev_priv: The device private structure.
 239  *
 240  * This function will idle the buffer using an uninterruptible wait, then
 241  * map the first page and initialize a pending occlusion query result structure,
 242  * Finally it will unmap the buffer.
 243  *
 244  * TODO: Since we're only mapping a single page, we should optimize the map
 245  * to use kmap_atomic / iomap_atomic.
 246  */
 247 static void vmw_dummy_query_bo_prepare(struct vmw_private *dev_priv)
 248 {
 249         struct ttm_bo_kmap_obj map;
 250         volatile SVGA3dQueryResult *result;
 251         bool dummy;
 252         int ret;
 253         struct ttm_bo_device *bdev = &dev_priv->bdev;
 254         struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
 255
 256         ttm_bo_reserve(bo, false, false, false, 0);
 257         spin_lock(&bdev->fence_lock);
 258         ret = ttm_bo_wait(bo, false, false, false);
 259         spin_unlock(&bdev->fence_lock);
 260         if (unlikely(ret != 0))
 261                 (void) vmw_fallback_wait(dev_priv, false, true, 0, false,
 262                                          10*HZ);
 263
 264         ret = ttm_bo_kmap(bo, 0, 1, &map);
 265         if (likely(ret == 0)) {
 266                 result = ttm_kmap_obj_virtual(&map, &dummy);
 267                 result->totalSize = sizeof(*result);
 268                 result->state = SVGA3D_QUERYSTATE_PENDING;
 269                 result->result32 = 0xff;
 270                 ttm_bo_kunmap(&map);
 271         } else
 272                 DRM_ERROR("Dummy query buffer map failed.\n");
 273         ttm_bo_unreserve(bo);
 274 }
 275
 276
 277 /**
 278  * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
 279  *
 280  * @dev_priv: A device private structure.
 281  *
 282  * This function creates a small buffer object that holds the query
 283  * result for dummy queries emitted as query barriers.
 284  * No interruptible waits are done within this function.
 285  *
 286  * Returns an error if bo creation fails.
 287  */
 288 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
 289 {
 290         return ttm_bo_create(&dev_priv->bdev,
 291                              PAGE_SIZE,
 292                              ttm_bo_type_device,
 293                              &vmw_vram_sys_placement,
 294                              0, 0, false, NULL,
 295                              &dev_priv->dummy_query_bo);
 296 }
 297
 298
 299 static int vmw_request_device(struct vmw_private *dev_priv)
 300 {
 301         int ret;
 302
 303         ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
 304         if (unlikely(ret != 0)) {
 305                 DRM_ERROR("Unable to initialize FIFO.\n");
 306                 return ret;
 307         }
 308         vmw_fence_fifo_up(dev_priv->fman);
 309         ret = vmw_dummy_query_bo_create(dev_priv);
 310         if (unlikely(ret != 0))
 311                 goto out_no_query_bo;
 312         vmw_dummy_query_bo_prepare(dev_priv);
 313
 314         return 0;
 315
 316 out_no_query_bo:
 317         vmw_fence_fifo_down(dev_priv->fman);
 318         vmw_fifo_release(dev_priv, &dev_priv->fifo);
 319         return ret;
 320 }
 321
 322 static void vmw_release_device(struct vmw_private *dev_priv)
 323 {
 324         /*
 325          * Previous destructions should've released
 326          * the pinned bo.
 327          */
 328
 329         BUG_ON(dev_priv->pinned_bo != NULL);
 330
 331         ttm_bo_unref(&dev_priv->dummy_query_bo);
 332         vmw_fence_fifo_down(dev_priv->fman);
 333         vmw_fifo_release(dev_priv, &dev_priv->fifo);
 334 }
 335
 336 /**
 337  * Increase the 3d resource refcount.
 338  * If the count was prevously zero, initialize the fifo, switching to svga
 339  * mode. Note that the master holds a ref as well, and may request an
 340  * explicit switch to svga mode if fb is not running, using @unhide_svga.
 341  */
 342 int vmw_3d_resource_inc(struct vmw_private *dev_priv,
 343                         bool unhide_svga)
 344 {
 345         int ret = 0;
 346
 347         mutex_lock(&dev_priv->release_mutex);
 348         if (unlikely(dev_priv->num_3d_resources++ == 0)) {
 349                 ret = vmw_request_device(dev_priv);
 350                 if (unlikely(ret != 0))
 351                         --dev_priv->num_3d_resources;
 352         } else if (unhide_svga) {
 353                 mutex_lock(&dev_priv->hw_mutex);
 354                 vmw_write(dev_priv, SVGA_REG_ENABLE,
 355                           vmw_read(dev_priv, SVGA_REG_ENABLE) &
 356                           ~SVGA_REG_ENABLE_HIDE);
 357                 mutex_unlock(&dev_priv->hw_mutex);
 358         }
 359
 360         mutex_unlock(&dev_priv->release_mutex);
 361         return ret;
 362 }
 363
 364 /**
 365  * Decrease the 3d resource refcount.
 366  * If the count reaches zero, disable the fifo, switching to vga mode.
 367  * Note that the master holds a refcount as well, and may request an
 368  * explicit switch to vga mode when it releases its refcount to account
 369  * for the situation of an X server vt switch to VGA with 3d resources
 370  * active.
 371  */
 372 void vmw_3d_resource_dec(struct vmw_private *dev_priv,
 373                          bool hide_svga)
 374 {
 375         int32_t n3d;
 376
 377         mutex_lock(&dev_priv->release_mutex);
 378         if (unlikely(--dev_priv->num_3d_resources == 0))
 379                 vmw_release_device(dev_priv);
 380         else if (hide_svga) {
 381                 mutex_lock(&dev_priv->hw_mutex);
 382                 vmw_write(dev_priv, SVGA_REG_ENABLE,
 383                           vmw_read(dev_priv, SVGA_REG_ENABLE) |
 384                           SVGA_REG_ENABLE_HIDE);
 385                 mutex_unlock(&dev_priv->hw_mutex);
 386         }
 387
 388         n3d = (int32_t) dev_priv->num_3d_resources;
 389         mutex_unlock(&dev_priv->release_mutex);
 390
 391         BUG_ON(n3d < 0);
 392 }
 393
 394 /**
 395  * Sets the initial_[width|height] fields on the given vmw_private.
 396  *
 397  * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
 398  * clamping the value to fb_max_[width|height] fields and the
 399  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
 400  * If the values appear to be invalid, set them to
 401  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
 402  */
 403 static void vmw_get_initial_size(struct vmw_private *dev_priv)
 404 {
 405         uint32_t width;
 406         uint32_t height;
 407
 408         width = vmw_read(dev_priv, SVGA_REG_WIDTH);
 409         height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
 410
 411         width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
 412         height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
 413
 414         if (width > dev_priv->fb_max_width ||
 415             height > dev_priv->fb_max_height) {
 416
 417                 /*
 418                  * This is a host error and shouldn't occur.
 419                  */
 420
 421                 width = VMW_MIN_INITIAL_WIDTH;
 422                 height = VMW_MIN_INITIAL_HEIGHT;
 423         }
 424
 425         dev_priv->initial_width = width;
 426         dev_priv->initial_height = height;
 427 }
 428
 429 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
 430 {
 431         struct vmw_private *dev_priv;
 432         int ret;
 433         uint32_t svga_id;
 434
 435         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 436         if (unlikely(dev_priv == NULL)) {
 437                 DRM_ERROR("Failed allocating a device private struct.\n");
 438                 return -ENOMEM;
 439         }
 440
 441         pci_set_master(dev->pdev);
 442
 443         dev_priv->dev = dev;
 444         dev_priv->vmw_chipset = chipset;
 445         dev_priv->last_read_seqno = (uint32_t) -100;
 446         mutex_init(&dev_priv->hw_mutex);
 447         mutex_init(&dev_priv->cmdbuf_mutex);
 448         mutex_init(&dev_priv->release_mutex);
 449         rwlock_init(&dev_priv->resource_lock);
 450         idr_init(&dev_priv->context_idr);
 451         idr_init(&dev_priv->surface_idr);
 452         idr_init(&dev_priv->stream_idr);
 453         mutex_init(&dev_priv->init_mutex);
 454         init_waitqueue_head(&dev_priv->fence_queue);
 455         init_waitqueue_head(&dev_priv->fifo_queue);
 456         dev_priv->fence_queue_waiters = 0;
 457         atomic_set(&dev_priv->fifo_queue_waiters, 0);
 458         INIT_LIST_HEAD(&dev_priv->surface_lru);
 459         dev_priv->used_memory_size = 0;
 460
 461         dev_priv->io_start = pci_resource_start(dev->pdev, 0);
 462         dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
 463         dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
 464
 465         dev_priv->enable_fb = enable_fbdev;
 466
 467         mutex_lock(&dev_priv->hw_mutex);
 468
 469         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
 470         svga_id = vmw_read(dev_priv, SVGA_REG_ID);
 471         if (svga_id != SVGA_ID_2) {
 472                 ret = -ENOSYS;
 473                 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
 474                 mutex_unlock(&dev_priv->hw_mutex);
 475                 goto out_err0;
 476         }
 477
 478         dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
 479
 480         dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
 481         dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
 482         dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
 483         dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
 484
 485         vmw_get_initial_size(dev_priv);
 486
 487         if (dev_priv->capabilities & SVGA_CAP_GMR) {
 488                 dev_priv->max_gmr_descriptors =
 489                         vmw_read(dev_priv,
 490                                  SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
 491                 dev_priv->max_gmr_ids =
 492                         vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
 493         }
 494         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 495                 dev_priv->max_gmr_pages =
 496                         vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
 497                 dev_priv->memory_size =
 498                         vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
 499                 dev_priv->memory_size -= dev_priv->vram_size;
 500         } else {
 501                 /*
 502                  * An arbitrary limit of 512MiB on surface
 503                  * memory. But all HWV8 hardware supports GMR2.
 504                  */
 505                 dev_priv->memory_size = 512*1024*1024;
 506         }
 507
 508         mutex_unlock(&dev_priv->hw_mutex);
 509
 510         vmw_print_capabilities(dev_priv->capabilities);
 511
 512         if (dev_priv->capabilities & SVGA_CAP_GMR) {
 513                 DRM_INFO("Max GMR ids is %u\n",
 514                          (unsigned)dev_priv->max_gmr_ids);
 515                 DRM_INFO("Max GMR descriptors is %u\n",
 516                          (unsigned)dev_priv->max_gmr_descriptors);
 517         }
 518         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 519                 DRM_INFO("Max number of GMR pages is %u\n",
 520                          (unsigned)dev_priv->max_gmr_pages);
 521                 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
 522                          (unsigned)dev_priv->memory_size / 1024);
 523         }
 524         DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
 525                  dev_priv->vram_start, dev_priv->vram_size / 1024);
 526         DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
 527                  dev_priv->mmio_start, dev_priv->mmio_size / 1024);
 528
 529         ret = vmw_ttm_global_init(dev_priv);
 530         if (unlikely(ret != 0))
 531                 goto out_err0;
 532
 533
 534         vmw_master_init(&dev_priv->fbdev_master);
 535         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
 536         dev_priv->active_master = &dev_priv->fbdev_master;
 537
 538
 539         ret = ttm_bo_device_init(&dev_priv->bdev,
 540                                  dev_priv->bo_global_ref.ref.object,
 541                                  &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET,
 542                                  false);
 543         if (unlikely(ret != 0)) {
 544                 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
 545                 goto out_err1;
 546         }
 547
 548         ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
 549                              (dev_priv->vram_size >> PAGE_SHIFT));
 550         if (unlikely(ret != 0)) {
 551                 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
 552                 goto out_err2;
 553         }
 554
 555         dev_priv->has_gmr = true;
 556         if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
 557                            dev_priv->max_gmr_ids) != 0) {
 558                 DRM_INFO("No GMR memory available. "
 559                          "Graphics memory resources are very limited.\n");
 560                 dev_priv->has_gmr = false;
 561         }
 562
 563         dev_priv->mmio_mtrr = drm_mtrr_add(dev_priv->mmio_start,
 564                                            dev_priv->mmio_size, DRM_MTRR_WC);
 565
 566         dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
 567                                          dev_priv->mmio_size);
 568
 569         if (unlikely(dev_priv->mmio_virt == NULL)) {
 570                 ret = -ENOMEM;
 571                 DRM_ERROR("Failed mapping MMIO.\n");
 572                 goto out_err3;
 573         }
 574
 575         /* Need mmio memory to check for fifo pitchlock cap. */
 576         if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
 577             !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
 578             !vmw_fifo_have_pitchlock(dev_priv)) {
 579                 ret = -ENOSYS;
 580                 DRM_ERROR("Hardware has no pitchlock\n");
 581                 goto out_err4;
 582         }
 583
 584         dev_priv->tdev = ttm_object_device_init
 585             (dev_priv->mem_global_ref.object, 12);
 586
 587         if (unlikely(dev_priv->tdev == NULL)) {
 588                 DRM_ERROR("Unable to initialize TTM object management.\n");
 589                 ret = -ENOMEM;
 590                 goto out_err4;
 591         }
 592
 593         dev->dev_private = dev_priv;
 594
 595         ret = pci_request_regions(dev->pdev, "vmwgfx probe");
 596         dev_priv->stealth = (ret != 0);
 597         if (dev_priv->stealth) {
 598                 /**
 599                  * Request at least the mmio PCI resource.
 600                  */
 601
 602                 DRM_INFO("It appears like vesafb is loaded. "
 603                          "Ignore above error if any.\n");
 604                 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
 605                 if (unlikely(ret != 0)) {
 606                         DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
 607                         goto out_no_device;
 608                 }
 609         }
 610
 611         dev_priv->fman = vmw_fence_manager_init(dev_priv);
 612         if (unlikely(dev_priv->fman == NULL))
 613                 goto out_no_fman;
 614
 615         /* Need to start the fifo to check if we can do screen objects */
 616         ret = vmw_3d_resource_inc(dev_priv, true);
 617         if (unlikely(ret != 0))
 618                 goto out_no_fifo;
 619         vmw_kms_save_vga(dev_priv);
 620
 621         /* Start kms and overlay systems, needs fifo. */
 622         ret = vmw_kms_init(dev_priv);
 623         if (unlikely(ret != 0))
 624                 goto out_no_kms;
 625         vmw_overlay_init(dev_priv);
 626
 627         /* 3D Depends on Screen Objects being used. */
 628         DRM_INFO("Detected %sdevice 3D availability.\n",
 629                  vmw_fifo_have_3d(dev_priv) ?
 630                  "" : "no ");
 631
 632         /* We might be done with the fifo now */
 633         if (dev_priv->enable_fb) {
 634                 vmw_fb_init(dev_priv);
 635         } else {
 636                 vmw_kms_restore_vga(dev_priv);
 637                 vmw_3d_resource_dec(dev_priv, true);
 638         }
 639
 640         if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
 641                 ret = drm_irq_install(dev);
 642                 if (unlikely(ret != 0)) {
 643                         DRM_ERROR("Failed installing irq: %d\n", ret);
 644                         goto out_no_irq;
 645                 }
 646         }
 647
 648         dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
 649         register_pm_notifier(&dev_priv->pm_nb);
 650
 651         return 0;
 652
 653 out_no_irq:
 654         if (dev_priv->enable_fb)
 655                 vmw_fb_close(dev_priv);
 656         vmw_overlay_close(dev_priv);
 657         vmw_kms_close(dev_priv);
 658 out_no_kms:
 659         /* We still have a 3D resource reference held */
 660         if (dev_priv->enable_fb) {
 661                 vmw_kms_restore_vga(dev_priv);
 662                 vmw_3d_resource_dec(dev_priv, false);
 663         }
 664 out_no_fifo:
 665         vmw_fence_manager_takedown(dev_priv->fman);
 666 out_no_fman:
 667         if (dev_priv->stealth)
 668                 pci_release_region(dev->pdev, 2);
 669         else
 670                 pci_release_regions(dev->pdev);
 671 out_no_device:
 672         ttm_object_device_release(&dev_priv->tdev);
 673 out_err4:
 674         iounmap(dev_priv->mmio_virt);
 675 out_err3:
 676         drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
 677                      dev_priv->mmio_size, DRM_MTRR_WC);
 678         if (dev_priv->has_gmr)
 679                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
 680         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
 681 out_err2:
 682         (void)ttm_bo_device_release(&dev_priv->bdev);
 683 out_err1:
 684         vmw_ttm_global_release(dev_priv);
 685 out_err0:
 686         idr_destroy(&dev_priv->surface_idr);
 687         idr_destroy(&dev_priv->context_idr);
 688         idr_destroy(&dev_priv->stream_idr);
 689         kfree(dev_priv);
 690         return ret;
 691 }
 692
 693 static int vmw_driver_unload(struct drm_device *dev)
 694 {
 695         struct vmw_private *dev_priv = vmw_priv(dev);
 696
 697         unregister_pm_notifier(&dev_priv->pm_nb);
 698
 699         if (dev_priv->ctx.cmd_bounce)
 700                 vfree(dev_priv->ctx.cmd_bounce);
 701         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
 702                 drm_irq_uninstall(dev_priv->dev);
 703         if (dev_priv->enable_fb) {
 704                 vmw_fb_close(dev_priv);
 705                 vmw_kms_restore_vga(dev_priv);
 706                 vmw_3d_resource_dec(dev_priv, false);
 707         }
 708         vmw_kms_close(dev_priv);
 709         vmw_overlay_close(dev_priv);
 710         vmw_fence_manager_takedown(dev_priv->fman);
 711         if (dev_priv->stealth)
 712                 pci_release_region(dev->pdev, 2);
 713         else
 714                 pci_release_regions(dev->pdev);
 715
 716         ttm_object_device_release(&dev_priv->tdev);
 717         iounmap(dev_priv->mmio_virt);
 718         drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
 719                      dev_priv->mmio_size, DRM_MTRR_WC);
 720         if (dev_priv->has_gmr)
 721                 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
 722         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
 723         (void)ttm_bo_device_release(&dev_priv->bdev);
 724         vmw_ttm_global_release(dev_priv);
 725         idr_destroy(&dev_priv->surface_idr);
 726         idr_destroy(&dev_priv->context_idr);
 727         idr_destroy(&dev_priv->stream_idr);
 728
 729         kfree(dev_priv);
 730
 731         return 0;
 732 }
 733
 734 static void vmw_preclose(struct drm_device *dev,
 735                          struct drm_file *file_priv)
 736 {
 737         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
 738         struct vmw_private *dev_priv = vmw_priv(dev);
 739
 740         vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events);
 741 }
 742
 743 static void vmw_postclose(struct drm_device *dev,
 744                          struct drm_file *file_priv)
 745 {
 746         struct vmw_fpriv *vmw_fp;
 747
 748         vmw_fp = vmw_fpriv(file_priv);
 749         ttm_object_file_release(&vmw_fp->tfile);
 750         if (vmw_fp->locked_master)
 751                 drm_master_put(&vmw_fp->locked_master);
 752         kfree(vmw_fp);
 753 }
 754
 755 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
 756 {
 757         struct vmw_private *dev_priv = vmw_priv(dev);
 758         struct vmw_fpriv *vmw_fp;
 759         int ret = -ENOMEM;
 760
 761         vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
 762         if (unlikely(vmw_fp == NULL))
 763                 return ret;
 764
 765         INIT_LIST_HEAD(&vmw_fp->fence_events);
 766         vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
 767         if (unlikely(vmw_fp->tfile == NULL))
 768                 goto out_no_tfile;
 769
 770         file_priv->driver_priv = vmw_fp;
 771         dev_priv->bdev.dev_mapping = dev->dev_mapping;
 772
 773         return 0;
 774
 775 out_no_tfile:
 776         kfree(vmw_fp);
 777         return ret;
 778 }
 779
 780 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
 781                                unsigned long arg)
 782 {
 783         struct drm_file *file_priv = filp->private_data;
 784         struct drm_device *dev = file_priv->minor->dev;
 785         unsigned int nr = DRM_IOCTL_NR(cmd);
 786
 787         /*
 788          * Do extra checking on driver private ioctls.
 789          */
 790
 791         if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
 792             && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
 793                 struct drm_ioctl_desc *ioctl =
 794                     &vmw_ioctls[nr - DRM_COMMAND_BASE];
 795
 796                 if (unlikely(ioctl->cmd_drv != cmd)) {
 797                         DRM_ERROR("Invalid command format, ioctl %d\n",
 798                                   nr - DRM_COMMAND_BASE);
 799                         return -EINVAL;
 800                 }
 801         }
 802
 803         return drm_ioctl(filp, cmd, arg);
 804 }
 805
 806 static int vmw_firstopen(struct drm_device *dev)
 807 {
 808         struct vmw_private *dev_priv = vmw_priv(dev);
 809         dev_priv->is_opened = true;
 810
 811         return 0;
 812 }
 813
 814 static void vmw_lastclose(struct drm_device *dev)
 815 {
 816         struct vmw_private *dev_priv = vmw_priv(dev);
 817         struct drm_crtc *crtc;
 818         struct drm_mode_set set;
 819         int ret;
 820
 821         /**
 822          * Do nothing on the lastclose call from drm_unload.
 823          */
 824
 825         if (!dev_priv->is_opened)
 826                 return;
 827
 828         dev_priv->is_opened = false;
 829         set.x = 0;
 830         set.y = 0;
 831         set.fb = NULL;
 832         set.mode = NULL;
 833         set.connectors = NULL;
 834         set.num_connectors = 0;
 835
 836         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 837                 set.crtc = crtc;
 838                 ret = crtc->funcs->set_config(&set);
 839                 WARN_ON(ret != 0);
 840         }
 841
 842 }
 843
 844 static void vmw_master_init(struct vmw_master *vmaster)
 845 {
 846         ttm_lock_init(&vmaster->lock);
 847         INIT_LIST_HEAD(&vmaster->fb_surf);
 848         mutex_init(&vmaster->fb_surf_mutex);
 849 }
 850
 851 static int vmw_master_create(struct drm_device *dev,
 852                              struct drm_master *master)
 853 {
 854         struct vmw_master *vmaster;
 855
 856         vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
 857         if (unlikely(vmaster == NULL))
 858                 return -ENOMEM;
 859
 860         vmw_master_init(vmaster);
 861         ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
 862         master->driver_priv = vmaster;
 863
 864         return 0;
 865 }
 866
 867 static void vmw_master_destroy(struct drm_device *dev,
 868                                struct drm_master *master)
 869 {
 870         struct vmw_master *vmaster = vmw_master(master);
 871
 872         master->driver_priv = NULL;
 873         kfree(vmaster);
 874 }
 875
 876
 877 static int vmw_master_set(struct drm_device *dev,
 878                           struct drm_file *file_priv,
 879                           bool from_open)
 880 {
 881         struct vmw_private *dev_priv = vmw_priv(dev);
 882         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
 883         struct vmw_master *active = dev_priv->active_master;
 884         struct vmw_master *vmaster = vmw_master(file_priv->master);
 885         int ret = 0;
 886
 887         if (!dev_priv->enable_fb) {
 888                 ret = vmw_3d_resource_inc(dev_priv, true);
 889                 if (unlikely(ret != 0))
 890                         return ret;
 891                 vmw_kms_save_vga(dev_priv);
 892                 mutex_lock(&dev_priv->hw_mutex);
 893                 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
 894                 mutex_unlock(&dev_priv->hw_mutex);
 895         }
 896
 897         if (active) {
 898                 BUG_ON(active != &dev_priv->fbdev_master);
 899                 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
 900                 if (unlikely(ret != 0))
 901                         goto out_no_active_lock;
 902
 903                 ttm_lock_set_kill(&active->lock, true, SIGTERM);
 904                 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
 905                 if (unlikely(ret != 0)) {
 906                         DRM_ERROR("Unable to clean VRAM on "
 907                                   "master drop.\n");
 908                 }
 909
 910                 dev_priv->active_master = NULL;
 911         }
 912
 913         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
 914         if (!from_open) {
 915                 ttm_vt_unlock(&vmaster->lock);
 916                 BUG_ON(vmw_fp->locked_master != file_priv->master);
 917                 drm_master_put(&vmw_fp->locked_master);
 918         }
 919
 920         dev_priv->active_master = vmaster;
 921
 922         return 0;
 923
 924 out_no_active_lock:
 925         if (!dev_priv->enable_fb) {
 926                 mutex_lock(&dev_priv->hw_mutex);
 927                 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
 928                 mutex_unlock(&dev_priv->hw_mutex);
 929                 vmw_kms_restore_vga(dev_priv);
 930                 vmw_3d_resource_dec(dev_priv, true);
 931         }
 932         return ret;
 933 }
 934
 935 static void vmw_master_drop(struct drm_device *dev,
 936                             struct drm_file *file_priv,
 937                             bool from_release)
 938 {
 939         struct vmw_private *dev_priv = vmw_priv(dev);
 940         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
 941         struct vmw_master *vmaster = vmw_master(file_priv->master);
 942         int ret;
 943
 944         /**
 945          * Make sure the master doesn't disappear while we have
 946          * it locked.
 947          */
 948
 949         vmw_fp->locked_master = drm_master_get(file_priv->master);
 950         ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
 951         vmw_execbuf_release_pinned_bo(dev_priv, false, 0);
 952
 953         if (unlikely((ret != 0))) {
 954                 DRM_ERROR("Unable to lock TTM at VT switch.\n");
 955                 drm_master_put(&vmw_fp->locked_master);
 956         }
 957
 958         ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
 959
 960         if (!dev_priv->enable_fb) {
 961                 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
 962                 if (unlikely(ret != 0))
 963                         DRM_ERROR("Unable to clean VRAM on master drop.\n");
 964                 mutex_lock(&dev_priv->hw_mutex);
 965                 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
 966                 mutex_unlock(&dev_priv->hw_mutex);
 967                 vmw_kms_restore_vga(dev_priv);
 968                 vmw_3d_resource_dec(dev_priv, true);
 969         }
 970
 971         dev_priv->active_master = &dev_priv->fbdev_master;
 972         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
 973         ttm_vt_unlock(&dev_priv->fbdev_master.lock);
 974
 975         if (dev_priv->enable_fb)
 976                 vmw_fb_on(dev_priv);
 977 }
 978
 979
 980 static void vmw_remove(struct pci_dev *pdev)
 981 {
 982         struct drm_device *dev = pci_get_drvdata(pdev);
 983
 984         drm_put_dev(dev);
 985 }
 986
 987 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
 988                               void *ptr)
 989 {
 990         struct vmw_private *dev_priv =
 991                 container_of(nb, struct vmw_private, pm_nb);
 992         struct vmw_master *vmaster = dev_priv->active_master;
 993
 994         switch (val) {
 995         case PM_HIBERNATION_PREPARE:
 996         case PM_SUSPEND_PREPARE:
 997                 ttm_suspend_lock(&vmaster->lock);
 998
 999                 /**
1000                  * This empties VRAM and unbinds all GMR bindings.
1001                  * Buffer contents is moved to swappable memory.
1002                  */
1003                 vmw_execbuf_release_pinned_bo(dev_priv, false, 0);
1004                 ttm_bo_swapout_all(&dev_priv->bdev);
1005
1006                 break;
1007         case PM_POST_HIBERNATION:
1008         case PM_POST_SUSPEND:
1009         case PM_POST_RESTORE:
1010                 ttm_suspend_unlock(&vmaster->lock);
1011
1012                 break;
1013         case PM_RESTORE_PREPARE:
1014                 break;
1015         default:
1016                 break;
1017         }
1018         return 0;
1019 }
1020
1021 /**
1022  * These might not be needed with the virtual SVGA device.
1023  */
1024
1025 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1026 {
1027         struct drm_device *dev = pci_get_drvdata(pdev);
1028         struct vmw_private *dev_priv = vmw_priv(dev);
1029
1030         if (dev_priv->num_3d_resources != 0) {
1031                 DRM_INFO("Can't suspend or hibernate "
1032                          "while 3D resources are active.\n");
1033                 return -EBUSY;
1034         }
1035
1036         pci_save_state(pdev);
1037         pci_disable_device(pdev);
1038         pci_set_power_state(pdev, PCI_D3hot);
1039         return 0;
1040 }
1041
1042 static int vmw_pci_resume(struct pci_dev *pdev)
1043 {
1044         pci_set_power_state(pdev, PCI_D0);
1045         pci_restore_state(pdev);
1046         return pci_enable_device(pdev);
1047 }
1048
1049 static int vmw_pm_suspend(struct device *kdev)
1050 {
1051         struct pci_dev *pdev = to_pci_dev(kdev);
1052         struct pm_message dummy;
1053
1054         dummy.event = 0;
1055
1056         return vmw_pci_suspend(pdev, dummy);
1057 }
1058
1059 static int vmw_pm_resume(struct device *kdev)
1060 {
1061         struct pci_dev *pdev = to_pci_dev(kdev);
1062
1063         return vmw_pci_resume(pdev);
1064 }
1065
1066 static int vmw_pm_prepare(struct device *kdev)
1067 {
1068         struct pci_dev *pdev = to_pci_dev(kdev);
1069         struct drm_device *dev = pci_get_drvdata(pdev);
1070         struct vmw_private *dev_priv = vmw_priv(dev);
1071
1072         /**
1073          * Release 3d reference held by fbdev and potentially
1074          * stop fifo.
1075          */
1076         dev_priv->suspended = true;
1077         if (dev_priv->enable_fb)
1078                         vmw_3d_resource_dec(dev_priv, true);
1079
1080         if (dev_priv->num_3d_resources != 0) {
1081
1082                 DRM_INFO("Can't suspend or hibernate "
1083                          "while 3D resources are active.\n");
1084
1085                 if (dev_priv->enable_fb)
1086                         vmw_3d_resource_inc(dev_priv, true);
1087                 dev_priv->suspended = false;
1088                 return -EBUSY;
1089         }
1090
1091         return 0;
1092 }
1093
1094 static void vmw_pm_complete(struct device *kdev)
1095 {
1096         struct pci_dev *pdev = to_pci_dev(kdev);
1097         struct drm_device *dev = pci_get_drvdata(pdev);
1098         struct vmw_private *dev_priv = vmw_priv(dev);
1099
1100         /**
1101          * Reclaim 3d reference held by fbdev and potentially
1102          * start fifo.
1103          */
1104         if (dev_priv->enable_fb)
1105                         vmw_3d_resource_inc(dev_priv, false);
1106
1107         dev_priv->suspended = false;
1108 }
1109
1110 static const struct dev_pm_ops vmw_pm_ops = {
1111         .prepare = vmw_pm_prepare,
1112         .complete = vmw_pm_complete,
1113         .suspend = vmw_pm_suspend,
1114         .resume = vmw_pm_resume,
1115 };
1116
1117 static const struct file_operations vmwgfx_driver_fops = {
1118         .owner = THIS_MODULE,
1119         .open = drm_open,
1120         .release = drm_release,
1121         .unlocked_ioctl = vmw_unlocked_ioctl,
1122         .mmap = vmw_mmap,
1123         .poll = vmw_fops_poll,
1124         .read = vmw_fops_read,
1125         .fasync = drm_fasync,
1126 #if defined(CONFIG_COMPAT)
1127         .compat_ioctl = drm_compat_ioctl,
1128 #endif
1129         .llseek = noop_llseek,
1130 };
1131
1132 static struct drm_driver driver = {
1133         .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1134         DRIVER_MODESET,
1135         .load = vmw_driver_load,
1136         .unload = vmw_driver_unload,
1137         .firstopen = vmw_firstopen,
1138         .lastclose = vmw_lastclose,
1139         .irq_preinstall = vmw_irq_preinstall,
1140         .irq_postinstall = vmw_irq_postinstall,
1141         .irq_uninstall = vmw_irq_uninstall,
1142         .irq_handler = vmw_irq_handler,
1143         .get_vblank_counter = vmw_get_vblank_counter,
1144         .enable_vblank = vmw_enable_vblank,
1145         .disable_vblank = vmw_disable_vblank,
1146         .ioctls = vmw_ioctls,
1147         .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
1148         .dma_quiescent = NULL,  /*vmw_dma_quiescent, */
1149         .master_create = vmw_master_create,
1150         .master_destroy = vmw_master_destroy,
1151         .master_set = vmw_master_set,
1152         .master_drop = vmw_master_drop,
1153         .open = vmw_driver_open,
1154         .preclose = vmw_preclose,
1155         .postclose = vmw_postclose,
1156         .fops = &vmwgfx_driver_fops,
1157         .name = VMWGFX_DRIVER_NAME,
1158         .desc = VMWGFX_DRIVER_DESC,
1159         .date = VMWGFX_DRIVER_DATE,
1160         .major = VMWGFX_DRIVER_MAJOR,
1161         .minor = VMWGFX_DRIVER_MINOR,
1162         .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1163 };
1164
1165 static struct pci_driver vmw_pci_driver = {
1166         .name = VMWGFX_DRIVER_NAME,
1167         .id_table = vmw_pci_id_list,
1168         .probe = vmw_probe,
1169         .remove = vmw_remove,
1170         .driver = {
1171                 .pm = &vmw_pm_ops
1172         }
1173 };
1174
1175 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1176 {
1177         return drm_get_pci_dev(pdev, ent, &driver);
1178 }
1179
1180 static int __init vmwgfx_init(void)
1181 {
1182         int ret;
1183         ret = drm_pci_init(&driver, &vmw_pci_driver);
1184         if (ret)
1185                 DRM_ERROR("Failed initializing DRM.\n");
1186         return ret;
1187 }
1188
1189 static void __exit vmwgfx_exit(void)
1190 {
1191         drm_pci_exit(&driver, &vmw_pci_driver);
1192 }
1193
1194 module_init(vmwgfx_init);
1195 module_exit(vmwgfx_exit);
1196
1197 MODULE_AUTHOR("VMware Inc. and others");
1198 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1199 MODULE_LICENSE("GPL and additional rights");
1200 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1201                __stringify(VMWGFX_DRIVER_MINOR) "."
1202                __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1203                "0");