1 /**************************************************************************
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
27 #include <linux/module.h>
30 #include "vmwgfx_drv.h"
31 #include <drm/ttm/ttm_placement.h>
32 #include <drm/ttm/ttm_bo_driver.h>
33 #include <drm/ttm/ttm_object.h>
34 #include <drm/ttm/ttm_module.h>
35 #include <linux/dma_remapping.h>
37 #define VMWGFX_DRIVER_NAME "vmwgfx"
38 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
39 #define VMWGFX_CHIP_SVGAII 0
40 #define VMW_FB_RESERVATION 0
42 #define VMW_MIN_INITIAL_WIDTH 800
43 #define VMW_MIN_INITIAL_HEIGHT 600
47 * Fully encoded drm commands. Might move to vmw_drm.h
50 #define DRM_IOCTL_VMW_GET_PARAM \
51 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
52 struct drm_vmw_getparam_arg)
53 #define DRM_IOCTL_VMW_ALLOC_DMABUF \
54 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
55 union drm_vmw_alloc_dmabuf_arg)
56 #define DRM_IOCTL_VMW_UNREF_DMABUF \
57 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
58 struct drm_vmw_unref_dmabuf_arg)
59 #define DRM_IOCTL_VMW_CURSOR_BYPASS \
60 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
61 struct drm_vmw_cursor_bypass_arg)
63 #define DRM_IOCTL_VMW_CONTROL_STREAM \
64 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
65 struct drm_vmw_control_stream_arg)
66 #define DRM_IOCTL_VMW_CLAIM_STREAM \
67 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
68 struct drm_vmw_stream_arg)
69 #define DRM_IOCTL_VMW_UNREF_STREAM \
70 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
71 struct drm_vmw_stream_arg)
73 #define DRM_IOCTL_VMW_CREATE_CONTEXT \
74 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
75 struct drm_vmw_context_arg)
76 #define DRM_IOCTL_VMW_UNREF_CONTEXT \
77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
78 struct drm_vmw_context_arg)
79 #define DRM_IOCTL_VMW_CREATE_SURFACE \
80 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
81 union drm_vmw_surface_create_arg)
82 #define DRM_IOCTL_VMW_UNREF_SURFACE \
83 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
84 struct drm_vmw_surface_arg)
85 #define DRM_IOCTL_VMW_REF_SURFACE \
86 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
87 union drm_vmw_surface_reference_arg)
88 #define DRM_IOCTL_VMW_EXECBUF \
89 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
90 struct drm_vmw_execbuf_arg)
91 #define DRM_IOCTL_VMW_GET_3D_CAP \
92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
93 struct drm_vmw_get_3d_cap_arg)
94 #define DRM_IOCTL_VMW_FENCE_WAIT \
95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
96 struct drm_vmw_fence_wait_arg)
97 #define DRM_IOCTL_VMW_FENCE_SIGNALED \
98 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
99 struct drm_vmw_fence_signaled_arg)
100 #define DRM_IOCTL_VMW_FENCE_UNREF \
101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
102 struct drm_vmw_fence_arg)
103 #define DRM_IOCTL_VMW_FENCE_EVENT \
104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
105 struct drm_vmw_fence_event_arg)
106 #define DRM_IOCTL_VMW_PRESENT \
107 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
108 struct drm_vmw_present_arg)
109 #define DRM_IOCTL_VMW_PRESENT_READBACK \
110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
111 struct drm_vmw_present_readback_arg)
112 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \
113 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
114 struct drm_vmw_update_layout_arg)
117 * The core DRM version of this macro doesn't account for
121 #define VMW_IOCTL_DEF(ioctl, func, flags) \
122 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
128 static const struct drm_ioctl_desc vmw_ioctls
[] = {
129 VMW_IOCTL_DEF(VMW_GET_PARAM
, vmw_getparam_ioctl
,
130 DRM_AUTH
| DRM_UNLOCKED
),
131 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF
, vmw_dmabuf_alloc_ioctl
,
132 DRM_AUTH
| DRM_UNLOCKED
),
133 VMW_IOCTL_DEF(VMW_UNREF_DMABUF
, vmw_dmabuf_unref_ioctl
,
134 DRM_AUTH
| DRM_UNLOCKED
),
135 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS
,
136 vmw_kms_cursor_bypass_ioctl
,
137 DRM_MASTER
| DRM_CONTROL_ALLOW
| DRM_UNLOCKED
),
139 VMW_IOCTL_DEF(VMW_CONTROL_STREAM
, vmw_overlay_ioctl
,
140 DRM_MASTER
| DRM_CONTROL_ALLOW
| DRM_UNLOCKED
),
141 VMW_IOCTL_DEF(VMW_CLAIM_STREAM
, vmw_stream_claim_ioctl
,
142 DRM_MASTER
| DRM_CONTROL_ALLOW
| DRM_UNLOCKED
),
143 VMW_IOCTL_DEF(VMW_UNREF_STREAM
, vmw_stream_unref_ioctl
,
144 DRM_MASTER
| DRM_CONTROL_ALLOW
| DRM_UNLOCKED
),
146 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT
, vmw_context_define_ioctl
,
147 DRM_AUTH
| DRM_UNLOCKED
),
148 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT
, vmw_context_destroy_ioctl
,
149 DRM_AUTH
| DRM_UNLOCKED
),
150 VMW_IOCTL_DEF(VMW_CREATE_SURFACE
, vmw_surface_define_ioctl
,
151 DRM_AUTH
| DRM_UNLOCKED
),
152 VMW_IOCTL_DEF(VMW_UNREF_SURFACE
, vmw_surface_destroy_ioctl
,
153 DRM_AUTH
| DRM_UNLOCKED
),
154 VMW_IOCTL_DEF(VMW_REF_SURFACE
, vmw_surface_reference_ioctl
,
155 DRM_AUTH
| DRM_UNLOCKED
),
156 VMW_IOCTL_DEF(VMW_EXECBUF
, vmw_execbuf_ioctl
,
157 DRM_AUTH
| DRM_UNLOCKED
),
158 VMW_IOCTL_DEF(VMW_FENCE_WAIT
, vmw_fence_obj_wait_ioctl
,
159 DRM_AUTH
| DRM_UNLOCKED
),
160 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED
,
161 vmw_fence_obj_signaled_ioctl
,
162 DRM_AUTH
| DRM_UNLOCKED
),
163 VMW_IOCTL_DEF(VMW_FENCE_UNREF
, vmw_fence_obj_unref_ioctl
,
164 DRM_AUTH
| DRM_UNLOCKED
),
165 VMW_IOCTL_DEF(VMW_FENCE_EVENT
,
166 vmw_fence_event_ioctl
,
167 DRM_AUTH
| DRM_UNLOCKED
),
168 VMW_IOCTL_DEF(VMW_GET_3D_CAP
, vmw_get_cap_3d_ioctl
,
169 DRM_AUTH
| DRM_UNLOCKED
),
171 /* these allow direct access to the framebuffers mark as master only */
172 VMW_IOCTL_DEF(VMW_PRESENT
, vmw_present_ioctl
,
173 DRM_MASTER
| DRM_AUTH
| DRM_UNLOCKED
),
174 VMW_IOCTL_DEF(VMW_PRESENT_READBACK
,
175 vmw_present_readback_ioctl
,
176 DRM_MASTER
| DRM_AUTH
| DRM_UNLOCKED
),
177 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT
,
178 vmw_kms_update_layout_ioctl
,
179 DRM_MASTER
| DRM_UNLOCKED
),
182 static struct pci_device_id vmw_pci_id_list
[] = {
183 {0x15ad, 0x0405, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, VMWGFX_CHIP_SVGAII
},
186 MODULE_DEVICE_TABLE(pci
, vmw_pci_id_list
);
188 static int enable_fbdev
= IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON
);
189 static int vmw_force_iommu
;
190 static int vmw_restrict_iommu
;
191 static int vmw_force_coherent
;
193 static int vmw_probe(struct pci_dev
*, const struct pci_device_id
*);
194 static void vmw_master_init(struct vmw_master
*);
195 static int vmwgfx_pm_notifier(struct notifier_block
*nb
, unsigned long val
,
198 MODULE_PARM_DESC(enable_fbdev
, "Enable vmwgfx fbdev");
199 module_param_named(enable_fbdev
, enable_fbdev
, int, 0600);
200 MODULE_PARM_DESC(force_dma_api
, "Force using the DMA API for TTM pages");
201 module_param_named(force_dma_api
, vmw_force_iommu
, int, 0600);
202 MODULE_PARM_DESC(restrict_iommu
, "Try to limit IOMMU usage for TTM pages");
203 module_param_named(restrict_iommu
, vmw_restrict_iommu
, int, 0600);
204 MODULE_PARM_DESC(force_coherent
, "Force coherent TTM pages");
205 module_param_named(force_coherent
, vmw_force_coherent
, int, 0600);
208 static void vmw_print_capabilities(uint32_t capabilities
)
210 DRM_INFO("Capabilities:\n");
211 if (capabilities
& SVGA_CAP_RECT_COPY
)
212 DRM_INFO(" Rect copy.\n");
213 if (capabilities
& SVGA_CAP_CURSOR
)
214 DRM_INFO(" Cursor.\n");
215 if (capabilities
& SVGA_CAP_CURSOR_BYPASS
)
216 DRM_INFO(" Cursor bypass.\n");
217 if (capabilities
& SVGA_CAP_CURSOR_BYPASS_2
)
218 DRM_INFO(" Cursor bypass 2.\n");
219 if (capabilities
& SVGA_CAP_8BIT_EMULATION
)
220 DRM_INFO(" 8bit emulation.\n");
221 if (capabilities
& SVGA_CAP_ALPHA_CURSOR
)
222 DRM_INFO(" Alpha cursor.\n");
223 if (capabilities
& SVGA_CAP_3D
)
225 if (capabilities
& SVGA_CAP_EXTENDED_FIFO
)
226 DRM_INFO(" Extended Fifo.\n");
227 if (capabilities
& SVGA_CAP_MULTIMON
)
228 DRM_INFO(" Multimon.\n");
229 if (capabilities
& SVGA_CAP_PITCHLOCK
)
230 DRM_INFO(" Pitchlock.\n");
231 if (capabilities
& SVGA_CAP_IRQMASK
)
232 DRM_INFO(" Irq mask.\n");
233 if (capabilities
& SVGA_CAP_DISPLAY_TOPOLOGY
)
234 DRM_INFO(" Display Topology.\n");
235 if (capabilities
& SVGA_CAP_GMR
)
237 if (capabilities
& SVGA_CAP_TRACES
)
238 DRM_INFO(" Traces.\n");
239 if (capabilities
& SVGA_CAP_GMR2
)
240 DRM_INFO(" GMR2.\n");
241 if (capabilities
& SVGA_CAP_SCREEN_OBJECT_2
)
242 DRM_INFO(" Screen Object 2.\n");
247 * vmw_execbuf_prepare_dummy_query - Initialize a query result structure at
248 * the start of a buffer object.
250 * @dev_priv: The device private structure.
252 * This function will idle the buffer using an uninterruptible wait, then
253 * map the first page and initialize a pending occlusion query result structure,
254 * Finally it will unmap the buffer.
256 * TODO: Since we're only mapping a single page, we should optimize the map
257 * to use kmap_atomic / iomap_atomic.
259 static void vmw_dummy_query_bo_prepare(struct vmw_private
*dev_priv
)
261 struct ttm_bo_kmap_obj map
;
262 volatile SVGA3dQueryResult
*result
;
265 struct ttm_bo_device
*bdev
= &dev_priv
->bdev
;
266 struct ttm_buffer_object
*bo
= dev_priv
->dummy_query_bo
;
268 ttm_bo_reserve(bo
, false, false, false, 0);
269 spin_lock(&bdev
->fence_lock
);
270 ret
= ttm_bo_wait(bo
, false, false, false);
271 spin_unlock(&bdev
->fence_lock
);
272 if (unlikely(ret
!= 0))
273 (void) vmw_fallback_wait(dev_priv
, false, true, 0, false,
276 ret
= ttm_bo_kmap(bo
, 0, 1, &map
);
277 if (likely(ret
== 0)) {
278 result
= ttm_kmap_obj_virtual(&map
, &dummy
);
279 result
->totalSize
= sizeof(*result
);
280 result
->state
= SVGA3D_QUERYSTATE_PENDING
;
281 result
->result32
= 0xff;
284 DRM_ERROR("Dummy query buffer map failed.\n");
285 ttm_bo_unreserve(bo
);
290 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
292 * @dev_priv: A device private structure.
294 * This function creates a small buffer object that holds the query
295 * result for dummy queries emitted as query barriers.
296 * No interruptible waits are done within this function.
298 * Returns an error if bo creation fails.
300 static int vmw_dummy_query_bo_create(struct vmw_private
*dev_priv
)
302 return ttm_bo_create(&dev_priv
->bdev
,
305 &vmw_vram_sys_placement
,
307 &dev_priv
->dummy_query_bo
);
311 static int vmw_request_device(struct vmw_private
*dev_priv
)
315 ret
= vmw_fifo_init(dev_priv
, &dev_priv
->fifo
);
316 if (unlikely(ret
!= 0)) {
317 DRM_ERROR("Unable to initialize FIFO.\n");
320 vmw_fence_fifo_up(dev_priv
->fman
);
321 ret
= vmw_dummy_query_bo_create(dev_priv
);
322 if (unlikely(ret
!= 0))
323 goto out_no_query_bo
;
324 vmw_dummy_query_bo_prepare(dev_priv
);
329 vmw_fence_fifo_down(dev_priv
->fman
);
330 vmw_fifo_release(dev_priv
, &dev_priv
->fifo
);
334 static void vmw_release_device(struct vmw_private
*dev_priv
)
337 * Previous destructions should've released
341 BUG_ON(dev_priv
->pinned_bo
!= NULL
);
343 ttm_bo_unref(&dev_priv
->dummy_query_bo
);
344 vmw_fence_fifo_down(dev_priv
->fman
);
345 vmw_fifo_release(dev_priv
, &dev_priv
->fifo
);
349 * Increase the 3d resource refcount.
350 * If the count was prevously zero, initialize the fifo, switching to svga
351 * mode. Note that the master holds a ref as well, and may request an
352 * explicit switch to svga mode if fb is not running, using @unhide_svga.
354 int vmw_3d_resource_inc(struct vmw_private
*dev_priv
,
359 mutex_lock(&dev_priv
->release_mutex
);
360 if (unlikely(dev_priv
->num_3d_resources
++ == 0)) {
361 ret
= vmw_request_device(dev_priv
);
362 if (unlikely(ret
!= 0))
363 --dev_priv
->num_3d_resources
;
364 } else if (unhide_svga
) {
365 mutex_lock(&dev_priv
->hw_mutex
);
366 vmw_write(dev_priv
, SVGA_REG_ENABLE
,
367 vmw_read(dev_priv
, SVGA_REG_ENABLE
) &
368 ~SVGA_REG_ENABLE_HIDE
);
369 mutex_unlock(&dev_priv
->hw_mutex
);
372 mutex_unlock(&dev_priv
->release_mutex
);
377 * Decrease the 3d resource refcount.
378 * If the count reaches zero, disable the fifo, switching to vga mode.
379 * Note that the master holds a refcount as well, and may request an
380 * explicit switch to vga mode when it releases its refcount to account
381 * for the situation of an X server vt switch to VGA with 3d resources
384 void vmw_3d_resource_dec(struct vmw_private
*dev_priv
,
389 mutex_lock(&dev_priv
->release_mutex
);
390 if (unlikely(--dev_priv
->num_3d_resources
== 0))
391 vmw_release_device(dev_priv
);
392 else if (hide_svga
) {
393 mutex_lock(&dev_priv
->hw_mutex
);
394 vmw_write(dev_priv
, SVGA_REG_ENABLE
,
395 vmw_read(dev_priv
, SVGA_REG_ENABLE
) |
396 SVGA_REG_ENABLE_HIDE
);
397 mutex_unlock(&dev_priv
->hw_mutex
);
400 n3d
= (int32_t) dev_priv
->num_3d_resources
;
401 mutex_unlock(&dev_priv
->release_mutex
);
407 * Sets the initial_[width|height] fields on the given vmw_private.
409 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
410 * clamping the value to fb_max_[width|height] fields and the
411 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
412 * If the values appear to be invalid, set them to
413 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
415 static void vmw_get_initial_size(struct vmw_private
*dev_priv
)
420 width
= vmw_read(dev_priv
, SVGA_REG_WIDTH
);
421 height
= vmw_read(dev_priv
, SVGA_REG_HEIGHT
);
423 width
= max_t(uint32_t, width
, VMW_MIN_INITIAL_WIDTH
);
424 height
= max_t(uint32_t, height
, VMW_MIN_INITIAL_HEIGHT
);
426 if (width
> dev_priv
->fb_max_width
||
427 height
> dev_priv
->fb_max_height
) {
430 * This is a host error and shouldn't occur.
433 width
= VMW_MIN_INITIAL_WIDTH
;
434 height
= VMW_MIN_INITIAL_HEIGHT
;
437 dev_priv
->initial_width
= width
;
438 dev_priv
->initial_height
= height
;
442 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
445 * @dev_priv: Pointer to a struct vmw_private
447 * This functions tries to determine the IOMMU setup and what actions
448 * need to be taken by the driver to make system pages visible to the
450 * If this function decides that DMA is not possible, it returns -EINVAL.
451 * The driver may then try to disable features of the device that require
454 static int vmw_dma_select_mode(struct vmw_private
*dev_priv
)
456 static const char *names
[vmw_dma_map_max
] = {
457 [vmw_dma_phys
] = "Using physical TTM page addresses.",
458 [vmw_dma_alloc_coherent
] = "Using coherent TTM pages.",
459 [vmw_dma_map_populate
] = "Keeping DMA mappings.",
460 [vmw_dma_map_bind
] = "Giving up DMA mappings early."};
462 const struct dma_map_ops
*dma_ops
= get_dma_ops(dev_priv
->dev
->dev
);
464 #ifdef CONFIG_INTEL_IOMMU
465 if (intel_iommu_enabled
) {
466 dev_priv
->map_mode
= vmw_dma_map_populate
;
471 if (!(vmw_force_iommu
|| vmw_force_coherent
)) {
472 dev_priv
->map_mode
= vmw_dma_phys
;
473 DRM_INFO("DMA map mode: %s\n", names
[dev_priv
->map_mode
]);
477 dev_priv
->map_mode
= vmw_dma_map_populate
;
479 if (dma_ops
->sync_single_for_cpu
)
480 dev_priv
->map_mode
= vmw_dma_alloc_coherent
;
481 #ifdef CONFIG_SWIOTLB
482 if (swiotlb_nr_tbl() == 0)
483 dev_priv
->map_mode
= vmw_dma_map_populate
;
486 #ifdef CONFIG_INTEL_IOMMU
489 if (dev_priv
->map_mode
== vmw_dma_map_populate
&&
491 dev_priv
->map_mode
= vmw_dma_map_bind
;
493 if (vmw_force_coherent
)
494 dev_priv
->map_mode
= vmw_dma_alloc_coherent
;
496 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
498 * No coherent page pool
500 if (dev_priv
->map_mode
== vmw_dma_alloc_coherent
)
504 #else /* CONFIG_X86 */
505 dev_priv
->map_mode
= vmw_dma_map_populate
;
506 #endif /* CONFIG_X86 */
508 DRM_INFO("DMA map mode: %s\n", names
[dev_priv
->map_mode
]);
513 static int vmw_driver_load(struct drm_device
*dev
, unsigned long chipset
)
515 struct vmw_private
*dev_priv
;
519 bool refuse_dma
= false;
521 dev_priv
= kzalloc(sizeof(*dev_priv
), GFP_KERNEL
);
522 if (unlikely(dev_priv
== NULL
)) {
523 DRM_ERROR("Failed allocating a device private struct.\n");
527 pci_set_master(dev
->pdev
);
530 dev_priv
->vmw_chipset
= chipset
;
531 dev_priv
->last_read_seqno
= (uint32_t) -100;
532 mutex_init(&dev_priv
->hw_mutex
);
533 mutex_init(&dev_priv
->cmdbuf_mutex
);
534 mutex_init(&dev_priv
->release_mutex
);
535 rwlock_init(&dev_priv
->resource_lock
);
537 for (i
= vmw_res_context
; i
< vmw_res_max
; ++i
) {
538 idr_init(&dev_priv
->res_idr
[i
]);
539 INIT_LIST_HEAD(&dev_priv
->res_lru
[i
]);
542 mutex_init(&dev_priv
->init_mutex
);
543 init_waitqueue_head(&dev_priv
->fence_queue
);
544 init_waitqueue_head(&dev_priv
->fifo_queue
);
545 dev_priv
->fence_queue_waiters
= 0;
546 atomic_set(&dev_priv
->fifo_queue_waiters
, 0);
548 dev_priv
->used_memory_size
= 0;
550 dev_priv
->io_start
= pci_resource_start(dev
->pdev
, 0);
551 dev_priv
->vram_start
= pci_resource_start(dev
->pdev
, 1);
552 dev_priv
->mmio_start
= pci_resource_start(dev
->pdev
, 2);
554 dev_priv
->enable_fb
= enable_fbdev
;
556 mutex_lock(&dev_priv
->hw_mutex
);
558 vmw_write(dev_priv
, SVGA_REG_ID
, SVGA_ID_2
);
559 svga_id
= vmw_read(dev_priv
, SVGA_REG_ID
);
560 if (svga_id
!= SVGA_ID_2
) {
562 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id
);
563 mutex_unlock(&dev_priv
->hw_mutex
);
567 dev_priv
->capabilities
= vmw_read(dev_priv
, SVGA_REG_CAPABILITIES
);
568 ret
= vmw_dma_select_mode(dev_priv
);
569 if (unlikely(ret
!= 0)) {
570 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
574 dev_priv
->vram_size
= vmw_read(dev_priv
, SVGA_REG_VRAM_SIZE
);
575 dev_priv
->mmio_size
= vmw_read(dev_priv
, SVGA_REG_MEM_SIZE
);
576 dev_priv
->fb_max_width
= vmw_read(dev_priv
, SVGA_REG_MAX_WIDTH
);
577 dev_priv
->fb_max_height
= vmw_read(dev_priv
, SVGA_REG_MAX_HEIGHT
);
579 vmw_get_initial_size(dev_priv
);
581 if (dev_priv
->capabilities
& SVGA_CAP_GMR
) {
582 dev_priv
->max_gmr_descriptors
=
584 SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH
);
585 dev_priv
->max_gmr_ids
=
586 vmw_read(dev_priv
, SVGA_REG_GMR_MAX_IDS
);
588 if (dev_priv
->capabilities
& SVGA_CAP_GMR2
) {
589 dev_priv
->max_gmr_pages
=
590 vmw_read(dev_priv
, SVGA_REG_GMRS_MAX_PAGES
);
591 dev_priv
->memory_size
=
592 vmw_read(dev_priv
, SVGA_REG_MEMORY_SIZE
);
593 dev_priv
->memory_size
-= dev_priv
->vram_size
;
596 * An arbitrary limit of 512MiB on surface
597 * memory. But all HWV8 hardware supports GMR2.
599 dev_priv
->memory_size
= 512*1024*1024;
602 mutex_unlock(&dev_priv
->hw_mutex
);
604 vmw_print_capabilities(dev_priv
->capabilities
);
606 if (dev_priv
->capabilities
& SVGA_CAP_GMR
) {
607 DRM_INFO("Max GMR ids is %u\n",
608 (unsigned)dev_priv
->max_gmr_ids
);
609 DRM_INFO("Max GMR descriptors is %u\n",
610 (unsigned)dev_priv
->max_gmr_descriptors
);
612 if (dev_priv
->capabilities
& SVGA_CAP_GMR2
) {
613 DRM_INFO("Max number of GMR pages is %u\n",
614 (unsigned)dev_priv
->max_gmr_pages
);
615 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
616 (unsigned)dev_priv
->memory_size
/ 1024);
618 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
619 dev_priv
->vram_start
, dev_priv
->vram_size
/ 1024);
620 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
621 dev_priv
->mmio_start
, dev_priv
->mmio_size
/ 1024);
623 ret
= vmw_ttm_global_init(dev_priv
);
624 if (unlikely(ret
!= 0))
628 vmw_master_init(&dev_priv
->fbdev_master
);
629 ttm_lock_set_kill(&dev_priv
->fbdev_master
.lock
, false, SIGTERM
);
630 dev_priv
->active_master
= &dev_priv
->fbdev_master
;
633 ret
= ttm_bo_device_init(&dev_priv
->bdev
,
634 dev_priv
->bo_global_ref
.ref
.object
,
635 &vmw_bo_driver
, VMWGFX_FILE_PAGE_OFFSET
,
637 if (unlikely(ret
!= 0)) {
638 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
642 ret
= ttm_bo_init_mm(&dev_priv
->bdev
, TTM_PL_VRAM
,
643 (dev_priv
->vram_size
>> PAGE_SHIFT
));
644 if (unlikely(ret
!= 0)) {
645 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
649 dev_priv
->has_gmr
= true;
650 if (((dev_priv
->capabilities
& (SVGA_CAP_GMR
| SVGA_CAP_GMR2
)) == 0) ||
651 refuse_dma
|| ttm_bo_init_mm(&dev_priv
->bdev
, VMW_PL_GMR
,
652 dev_priv
->max_gmr_ids
) != 0) {
653 DRM_INFO("No GMR memory available. "
654 "Graphics memory resources are very limited.\n");
655 dev_priv
->has_gmr
= false;
658 dev_priv
->mmio_mtrr
= arch_phys_wc_add(dev_priv
->mmio_start
,
659 dev_priv
->mmio_size
);
661 dev_priv
->mmio_virt
= ioremap_wc(dev_priv
->mmio_start
,
662 dev_priv
->mmio_size
);
664 if (unlikely(dev_priv
->mmio_virt
== NULL
)) {
666 DRM_ERROR("Failed mapping MMIO.\n");
670 /* Need mmio memory to check for fifo pitchlock cap. */
671 if (!(dev_priv
->capabilities
& SVGA_CAP_DISPLAY_TOPOLOGY
) &&
672 !(dev_priv
->capabilities
& SVGA_CAP_PITCHLOCK
) &&
673 !vmw_fifo_have_pitchlock(dev_priv
)) {
675 DRM_ERROR("Hardware has no pitchlock\n");
679 dev_priv
->tdev
= ttm_object_device_init
680 (dev_priv
->mem_global_ref
.object
, 12, &vmw_prime_dmabuf_ops
);
682 if (unlikely(dev_priv
->tdev
== NULL
)) {
683 DRM_ERROR("Unable to initialize TTM object management.\n");
688 dev
->dev_private
= dev_priv
;
690 ret
= pci_request_regions(dev
->pdev
, "vmwgfx probe");
691 dev_priv
->stealth
= (ret
!= 0);
692 if (dev_priv
->stealth
) {
694 * Request at least the mmio PCI resource.
697 DRM_INFO("It appears like vesafb is loaded. "
698 "Ignore above error if any.\n");
699 ret
= pci_request_region(dev
->pdev
, 2, "vmwgfx stealth probe");
700 if (unlikely(ret
!= 0)) {
701 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
706 if (dev_priv
->capabilities
& SVGA_CAP_IRQMASK
) {
707 ret
= drm_irq_install(dev
);
709 DRM_ERROR("Failed installing irq: %d\n", ret
);
714 dev_priv
->fman
= vmw_fence_manager_init(dev_priv
);
715 if (unlikely(dev_priv
->fman
== NULL
)) {
720 vmw_kms_save_vga(dev_priv
);
722 /* Start kms and overlay systems, needs fifo. */
723 ret
= vmw_kms_init(dev_priv
);
724 if (unlikely(ret
!= 0))
726 vmw_overlay_init(dev_priv
);
728 if (dev_priv
->enable_fb
) {
729 ret
= vmw_3d_resource_inc(dev_priv
, true);
730 if (unlikely(ret
!= 0))
732 vmw_fb_init(dev_priv
);
735 dev_priv
->pm_nb
.notifier_call
= vmwgfx_pm_notifier
;
736 register_pm_notifier(&dev_priv
->pm_nb
);
741 vmw_overlay_close(dev_priv
);
742 vmw_kms_close(dev_priv
);
744 vmw_kms_restore_vga(dev_priv
);
745 vmw_fence_manager_takedown(dev_priv
->fman
);
747 if (dev_priv
->capabilities
& SVGA_CAP_IRQMASK
)
748 drm_irq_uninstall(dev_priv
->dev
);
750 if (dev_priv
->stealth
)
751 pci_release_region(dev
->pdev
, 2);
753 pci_release_regions(dev
->pdev
);
755 ttm_object_device_release(&dev_priv
->tdev
);
757 iounmap(dev_priv
->mmio_virt
);
759 arch_phys_wc_del(dev_priv
->mmio_mtrr
);
760 if (dev_priv
->has_gmr
)
761 (void) ttm_bo_clean_mm(&dev_priv
->bdev
, VMW_PL_GMR
);
762 (void)ttm_bo_clean_mm(&dev_priv
->bdev
, TTM_PL_VRAM
);
764 (void)ttm_bo_device_release(&dev_priv
->bdev
);
766 vmw_ttm_global_release(dev_priv
);
768 for (i
= vmw_res_context
; i
< vmw_res_max
; ++i
)
769 idr_destroy(&dev_priv
->res_idr
[i
]);
775 static int vmw_driver_unload(struct drm_device
*dev
)
777 struct vmw_private
*dev_priv
= vmw_priv(dev
);
780 unregister_pm_notifier(&dev_priv
->pm_nb
);
782 if (dev_priv
->ctx
.res_ht_initialized
)
783 drm_ht_remove(&dev_priv
->ctx
.res_ht
);
784 if (dev_priv
->ctx
.cmd_bounce
)
785 vfree(dev_priv
->ctx
.cmd_bounce
);
786 if (dev_priv
->enable_fb
) {
787 vmw_fb_close(dev_priv
);
788 vmw_kms_restore_vga(dev_priv
);
789 vmw_3d_resource_dec(dev_priv
, false);
791 vmw_kms_close(dev_priv
);
792 vmw_overlay_close(dev_priv
);
793 vmw_fence_manager_takedown(dev_priv
->fman
);
794 if (dev_priv
->capabilities
& SVGA_CAP_IRQMASK
)
795 drm_irq_uninstall(dev_priv
->dev
);
796 if (dev_priv
->stealth
)
797 pci_release_region(dev
->pdev
, 2);
799 pci_release_regions(dev
->pdev
);
801 ttm_object_device_release(&dev_priv
->tdev
);
802 iounmap(dev_priv
->mmio_virt
);
803 arch_phys_wc_del(dev_priv
->mmio_mtrr
);
804 if (dev_priv
->has_gmr
)
805 (void)ttm_bo_clean_mm(&dev_priv
->bdev
, VMW_PL_GMR
);
806 (void)ttm_bo_clean_mm(&dev_priv
->bdev
, TTM_PL_VRAM
);
807 (void)ttm_bo_device_release(&dev_priv
->bdev
);
808 vmw_ttm_global_release(dev_priv
);
810 for (i
= vmw_res_context
; i
< vmw_res_max
; ++i
)
811 idr_destroy(&dev_priv
->res_idr
[i
]);
818 static void vmw_preclose(struct drm_device
*dev
,
819 struct drm_file
*file_priv
)
821 struct vmw_fpriv
*vmw_fp
= vmw_fpriv(file_priv
);
822 struct vmw_private
*dev_priv
= vmw_priv(dev
);
824 vmw_event_fence_fpriv_gone(dev_priv
->fman
, &vmw_fp
->fence_events
);
827 static void vmw_postclose(struct drm_device
*dev
,
828 struct drm_file
*file_priv
)
830 struct vmw_fpriv
*vmw_fp
;
832 vmw_fp
= vmw_fpriv(file_priv
);
834 if (vmw_fp
->locked_master
) {
835 struct vmw_master
*vmaster
=
836 vmw_master(vmw_fp
->locked_master
);
838 ttm_lock_set_kill(&vmaster
->lock
, true, SIGTERM
);
839 ttm_vt_unlock(&vmaster
->lock
);
840 drm_master_put(&vmw_fp
->locked_master
);
843 ttm_object_file_release(&vmw_fp
->tfile
);
847 static int vmw_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
)
849 struct vmw_private
*dev_priv
= vmw_priv(dev
);
850 struct vmw_fpriv
*vmw_fp
;
853 vmw_fp
= kzalloc(sizeof(*vmw_fp
), GFP_KERNEL
);
854 if (unlikely(vmw_fp
== NULL
))
857 INIT_LIST_HEAD(&vmw_fp
->fence_events
);
858 vmw_fp
->tfile
= ttm_object_file_init(dev_priv
->tdev
, 10);
859 if (unlikely(vmw_fp
->tfile
== NULL
))
862 file_priv
->driver_priv
= vmw_fp
;
863 dev_priv
->bdev
.dev_mapping
= dev
->dev_mapping
;
872 static long vmw_unlocked_ioctl(struct file
*filp
, unsigned int cmd
,
875 struct drm_file
*file_priv
= filp
->private_data
;
876 struct drm_device
*dev
= file_priv
->minor
->dev
;
877 unsigned int nr
= DRM_IOCTL_NR(cmd
);
880 * Do extra checking on driver private ioctls.
883 if ((nr
>= DRM_COMMAND_BASE
) && (nr
< DRM_COMMAND_END
)
884 && (nr
< DRM_COMMAND_BASE
+ dev
->driver
->num_ioctls
)) {
885 const struct drm_ioctl_desc
*ioctl
=
886 &vmw_ioctls
[nr
- DRM_COMMAND_BASE
];
888 if (unlikely(ioctl
->cmd_drv
!= cmd
)) {
889 DRM_ERROR("Invalid command format, ioctl %d\n",
890 nr
- DRM_COMMAND_BASE
);
895 return drm_ioctl(filp
, cmd
, arg
);
898 static void vmw_lastclose(struct drm_device
*dev
)
900 struct drm_crtc
*crtc
;
901 struct drm_mode_set set
;
908 set
.connectors
= NULL
;
909 set
.num_connectors
= 0;
911 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
913 ret
= drm_mode_set_config_internal(&set
);
919 static void vmw_master_init(struct vmw_master
*vmaster
)
921 ttm_lock_init(&vmaster
->lock
);
922 INIT_LIST_HEAD(&vmaster
->fb_surf
);
923 mutex_init(&vmaster
->fb_surf_mutex
);
926 static int vmw_master_create(struct drm_device
*dev
,
927 struct drm_master
*master
)
929 struct vmw_master
*vmaster
;
931 vmaster
= kzalloc(sizeof(*vmaster
), GFP_KERNEL
);
932 if (unlikely(vmaster
== NULL
))
935 vmw_master_init(vmaster
);
936 ttm_lock_set_kill(&vmaster
->lock
, true, SIGTERM
);
937 master
->driver_priv
= vmaster
;
942 static void vmw_master_destroy(struct drm_device
*dev
,
943 struct drm_master
*master
)
945 struct vmw_master
*vmaster
= vmw_master(master
);
947 master
->driver_priv
= NULL
;
952 static int vmw_master_set(struct drm_device
*dev
,
953 struct drm_file
*file_priv
,
956 struct vmw_private
*dev_priv
= vmw_priv(dev
);
957 struct vmw_fpriv
*vmw_fp
= vmw_fpriv(file_priv
);
958 struct vmw_master
*active
= dev_priv
->active_master
;
959 struct vmw_master
*vmaster
= vmw_master(file_priv
->master
);
962 if (!dev_priv
->enable_fb
) {
963 ret
= vmw_3d_resource_inc(dev_priv
, true);
964 if (unlikely(ret
!= 0))
966 vmw_kms_save_vga(dev_priv
);
967 mutex_lock(&dev_priv
->hw_mutex
);
968 vmw_write(dev_priv
, SVGA_REG_TRACES
, 0);
969 mutex_unlock(&dev_priv
->hw_mutex
);
973 BUG_ON(active
!= &dev_priv
->fbdev_master
);
974 ret
= ttm_vt_lock(&active
->lock
, false, vmw_fp
->tfile
);
975 if (unlikely(ret
!= 0))
976 goto out_no_active_lock
;
978 ttm_lock_set_kill(&active
->lock
, true, SIGTERM
);
979 ret
= ttm_bo_evict_mm(&dev_priv
->bdev
, TTM_PL_VRAM
);
980 if (unlikely(ret
!= 0)) {
981 DRM_ERROR("Unable to clean VRAM on "
985 dev_priv
->active_master
= NULL
;
988 ttm_lock_set_kill(&vmaster
->lock
, false, SIGTERM
);
990 ttm_vt_unlock(&vmaster
->lock
);
991 BUG_ON(vmw_fp
->locked_master
!= file_priv
->master
);
992 drm_master_put(&vmw_fp
->locked_master
);
995 dev_priv
->active_master
= vmaster
;
1000 if (!dev_priv
->enable_fb
) {
1001 vmw_kms_restore_vga(dev_priv
);
1002 vmw_3d_resource_dec(dev_priv
, true);
1003 mutex_lock(&dev_priv
->hw_mutex
);
1004 vmw_write(dev_priv
, SVGA_REG_TRACES
, 1);
1005 mutex_unlock(&dev_priv
->hw_mutex
);
1010 static void vmw_master_drop(struct drm_device
*dev
,
1011 struct drm_file
*file_priv
,
1014 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1015 struct vmw_fpriv
*vmw_fp
= vmw_fpriv(file_priv
);
1016 struct vmw_master
*vmaster
= vmw_master(file_priv
->master
);
1020 * Make sure the master doesn't disappear while we have
1024 vmw_fp
->locked_master
= drm_master_get(file_priv
->master
);
1025 ret
= ttm_vt_lock(&vmaster
->lock
, false, vmw_fp
->tfile
);
1026 if (unlikely((ret
!= 0))) {
1027 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1028 drm_master_put(&vmw_fp
->locked_master
);
1031 ttm_lock_set_kill(&vmaster
->lock
, false, SIGTERM
);
1032 vmw_execbuf_release_pinned_bo(dev_priv
);
1034 if (!dev_priv
->enable_fb
) {
1035 ret
= ttm_bo_evict_mm(&dev_priv
->bdev
, TTM_PL_VRAM
);
1036 if (unlikely(ret
!= 0))
1037 DRM_ERROR("Unable to clean VRAM on master drop.\n");
1038 vmw_kms_restore_vga(dev_priv
);
1039 vmw_3d_resource_dec(dev_priv
, true);
1040 mutex_lock(&dev_priv
->hw_mutex
);
1041 vmw_write(dev_priv
, SVGA_REG_TRACES
, 1);
1042 mutex_unlock(&dev_priv
->hw_mutex
);
1045 dev_priv
->active_master
= &dev_priv
->fbdev_master
;
1046 ttm_lock_set_kill(&dev_priv
->fbdev_master
.lock
, false, SIGTERM
);
1047 ttm_vt_unlock(&dev_priv
->fbdev_master
.lock
);
1049 if (dev_priv
->enable_fb
)
1050 vmw_fb_on(dev_priv
);
1054 static void vmw_remove(struct pci_dev
*pdev
)
1056 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1061 static int vmwgfx_pm_notifier(struct notifier_block
*nb
, unsigned long val
,
1064 struct vmw_private
*dev_priv
=
1065 container_of(nb
, struct vmw_private
, pm_nb
);
1066 struct vmw_master
*vmaster
= dev_priv
->active_master
;
1069 case PM_HIBERNATION_PREPARE
:
1070 case PM_SUSPEND_PREPARE
:
1071 ttm_suspend_lock(&vmaster
->lock
);
1074 * This empties VRAM and unbinds all GMR bindings.
1075 * Buffer contents is moved to swappable memory.
1077 vmw_execbuf_release_pinned_bo(dev_priv
);
1078 vmw_resource_evict_all(dev_priv
);
1079 ttm_bo_swapout_all(&dev_priv
->bdev
);
1082 case PM_POST_HIBERNATION
:
1083 case PM_POST_SUSPEND
:
1084 case PM_POST_RESTORE
:
1085 ttm_suspend_unlock(&vmaster
->lock
);
1088 case PM_RESTORE_PREPARE
:
1097 * These might not be needed with the virtual SVGA device.
1100 static int vmw_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1102 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1103 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1105 if (dev_priv
->num_3d_resources
!= 0) {
1106 DRM_INFO("Can't suspend or hibernate "
1107 "while 3D resources are active.\n");
1111 pci_save_state(pdev
);
1112 pci_disable_device(pdev
);
1113 pci_set_power_state(pdev
, PCI_D3hot
);
1117 static int vmw_pci_resume(struct pci_dev
*pdev
)
1119 pci_set_power_state(pdev
, PCI_D0
);
1120 pci_restore_state(pdev
);
1121 return pci_enable_device(pdev
);
1124 static int vmw_pm_suspend(struct device
*kdev
)
1126 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1127 struct pm_message dummy
;
1131 return vmw_pci_suspend(pdev
, dummy
);
1134 static int vmw_pm_resume(struct device
*kdev
)
1136 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1138 return vmw_pci_resume(pdev
);
1141 static int vmw_pm_prepare(struct device
*kdev
)
1143 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1144 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1145 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1148 * Release 3d reference held by fbdev and potentially
1151 dev_priv
->suspended
= true;
1152 if (dev_priv
->enable_fb
)
1153 vmw_3d_resource_dec(dev_priv
, true);
1155 if (dev_priv
->num_3d_resources
!= 0) {
1157 DRM_INFO("Can't suspend or hibernate "
1158 "while 3D resources are active.\n");
1160 if (dev_priv
->enable_fb
)
1161 vmw_3d_resource_inc(dev_priv
, true);
1162 dev_priv
->suspended
= false;
1169 static void vmw_pm_complete(struct device
*kdev
)
1171 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1172 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1173 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1175 mutex_lock(&dev_priv
->hw_mutex
);
1176 vmw_write(dev_priv
, SVGA_REG_ID
, SVGA_ID_2
);
1177 (void) vmw_read(dev_priv
, SVGA_REG_ID
);
1178 mutex_unlock(&dev_priv
->hw_mutex
);
1181 * Reclaim 3d reference held by fbdev and potentially
1184 if (dev_priv
->enable_fb
)
1185 vmw_3d_resource_inc(dev_priv
, false);
1187 dev_priv
->suspended
= false;
1190 static const struct dev_pm_ops vmw_pm_ops
= {
1191 .prepare
= vmw_pm_prepare
,
1192 .complete
= vmw_pm_complete
,
1193 .suspend
= vmw_pm_suspend
,
1194 .resume
= vmw_pm_resume
,
1197 static const struct file_operations vmwgfx_driver_fops
= {
1198 .owner
= THIS_MODULE
,
1200 .release
= drm_release
,
1201 .unlocked_ioctl
= vmw_unlocked_ioctl
,
1203 .poll
= vmw_fops_poll
,
1204 .read
= vmw_fops_read
,
1205 #if defined(CONFIG_COMPAT)
1206 .compat_ioctl
= drm_compat_ioctl
,
1208 .llseek
= noop_llseek
,
1211 static struct drm_driver driver
= {
1212 .driver_features
= DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
|
1213 DRIVER_MODESET
| DRIVER_PRIME
,
1214 .load
= vmw_driver_load
,
1215 .unload
= vmw_driver_unload
,
1216 .lastclose
= vmw_lastclose
,
1217 .irq_preinstall
= vmw_irq_preinstall
,
1218 .irq_postinstall
= vmw_irq_postinstall
,
1219 .irq_uninstall
= vmw_irq_uninstall
,
1220 .irq_handler
= vmw_irq_handler
,
1221 .get_vblank_counter
= vmw_get_vblank_counter
,
1222 .enable_vblank
= vmw_enable_vblank
,
1223 .disable_vblank
= vmw_disable_vblank
,
1224 .ioctls
= vmw_ioctls
,
1225 .num_ioctls
= DRM_ARRAY_SIZE(vmw_ioctls
),
1226 .master_create
= vmw_master_create
,
1227 .master_destroy
= vmw_master_destroy
,
1228 .master_set
= vmw_master_set
,
1229 .master_drop
= vmw_master_drop
,
1230 .open
= vmw_driver_open
,
1231 .preclose
= vmw_preclose
,
1232 .postclose
= vmw_postclose
,
1234 .dumb_create
= vmw_dumb_create
,
1235 .dumb_map_offset
= vmw_dumb_map_offset
,
1236 .dumb_destroy
= vmw_dumb_destroy
,
1238 .prime_fd_to_handle
= vmw_prime_fd_to_handle
,
1239 .prime_handle_to_fd
= vmw_prime_handle_to_fd
,
1241 .fops
= &vmwgfx_driver_fops
,
1242 .name
= VMWGFX_DRIVER_NAME
,
1243 .desc
= VMWGFX_DRIVER_DESC
,
1244 .date
= VMWGFX_DRIVER_DATE
,
1245 .major
= VMWGFX_DRIVER_MAJOR
,
1246 .minor
= VMWGFX_DRIVER_MINOR
,
1247 .patchlevel
= VMWGFX_DRIVER_PATCHLEVEL
1250 static struct pci_driver vmw_pci_driver
= {
1251 .name
= VMWGFX_DRIVER_NAME
,
1252 .id_table
= vmw_pci_id_list
,
1254 .remove
= vmw_remove
,
1260 static int vmw_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1262 return drm_get_pci_dev(pdev
, ent
, &driver
);
1265 static int __init
vmwgfx_init(void)
1268 ret
= drm_pci_init(&driver
, &vmw_pci_driver
);
1270 DRM_ERROR("Failed initializing DRM.\n");
1274 static void __exit
vmwgfx_exit(void)
1276 drm_pci_exit(&driver
, &vmw_pci_driver
);
1279 module_init(vmwgfx_init
);
1280 module_exit(vmwgfx_exit
);
1282 MODULE_AUTHOR("VMware Inc. and others");
1283 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1284 MODULE_LICENSE("GPL and additional rights");
1285 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR
) "."
1286 __stringify(VMWGFX_DRIVER_MINOR
) "."
1287 __stringify(VMWGFX_DRIVER_PATCHLEVEL
) "."