1 /**************************************************************************
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
27 #include <linux/module.h>
30 #include "vmwgfx_drv.h"
31 #include <drm/ttm/ttm_placement.h>
32 #include <drm/ttm/ttm_bo_driver.h>
33 #include <drm/ttm/ttm_object.h>
34 #include <drm/ttm/ttm_module.h>
35 #include <linux/dma_remapping.h>
37 #define VMWGFX_DRIVER_NAME "vmwgfx"
38 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
39 #define VMWGFX_CHIP_SVGAII 0
40 #define VMW_FB_RESERVATION 0
42 #define VMW_MIN_INITIAL_WIDTH 800
43 #define VMW_MIN_INITIAL_HEIGHT 600
47 * Fully encoded drm commands. Might move to vmw_drm.h
50 #define DRM_IOCTL_VMW_GET_PARAM \
51 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
52 struct drm_vmw_getparam_arg)
53 #define DRM_IOCTL_VMW_ALLOC_DMABUF \
54 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
55 union drm_vmw_alloc_dmabuf_arg)
56 #define DRM_IOCTL_VMW_UNREF_DMABUF \
57 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
58 struct drm_vmw_unref_dmabuf_arg)
59 #define DRM_IOCTL_VMW_CURSOR_BYPASS \
60 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
61 struct drm_vmw_cursor_bypass_arg)
63 #define DRM_IOCTL_VMW_CONTROL_STREAM \
64 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
65 struct drm_vmw_control_stream_arg)
66 #define DRM_IOCTL_VMW_CLAIM_STREAM \
67 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
68 struct drm_vmw_stream_arg)
69 #define DRM_IOCTL_VMW_UNREF_STREAM \
70 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
71 struct drm_vmw_stream_arg)
73 #define DRM_IOCTL_VMW_CREATE_CONTEXT \
74 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
75 struct drm_vmw_context_arg)
76 #define DRM_IOCTL_VMW_UNREF_CONTEXT \
77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
78 struct drm_vmw_context_arg)
79 #define DRM_IOCTL_VMW_CREATE_SURFACE \
80 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
81 union drm_vmw_surface_create_arg)
82 #define DRM_IOCTL_VMW_UNREF_SURFACE \
83 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
84 struct drm_vmw_surface_arg)
85 #define DRM_IOCTL_VMW_REF_SURFACE \
86 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
87 union drm_vmw_surface_reference_arg)
88 #define DRM_IOCTL_VMW_EXECBUF \
89 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
90 struct drm_vmw_execbuf_arg)
91 #define DRM_IOCTL_VMW_GET_3D_CAP \
92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
93 struct drm_vmw_get_3d_cap_arg)
94 #define DRM_IOCTL_VMW_FENCE_WAIT \
95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
96 struct drm_vmw_fence_wait_arg)
97 #define DRM_IOCTL_VMW_FENCE_SIGNALED \
98 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
99 struct drm_vmw_fence_signaled_arg)
100 #define DRM_IOCTL_VMW_FENCE_UNREF \
101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
102 struct drm_vmw_fence_arg)
103 #define DRM_IOCTL_VMW_FENCE_EVENT \
104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
105 struct drm_vmw_fence_event_arg)
106 #define DRM_IOCTL_VMW_PRESENT \
107 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
108 struct drm_vmw_present_arg)
109 #define DRM_IOCTL_VMW_PRESENT_READBACK \
110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
111 struct drm_vmw_present_readback_arg)
112 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \
113 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
114 struct drm_vmw_update_layout_arg)
115 #define DRM_IOCTL_VMW_CREATE_SHADER \
116 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
117 struct drm_vmw_shader_create_arg)
118 #define DRM_IOCTL_VMW_UNREF_SHADER \
119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
120 struct drm_vmw_shader_arg)
121 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
122 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
123 union drm_vmw_gb_surface_create_arg)
124 #define DRM_IOCTL_VMW_GB_SURFACE_REF \
125 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
126 union drm_vmw_gb_surface_reference_arg)
129 * The core DRM version of this macro doesn't account for
133 #define VMW_IOCTL_DEF(ioctl, func, flags) \
134 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
140 static const struct drm_ioctl_desc vmw_ioctls
[] = {
141 VMW_IOCTL_DEF(VMW_GET_PARAM
, vmw_getparam_ioctl
,
142 DRM_AUTH
| DRM_UNLOCKED
),
143 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF
, vmw_dmabuf_alloc_ioctl
,
144 DRM_AUTH
| DRM_UNLOCKED
),
145 VMW_IOCTL_DEF(VMW_UNREF_DMABUF
, vmw_dmabuf_unref_ioctl
,
146 DRM_AUTH
| DRM_UNLOCKED
),
147 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS
,
148 vmw_kms_cursor_bypass_ioctl
,
149 DRM_MASTER
| DRM_CONTROL_ALLOW
| DRM_UNLOCKED
),
151 VMW_IOCTL_DEF(VMW_CONTROL_STREAM
, vmw_overlay_ioctl
,
152 DRM_MASTER
| DRM_CONTROL_ALLOW
| DRM_UNLOCKED
),
153 VMW_IOCTL_DEF(VMW_CLAIM_STREAM
, vmw_stream_claim_ioctl
,
154 DRM_MASTER
| DRM_CONTROL_ALLOW
| DRM_UNLOCKED
),
155 VMW_IOCTL_DEF(VMW_UNREF_STREAM
, vmw_stream_unref_ioctl
,
156 DRM_MASTER
| DRM_CONTROL_ALLOW
| DRM_UNLOCKED
),
158 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT
, vmw_context_define_ioctl
,
159 DRM_AUTH
| DRM_UNLOCKED
),
160 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT
, vmw_context_destroy_ioctl
,
161 DRM_AUTH
| DRM_UNLOCKED
),
162 VMW_IOCTL_DEF(VMW_CREATE_SURFACE
, vmw_surface_define_ioctl
,
163 DRM_AUTH
| DRM_UNLOCKED
),
164 VMW_IOCTL_DEF(VMW_UNREF_SURFACE
, vmw_surface_destroy_ioctl
,
165 DRM_AUTH
| DRM_UNLOCKED
),
166 VMW_IOCTL_DEF(VMW_REF_SURFACE
, vmw_surface_reference_ioctl
,
167 DRM_AUTH
| DRM_UNLOCKED
),
168 VMW_IOCTL_DEF(VMW_EXECBUF
, vmw_execbuf_ioctl
,
169 DRM_AUTH
| DRM_UNLOCKED
),
170 VMW_IOCTL_DEF(VMW_FENCE_WAIT
, vmw_fence_obj_wait_ioctl
,
171 DRM_AUTH
| DRM_UNLOCKED
),
172 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED
,
173 vmw_fence_obj_signaled_ioctl
,
174 DRM_AUTH
| DRM_UNLOCKED
),
175 VMW_IOCTL_DEF(VMW_FENCE_UNREF
, vmw_fence_obj_unref_ioctl
,
176 DRM_AUTH
| DRM_UNLOCKED
),
177 VMW_IOCTL_DEF(VMW_FENCE_EVENT
,
178 vmw_fence_event_ioctl
,
179 DRM_AUTH
| DRM_UNLOCKED
),
180 VMW_IOCTL_DEF(VMW_GET_3D_CAP
, vmw_get_cap_3d_ioctl
,
181 DRM_AUTH
| DRM_UNLOCKED
),
183 /* these allow direct access to the framebuffers mark as master only */
184 VMW_IOCTL_DEF(VMW_PRESENT
, vmw_present_ioctl
,
185 DRM_MASTER
| DRM_AUTH
| DRM_UNLOCKED
),
186 VMW_IOCTL_DEF(VMW_PRESENT_READBACK
,
187 vmw_present_readback_ioctl
,
188 DRM_MASTER
| DRM_AUTH
| DRM_UNLOCKED
),
189 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT
,
190 vmw_kms_update_layout_ioctl
,
191 DRM_MASTER
| DRM_UNLOCKED
),
192 VMW_IOCTL_DEF(VMW_CREATE_SHADER
,
193 vmw_shader_define_ioctl
,
194 DRM_AUTH
| DRM_UNLOCKED
),
195 VMW_IOCTL_DEF(VMW_UNREF_SHADER
,
196 vmw_shader_destroy_ioctl
,
197 DRM_AUTH
| DRM_UNLOCKED
),
198 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE
,
199 vmw_gb_surface_define_ioctl
,
200 DRM_AUTH
| DRM_UNLOCKED
),
201 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF
,
202 vmw_gb_surface_reference_ioctl
,
203 DRM_AUTH
| DRM_UNLOCKED
),
206 static struct pci_device_id vmw_pci_id_list
[] = {
207 {0x15ad, 0x0405, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, VMWGFX_CHIP_SVGAII
},
210 MODULE_DEVICE_TABLE(pci
, vmw_pci_id_list
);
212 static int enable_fbdev
= IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON
);
213 static int vmw_force_iommu
;
214 static int vmw_restrict_iommu
;
215 static int vmw_force_coherent
;
216 static int vmw_restrict_dma_mask
;
218 static int vmw_probe(struct pci_dev
*, const struct pci_device_id
*);
219 static void vmw_master_init(struct vmw_master
*);
220 static int vmwgfx_pm_notifier(struct notifier_block
*nb
, unsigned long val
,
223 MODULE_PARM_DESC(enable_fbdev
, "Enable vmwgfx fbdev");
224 module_param_named(enable_fbdev
, enable_fbdev
, int, 0600);
225 MODULE_PARM_DESC(force_dma_api
, "Force using the DMA API for TTM pages");
226 module_param_named(force_dma_api
, vmw_force_iommu
, int, 0600);
227 MODULE_PARM_DESC(restrict_iommu
, "Try to limit IOMMU usage for TTM pages");
228 module_param_named(restrict_iommu
, vmw_restrict_iommu
, int, 0600);
229 MODULE_PARM_DESC(force_coherent
, "Force coherent TTM pages");
230 module_param_named(force_coherent
, vmw_force_coherent
, int, 0600);
231 MODULE_PARM_DESC(restrict_dma_mask
, "Restrict DMA mask to 44 bits with IOMMU");
232 module_param_named(restrict_dma_mask
, vmw_restrict_dma_mask
, int, 0600);
235 static void vmw_print_capabilities(uint32_t capabilities
)
237 DRM_INFO("Capabilities:\n");
238 if (capabilities
& SVGA_CAP_RECT_COPY
)
239 DRM_INFO(" Rect copy.\n");
240 if (capabilities
& SVGA_CAP_CURSOR
)
241 DRM_INFO(" Cursor.\n");
242 if (capabilities
& SVGA_CAP_CURSOR_BYPASS
)
243 DRM_INFO(" Cursor bypass.\n");
244 if (capabilities
& SVGA_CAP_CURSOR_BYPASS_2
)
245 DRM_INFO(" Cursor bypass 2.\n");
246 if (capabilities
& SVGA_CAP_8BIT_EMULATION
)
247 DRM_INFO(" 8bit emulation.\n");
248 if (capabilities
& SVGA_CAP_ALPHA_CURSOR
)
249 DRM_INFO(" Alpha cursor.\n");
250 if (capabilities
& SVGA_CAP_3D
)
252 if (capabilities
& SVGA_CAP_EXTENDED_FIFO
)
253 DRM_INFO(" Extended Fifo.\n");
254 if (capabilities
& SVGA_CAP_MULTIMON
)
255 DRM_INFO(" Multimon.\n");
256 if (capabilities
& SVGA_CAP_PITCHLOCK
)
257 DRM_INFO(" Pitchlock.\n");
258 if (capabilities
& SVGA_CAP_IRQMASK
)
259 DRM_INFO(" Irq mask.\n");
260 if (capabilities
& SVGA_CAP_DISPLAY_TOPOLOGY
)
261 DRM_INFO(" Display Topology.\n");
262 if (capabilities
& SVGA_CAP_GMR
)
264 if (capabilities
& SVGA_CAP_TRACES
)
265 DRM_INFO(" Traces.\n");
266 if (capabilities
& SVGA_CAP_GMR2
)
267 DRM_INFO(" GMR2.\n");
268 if (capabilities
& SVGA_CAP_SCREEN_OBJECT_2
)
269 DRM_INFO(" Screen Object 2.\n");
270 if (capabilities
& SVGA_CAP_COMMAND_BUFFERS
)
271 DRM_INFO(" Command Buffers.\n");
272 if (capabilities
& SVGA_CAP_CMD_BUFFERS_2
)
273 DRM_INFO(" Command Buffers 2.\n");
274 if (capabilities
& SVGA_CAP_GBOBJECTS
)
275 DRM_INFO(" Guest Backed Resources.\n");
280 * vmw_execbuf_prepare_dummy_query - Initialize a query result structure at
281 * the start of a buffer object.
283 * @dev_priv: The device private structure.
285 * This function will idle the buffer using an uninterruptible wait, then
286 * map the first page and initialize a pending occlusion query result structure,
287 * Finally it will unmap the buffer.
289 * TODO: Since we're only mapping a single page, we should optimize the map
290 * to use kmap_atomic / iomap_atomic.
292 static void vmw_dummy_query_bo_prepare(struct vmw_private
*dev_priv
)
294 struct ttm_bo_kmap_obj map
;
295 volatile SVGA3dQueryResult
*result
;
298 struct ttm_bo_device
*bdev
= &dev_priv
->bdev
;
299 struct ttm_buffer_object
*bo
= dev_priv
->dummy_query_bo
;
301 ttm_bo_reserve(bo
, false, false, false, 0);
302 spin_lock(&bdev
->fence_lock
);
303 ret
= ttm_bo_wait(bo
, false, false, false);
304 spin_unlock(&bdev
->fence_lock
);
305 if (unlikely(ret
!= 0))
306 (void) vmw_fallback_wait(dev_priv
, false, true, 0, false,
309 ret
= ttm_bo_kmap(bo
, 0, 1, &map
);
310 if (likely(ret
== 0)) {
311 result
= ttm_kmap_obj_virtual(&map
, &dummy
);
312 result
->totalSize
= sizeof(*result
);
313 result
->state
= SVGA3D_QUERYSTATE_PENDING
;
314 result
->result32
= 0xff;
317 DRM_ERROR("Dummy query buffer map failed.\n");
318 ttm_bo_unreserve(bo
);
323 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
325 * @dev_priv: A device private structure.
327 * This function creates a small buffer object that holds the query
328 * result for dummy queries emitted as query barriers.
329 * No interruptible waits are done within this function.
331 * Returns an error if bo creation fails.
333 static int vmw_dummy_query_bo_create(struct vmw_private
*dev_priv
)
335 return ttm_bo_create(&dev_priv
->bdev
,
338 &vmw_vram_sys_placement
,
340 &dev_priv
->dummy_query_bo
);
344 static int vmw_request_device(struct vmw_private
*dev_priv
)
348 ret
= vmw_fifo_init(dev_priv
, &dev_priv
->fifo
);
349 if (unlikely(ret
!= 0)) {
350 DRM_ERROR("Unable to initialize FIFO.\n");
353 vmw_fence_fifo_up(dev_priv
->fman
);
354 if (dev_priv
->has_mob
) {
355 ret
= vmw_otables_setup(dev_priv
);
356 if (unlikely(ret
!= 0)) {
357 DRM_ERROR("Unable to initialize "
358 "guest Memory OBjects.\n");
362 ret
= vmw_dummy_query_bo_create(dev_priv
);
363 if (unlikely(ret
!= 0))
364 goto out_no_query_bo
;
365 vmw_dummy_query_bo_prepare(dev_priv
);
370 if (dev_priv
->has_mob
)
371 vmw_otables_takedown(dev_priv
);
373 vmw_fence_fifo_down(dev_priv
->fman
);
374 vmw_fifo_release(dev_priv
, &dev_priv
->fifo
);
378 static void vmw_release_device(struct vmw_private
*dev_priv
)
381 * Previous destructions should've released
385 BUG_ON(dev_priv
->pinned_bo
!= NULL
);
387 ttm_bo_unref(&dev_priv
->dummy_query_bo
);
388 if (dev_priv
->has_mob
)
389 vmw_otables_takedown(dev_priv
);
390 vmw_fence_fifo_down(dev_priv
->fman
);
391 vmw_fifo_release(dev_priv
, &dev_priv
->fifo
);
396 * Increase the 3d resource refcount.
397 * If the count was prevously zero, initialize the fifo, switching to svga
398 * mode. Note that the master holds a ref as well, and may request an
399 * explicit switch to svga mode if fb is not running, using @unhide_svga.
401 int vmw_3d_resource_inc(struct vmw_private
*dev_priv
,
406 mutex_lock(&dev_priv
->release_mutex
);
407 if (unlikely(dev_priv
->num_3d_resources
++ == 0)) {
408 ret
= vmw_request_device(dev_priv
);
409 if (unlikely(ret
!= 0))
410 --dev_priv
->num_3d_resources
;
411 } else if (unhide_svga
) {
412 mutex_lock(&dev_priv
->hw_mutex
);
413 vmw_write(dev_priv
, SVGA_REG_ENABLE
,
414 vmw_read(dev_priv
, SVGA_REG_ENABLE
) &
415 ~SVGA_REG_ENABLE_HIDE
);
416 mutex_unlock(&dev_priv
->hw_mutex
);
419 mutex_unlock(&dev_priv
->release_mutex
);
424 * Decrease the 3d resource refcount.
425 * If the count reaches zero, disable the fifo, switching to vga mode.
426 * Note that the master holds a refcount as well, and may request an
427 * explicit switch to vga mode when it releases its refcount to account
428 * for the situation of an X server vt switch to VGA with 3d resources
431 void vmw_3d_resource_dec(struct vmw_private
*dev_priv
,
436 mutex_lock(&dev_priv
->release_mutex
);
437 if (unlikely(--dev_priv
->num_3d_resources
== 0))
438 vmw_release_device(dev_priv
);
439 else if (hide_svga
) {
440 mutex_lock(&dev_priv
->hw_mutex
);
441 vmw_write(dev_priv
, SVGA_REG_ENABLE
,
442 vmw_read(dev_priv
, SVGA_REG_ENABLE
) |
443 SVGA_REG_ENABLE_HIDE
);
444 mutex_unlock(&dev_priv
->hw_mutex
);
447 n3d
= (int32_t) dev_priv
->num_3d_resources
;
448 mutex_unlock(&dev_priv
->release_mutex
);
454 * Sets the initial_[width|height] fields on the given vmw_private.
456 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
457 * clamping the value to fb_max_[width|height] fields and the
458 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
459 * If the values appear to be invalid, set them to
460 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
462 static void vmw_get_initial_size(struct vmw_private
*dev_priv
)
467 width
= vmw_read(dev_priv
, SVGA_REG_WIDTH
);
468 height
= vmw_read(dev_priv
, SVGA_REG_HEIGHT
);
470 width
= max_t(uint32_t, width
, VMW_MIN_INITIAL_WIDTH
);
471 height
= max_t(uint32_t, height
, VMW_MIN_INITIAL_HEIGHT
);
473 if (width
> dev_priv
->fb_max_width
||
474 height
> dev_priv
->fb_max_height
) {
477 * This is a host error and shouldn't occur.
480 width
= VMW_MIN_INITIAL_WIDTH
;
481 height
= VMW_MIN_INITIAL_HEIGHT
;
484 dev_priv
->initial_width
= width
;
485 dev_priv
->initial_height
= height
;
489 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
492 * @dev_priv: Pointer to a struct vmw_private
494 * This functions tries to determine the IOMMU setup and what actions
495 * need to be taken by the driver to make system pages visible to the
497 * If this function decides that DMA is not possible, it returns -EINVAL.
498 * The driver may then try to disable features of the device that require
501 static int vmw_dma_select_mode(struct vmw_private
*dev_priv
)
503 static const char *names
[vmw_dma_map_max
] = {
504 [vmw_dma_phys
] = "Using physical TTM page addresses.",
505 [vmw_dma_alloc_coherent
] = "Using coherent TTM pages.",
506 [vmw_dma_map_populate
] = "Keeping DMA mappings.",
507 [vmw_dma_map_bind
] = "Giving up DMA mappings early."};
509 const struct dma_map_ops
*dma_ops
= get_dma_ops(dev_priv
->dev
->dev
);
511 #ifdef CONFIG_INTEL_IOMMU
512 if (intel_iommu_enabled
) {
513 dev_priv
->map_mode
= vmw_dma_map_populate
;
518 if (!(vmw_force_iommu
|| vmw_force_coherent
)) {
519 dev_priv
->map_mode
= vmw_dma_phys
;
520 DRM_INFO("DMA map mode: %s\n", names
[dev_priv
->map_mode
]);
524 dev_priv
->map_mode
= vmw_dma_map_populate
;
526 if (dma_ops
->sync_single_for_cpu
)
527 dev_priv
->map_mode
= vmw_dma_alloc_coherent
;
528 #ifdef CONFIG_SWIOTLB
529 if (swiotlb_nr_tbl() == 0)
530 dev_priv
->map_mode
= vmw_dma_map_populate
;
533 #ifdef CONFIG_INTEL_IOMMU
536 if (dev_priv
->map_mode
== vmw_dma_map_populate
&&
538 dev_priv
->map_mode
= vmw_dma_map_bind
;
540 if (vmw_force_coherent
)
541 dev_priv
->map_mode
= vmw_dma_alloc_coherent
;
543 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
545 * No coherent page pool
547 if (dev_priv
->map_mode
== vmw_dma_alloc_coherent
)
551 #else /* CONFIG_X86 */
552 dev_priv
->map_mode
= vmw_dma_map_populate
;
553 #endif /* CONFIG_X86 */
555 DRM_INFO("DMA map mode: %s\n", names
[dev_priv
->map_mode
]);
561 * vmw_dma_masks - set required page- and dma masks
563 * @dev: Pointer to struct drm-device
565 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
566 * restriction also for 64-bit systems.
568 #ifdef CONFIG_INTEL_IOMMU
569 static int vmw_dma_masks(struct vmw_private
*dev_priv
)
571 struct drm_device
*dev
= dev_priv
->dev
;
573 if (intel_iommu_enabled
&&
574 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask
)) {
575 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
576 return dma_set_mask(dev
->dev
, DMA_BIT_MASK(44));
581 static int vmw_dma_masks(struct vmw_private
*dev_priv
)
587 static int vmw_driver_load(struct drm_device
*dev
, unsigned long chipset
)
589 struct vmw_private
*dev_priv
;
593 bool refuse_dma
= false;
595 dev_priv
= kzalloc(sizeof(*dev_priv
), GFP_KERNEL
);
596 if (unlikely(dev_priv
== NULL
)) {
597 DRM_ERROR("Failed allocating a device private struct.\n");
601 pci_set_master(dev
->pdev
);
604 dev_priv
->vmw_chipset
= chipset
;
605 dev_priv
->last_read_seqno
= (uint32_t) -100;
606 mutex_init(&dev_priv
->hw_mutex
);
607 mutex_init(&dev_priv
->cmdbuf_mutex
);
608 mutex_init(&dev_priv
->release_mutex
);
609 rwlock_init(&dev_priv
->resource_lock
);
611 for (i
= vmw_res_context
; i
< vmw_res_max
; ++i
) {
612 idr_init(&dev_priv
->res_idr
[i
]);
613 INIT_LIST_HEAD(&dev_priv
->res_lru
[i
]);
616 mutex_init(&dev_priv
->init_mutex
);
617 init_waitqueue_head(&dev_priv
->fence_queue
);
618 init_waitqueue_head(&dev_priv
->fifo_queue
);
619 dev_priv
->fence_queue_waiters
= 0;
620 atomic_set(&dev_priv
->fifo_queue_waiters
, 0);
622 dev_priv
->used_memory_size
= 0;
624 dev_priv
->io_start
= pci_resource_start(dev
->pdev
, 0);
625 dev_priv
->vram_start
= pci_resource_start(dev
->pdev
, 1);
626 dev_priv
->mmio_start
= pci_resource_start(dev
->pdev
, 2);
628 dev_priv
->enable_fb
= enable_fbdev
;
630 mutex_lock(&dev_priv
->hw_mutex
);
632 vmw_write(dev_priv
, SVGA_REG_ID
, SVGA_ID_2
);
633 svga_id
= vmw_read(dev_priv
, SVGA_REG_ID
);
634 if (svga_id
!= SVGA_ID_2
) {
636 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id
);
637 mutex_unlock(&dev_priv
->hw_mutex
);
641 dev_priv
->capabilities
= vmw_read(dev_priv
, SVGA_REG_CAPABILITIES
);
642 ret
= vmw_dma_select_mode(dev_priv
);
643 if (unlikely(ret
!= 0)) {
644 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
648 dev_priv
->vram_size
= vmw_read(dev_priv
, SVGA_REG_VRAM_SIZE
);
649 dev_priv
->mmio_size
= vmw_read(dev_priv
, SVGA_REG_MEM_SIZE
);
650 dev_priv
->fb_max_width
= vmw_read(dev_priv
, SVGA_REG_MAX_WIDTH
);
651 dev_priv
->fb_max_height
= vmw_read(dev_priv
, SVGA_REG_MAX_HEIGHT
);
653 vmw_get_initial_size(dev_priv
);
655 if (dev_priv
->capabilities
& SVGA_CAP_GMR2
) {
656 dev_priv
->max_gmr_ids
=
657 vmw_read(dev_priv
, SVGA_REG_GMR_MAX_IDS
);
658 dev_priv
->max_gmr_pages
=
659 vmw_read(dev_priv
, SVGA_REG_GMRS_MAX_PAGES
);
660 dev_priv
->memory_size
=
661 vmw_read(dev_priv
, SVGA_REG_MEMORY_SIZE
);
662 dev_priv
->memory_size
-= dev_priv
->vram_size
;
665 * An arbitrary limit of 512MiB on surface
666 * memory. But all HWV8 hardware supports GMR2.
668 dev_priv
->memory_size
= 512*1024*1024;
670 dev_priv
->max_mob_pages
= 0;
671 if (dev_priv
->capabilities
& SVGA_CAP_GBOBJECTS
) {
674 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB
);
676 dev_priv
->max_mob_pages
= mem_size
* 1024 / PAGE_SIZE
;
677 dev_priv
->prim_bb_mem
=
679 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM
);
681 dev_priv
->prim_bb_mem
= dev_priv
->vram_size
;
683 ret
= vmw_dma_masks(dev_priv
);
684 if (unlikely(ret
!= 0))
687 if (unlikely(dev_priv
->prim_bb_mem
< dev_priv
->vram_size
))
688 dev_priv
->prim_bb_mem
= dev_priv
->vram_size
;
690 mutex_unlock(&dev_priv
->hw_mutex
);
692 vmw_print_capabilities(dev_priv
->capabilities
);
694 if (dev_priv
->capabilities
& SVGA_CAP_GMR2
) {
695 DRM_INFO("Max GMR ids is %u\n",
696 (unsigned)dev_priv
->max_gmr_ids
);
697 DRM_INFO("Max number of GMR pages is %u\n",
698 (unsigned)dev_priv
->max_gmr_pages
);
699 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
700 (unsigned)dev_priv
->memory_size
/ 1024);
702 DRM_INFO("Maximum display memory size is %u kiB\n",
703 dev_priv
->prim_bb_mem
/ 1024);
704 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
705 dev_priv
->vram_start
, dev_priv
->vram_size
/ 1024);
706 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
707 dev_priv
->mmio_start
, dev_priv
->mmio_size
/ 1024);
709 ret
= vmw_ttm_global_init(dev_priv
);
710 if (unlikely(ret
!= 0))
714 vmw_master_init(&dev_priv
->fbdev_master
);
715 ttm_lock_set_kill(&dev_priv
->fbdev_master
.lock
, false, SIGTERM
);
716 dev_priv
->active_master
= &dev_priv
->fbdev_master
;
719 ret
= ttm_bo_device_init(&dev_priv
->bdev
,
720 dev_priv
->bo_global_ref
.ref
.object
,
721 &vmw_bo_driver
, VMWGFX_FILE_PAGE_OFFSET
,
723 if (unlikely(ret
!= 0)) {
724 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
728 ret
= ttm_bo_init_mm(&dev_priv
->bdev
, TTM_PL_VRAM
,
729 (dev_priv
->vram_size
>> PAGE_SHIFT
));
730 if (unlikely(ret
!= 0)) {
731 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
735 dev_priv
->has_gmr
= true;
736 if (((dev_priv
->capabilities
& (SVGA_CAP_GMR
| SVGA_CAP_GMR2
)) == 0) ||
737 refuse_dma
|| ttm_bo_init_mm(&dev_priv
->bdev
, VMW_PL_GMR
,
739 DRM_INFO("No GMR memory available. "
740 "Graphics memory resources are very limited.\n");
741 dev_priv
->has_gmr
= false;
744 if (dev_priv
->capabilities
& SVGA_CAP_GBOBJECTS
) {
745 dev_priv
->has_mob
= true;
746 if (ttm_bo_init_mm(&dev_priv
->bdev
, VMW_PL_MOB
,
748 DRM_INFO("No MOB memory available. "
749 "3D will be disabled.\n");
750 dev_priv
->has_mob
= false;
754 dev_priv
->mmio_mtrr
= arch_phys_wc_add(dev_priv
->mmio_start
,
755 dev_priv
->mmio_size
);
757 dev_priv
->mmio_virt
= ioremap_wc(dev_priv
->mmio_start
,
758 dev_priv
->mmio_size
);
760 if (unlikely(dev_priv
->mmio_virt
== NULL
)) {
762 DRM_ERROR("Failed mapping MMIO.\n");
766 /* Need mmio memory to check for fifo pitchlock cap. */
767 if (!(dev_priv
->capabilities
& SVGA_CAP_DISPLAY_TOPOLOGY
) &&
768 !(dev_priv
->capabilities
& SVGA_CAP_PITCHLOCK
) &&
769 !vmw_fifo_have_pitchlock(dev_priv
)) {
771 DRM_ERROR("Hardware has no pitchlock\n");
775 dev_priv
->tdev
= ttm_object_device_init
776 (dev_priv
->mem_global_ref
.object
, 12, &vmw_prime_dmabuf_ops
);
778 if (unlikely(dev_priv
->tdev
== NULL
)) {
779 DRM_ERROR("Unable to initialize TTM object management.\n");
784 dev
->dev_private
= dev_priv
;
786 ret
= pci_request_regions(dev
->pdev
, "vmwgfx probe");
787 dev_priv
->stealth
= (ret
!= 0);
788 if (dev_priv
->stealth
) {
790 * Request at least the mmio PCI resource.
793 DRM_INFO("It appears like vesafb is loaded. "
794 "Ignore above error if any.\n");
795 ret
= pci_request_region(dev
->pdev
, 2, "vmwgfx stealth probe");
796 if (unlikely(ret
!= 0)) {
797 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
802 if (dev_priv
->capabilities
& SVGA_CAP_IRQMASK
) {
803 ret
= drm_irq_install(dev
);
805 DRM_ERROR("Failed installing irq: %d\n", ret
);
810 dev_priv
->fman
= vmw_fence_manager_init(dev_priv
);
811 if (unlikely(dev_priv
->fman
== NULL
)) {
816 vmw_kms_save_vga(dev_priv
);
818 /* Start kms and overlay systems, needs fifo. */
819 ret
= vmw_kms_init(dev_priv
);
820 if (unlikely(ret
!= 0))
822 vmw_overlay_init(dev_priv
);
824 if (dev_priv
->enable_fb
) {
825 ret
= vmw_3d_resource_inc(dev_priv
, true);
826 if (unlikely(ret
!= 0))
828 vmw_fb_init(dev_priv
);
831 dev_priv
->pm_nb
.notifier_call
= vmwgfx_pm_notifier
;
832 register_pm_notifier(&dev_priv
->pm_nb
);
837 vmw_overlay_close(dev_priv
);
838 vmw_kms_close(dev_priv
);
840 vmw_kms_restore_vga(dev_priv
);
841 vmw_fence_manager_takedown(dev_priv
->fman
);
843 if (dev_priv
->capabilities
& SVGA_CAP_IRQMASK
)
844 drm_irq_uninstall(dev_priv
->dev
);
846 if (dev_priv
->stealth
)
847 pci_release_region(dev
->pdev
, 2);
849 pci_release_regions(dev
->pdev
);
851 ttm_object_device_release(&dev_priv
->tdev
);
853 iounmap(dev_priv
->mmio_virt
);
855 arch_phys_wc_del(dev_priv
->mmio_mtrr
);
856 if (dev_priv
->has_mob
)
857 (void) ttm_bo_clean_mm(&dev_priv
->bdev
, VMW_PL_MOB
);
858 if (dev_priv
->has_gmr
)
859 (void) ttm_bo_clean_mm(&dev_priv
->bdev
, VMW_PL_GMR
);
860 (void)ttm_bo_clean_mm(&dev_priv
->bdev
, TTM_PL_VRAM
);
862 (void)ttm_bo_device_release(&dev_priv
->bdev
);
864 vmw_ttm_global_release(dev_priv
);
866 for (i
= vmw_res_context
; i
< vmw_res_max
; ++i
)
867 idr_destroy(&dev_priv
->res_idr
[i
]);
873 static int vmw_driver_unload(struct drm_device
*dev
)
875 struct vmw_private
*dev_priv
= vmw_priv(dev
);
878 unregister_pm_notifier(&dev_priv
->pm_nb
);
880 if (dev_priv
->ctx
.res_ht_initialized
)
881 drm_ht_remove(&dev_priv
->ctx
.res_ht
);
882 if (dev_priv
->ctx
.cmd_bounce
)
883 vfree(dev_priv
->ctx
.cmd_bounce
);
884 if (dev_priv
->enable_fb
) {
885 vmw_fb_close(dev_priv
);
886 vmw_kms_restore_vga(dev_priv
);
887 vmw_3d_resource_dec(dev_priv
, false);
889 vmw_kms_close(dev_priv
);
890 vmw_overlay_close(dev_priv
);
891 vmw_fence_manager_takedown(dev_priv
->fman
);
892 if (dev_priv
->capabilities
& SVGA_CAP_IRQMASK
)
893 drm_irq_uninstall(dev_priv
->dev
);
894 if (dev_priv
->stealth
)
895 pci_release_region(dev
->pdev
, 2);
897 pci_release_regions(dev
->pdev
);
899 ttm_object_device_release(&dev_priv
->tdev
);
900 iounmap(dev_priv
->mmio_virt
);
901 arch_phys_wc_del(dev_priv
->mmio_mtrr
);
902 if (dev_priv
->has_mob
)
903 (void) ttm_bo_clean_mm(&dev_priv
->bdev
, VMW_PL_MOB
);
904 if (dev_priv
->has_gmr
)
905 (void)ttm_bo_clean_mm(&dev_priv
->bdev
, VMW_PL_GMR
);
906 (void)ttm_bo_clean_mm(&dev_priv
->bdev
, TTM_PL_VRAM
);
907 (void)ttm_bo_device_release(&dev_priv
->bdev
);
908 vmw_ttm_global_release(dev_priv
);
910 for (i
= vmw_res_context
; i
< vmw_res_max
; ++i
)
911 idr_destroy(&dev_priv
->res_idr
[i
]);
918 static void vmw_preclose(struct drm_device
*dev
,
919 struct drm_file
*file_priv
)
921 struct vmw_fpriv
*vmw_fp
= vmw_fpriv(file_priv
);
922 struct vmw_private
*dev_priv
= vmw_priv(dev
);
924 vmw_event_fence_fpriv_gone(dev_priv
->fman
, &vmw_fp
->fence_events
);
927 static void vmw_postclose(struct drm_device
*dev
,
928 struct drm_file
*file_priv
)
930 struct vmw_fpriv
*vmw_fp
;
932 vmw_fp
= vmw_fpriv(file_priv
);
934 if (vmw_fp
->locked_master
) {
935 struct vmw_master
*vmaster
=
936 vmw_master(vmw_fp
->locked_master
);
938 ttm_lock_set_kill(&vmaster
->lock
, true, SIGTERM
);
939 ttm_vt_unlock(&vmaster
->lock
);
940 drm_master_put(&vmw_fp
->locked_master
);
943 ttm_object_file_release(&vmw_fp
->tfile
);
947 static int vmw_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
)
949 struct vmw_private
*dev_priv
= vmw_priv(dev
);
950 struct vmw_fpriv
*vmw_fp
;
953 vmw_fp
= kzalloc(sizeof(*vmw_fp
), GFP_KERNEL
);
954 if (unlikely(vmw_fp
== NULL
))
957 INIT_LIST_HEAD(&vmw_fp
->fence_events
);
958 vmw_fp
->tfile
= ttm_object_file_init(dev_priv
->tdev
, 10);
959 if (unlikely(vmw_fp
->tfile
== NULL
))
962 file_priv
->driver_priv
= vmw_fp
;
963 dev_priv
->bdev
.dev_mapping
= dev
->dev_mapping
;
972 static long vmw_unlocked_ioctl(struct file
*filp
, unsigned int cmd
,
975 struct drm_file
*file_priv
= filp
->private_data
;
976 struct drm_device
*dev
= file_priv
->minor
->dev
;
977 unsigned int nr
= DRM_IOCTL_NR(cmd
);
980 * Do extra checking on driver private ioctls.
983 if ((nr
>= DRM_COMMAND_BASE
) && (nr
< DRM_COMMAND_END
)
984 && (nr
< DRM_COMMAND_BASE
+ dev
->driver
->num_ioctls
)) {
985 const struct drm_ioctl_desc
*ioctl
=
986 &vmw_ioctls
[nr
- DRM_COMMAND_BASE
];
988 if (unlikely(ioctl
->cmd_drv
!= cmd
)) {
989 DRM_ERROR("Invalid command format, ioctl %d\n",
990 nr
- DRM_COMMAND_BASE
);
995 return drm_ioctl(filp
, cmd
, arg
);
998 static void vmw_lastclose(struct drm_device
*dev
)
1000 struct drm_crtc
*crtc
;
1001 struct drm_mode_set set
;
1008 set
.connectors
= NULL
;
1009 set
.num_connectors
= 0;
1011 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
1013 ret
= drm_mode_set_config_internal(&set
);
1019 static void vmw_master_init(struct vmw_master
*vmaster
)
1021 ttm_lock_init(&vmaster
->lock
);
1022 INIT_LIST_HEAD(&vmaster
->fb_surf
);
1023 mutex_init(&vmaster
->fb_surf_mutex
);
1026 static int vmw_master_create(struct drm_device
*dev
,
1027 struct drm_master
*master
)
1029 struct vmw_master
*vmaster
;
1031 vmaster
= kzalloc(sizeof(*vmaster
), GFP_KERNEL
);
1032 if (unlikely(vmaster
== NULL
))
1035 vmw_master_init(vmaster
);
1036 ttm_lock_set_kill(&vmaster
->lock
, true, SIGTERM
);
1037 master
->driver_priv
= vmaster
;
1042 static void vmw_master_destroy(struct drm_device
*dev
,
1043 struct drm_master
*master
)
1045 struct vmw_master
*vmaster
= vmw_master(master
);
1047 master
->driver_priv
= NULL
;
1052 static int vmw_master_set(struct drm_device
*dev
,
1053 struct drm_file
*file_priv
,
1056 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1057 struct vmw_fpriv
*vmw_fp
= vmw_fpriv(file_priv
);
1058 struct vmw_master
*active
= dev_priv
->active_master
;
1059 struct vmw_master
*vmaster
= vmw_master(file_priv
->master
);
1062 if (!dev_priv
->enable_fb
) {
1063 ret
= vmw_3d_resource_inc(dev_priv
, true);
1064 if (unlikely(ret
!= 0))
1066 vmw_kms_save_vga(dev_priv
);
1067 mutex_lock(&dev_priv
->hw_mutex
);
1068 vmw_write(dev_priv
, SVGA_REG_TRACES
, 0);
1069 mutex_unlock(&dev_priv
->hw_mutex
);
1073 BUG_ON(active
!= &dev_priv
->fbdev_master
);
1074 ret
= ttm_vt_lock(&active
->lock
, false, vmw_fp
->tfile
);
1075 if (unlikely(ret
!= 0))
1076 goto out_no_active_lock
;
1078 ttm_lock_set_kill(&active
->lock
, true, SIGTERM
);
1079 ret
= ttm_bo_evict_mm(&dev_priv
->bdev
, TTM_PL_VRAM
);
1080 if (unlikely(ret
!= 0)) {
1081 DRM_ERROR("Unable to clean VRAM on "
1085 dev_priv
->active_master
= NULL
;
1088 ttm_lock_set_kill(&vmaster
->lock
, false, SIGTERM
);
1090 ttm_vt_unlock(&vmaster
->lock
);
1091 BUG_ON(vmw_fp
->locked_master
!= file_priv
->master
);
1092 drm_master_put(&vmw_fp
->locked_master
);
1095 dev_priv
->active_master
= vmaster
;
1100 if (!dev_priv
->enable_fb
) {
1101 vmw_kms_restore_vga(dev_priv
);
1102 vmw_3d_resource_dec(dev_priv
, true);
1103 mutex_lock(&dev_priv
->hw_mutex
);
1104 vmw_write(dev_priv
, SVGA_REG_TRACES
, 1);
1105 mutex_unlock(&dev_priv
->hw_mutex
);
1110 static void vmw_master_drop(struct drm_device
*dev
,
1111 struct drm_file
*file_priv
,
1114 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1115 struct vmw_fpriv
*vmw_fp
= vmw_fpriv(file_priv
);
1116 struct vmw_master
*vmaster
= vmw_master(file_priv
->master
);
1120 * Make sure the master doesn't disappear while we have
1124 vmw_fp
->locked_master
= drm_master_get(file_priv
->master
);
1125 ret
= ttm_vt_lock(&vmaster
->lock
, false, vmw_fp
->tfile
);
1126 if (unlikely((ret
!= 0))) {
1127 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1128 drm_master_put(&vmw_fp
->locked_master
);
1131 ttm_lock_set_kill(&vmaster
->lock
, false, SIGTERM
);
1132 vmw_execbuf_release_pinned_bo(dev_priv
);
1134 if (!dev_priv
->enable_fb
) {
1135 ret
= ttm_bo_evict_mm(&dev_priv
->bdev
, TTM_PL_VRAM
);
1136 if (unlikely(ret
!= 0))
1137 DRM_ERROR("Unable to clean VRAM on master drop.\n");
1138 vmw_kms_restore_vga(dev_priv
);
1139 vmw_3d_resource_dec(dev_priv
, true);
1140 mutex_lock(&dev_priv
->hw_mutex
);
1141 vmw_write(dev_priv
, SVGA_REG_TRACES
, 1);
1142 mutex_unlock(&dev_priv
->hw_mutex
);
1145 dev_priv
->active_master
= &dev_priv
->fbdev_master
;
1146 ttm_lock_set_kill(&dev_priv
->fbdev_master
.lock
, false, SIGTERM
);
1147 ttm_vt_unlock(&dev_priv
->fbdev_master
.lock
);
1149 if (dev_priv
->enable_fb
)
1150 vmw_fb_on(dev_priv
);
1154 static void vmw_remove(struct pci_dev
*pdev
)
1156 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1161 static int vmwgfx_pm_notifier(struct notifier_block
*nb
, unsigned long val
,
1164 struct vmw_private
*dev_priv
=
1165 container_of(nb
, struct vmw_private
, pm_nb
);
1166 struct vmw_master
*vmaster
= dev_priv
->active_master
;
1169 case PM_HIBERNATION_PREPARE
:
1170 case PM_SUSPEND_PREPARE
:
1171 ttm_suspend_lock(&vmaster
->lock
);
1174 * This empties VRAM and unbinds all GMR bindings.
1175 * Buffer contents is moved to swappable memory.
1177 vmw_execbuf_release_pinned_bo(dev_priv
);
1178 vmw_resource_evict_all(dev_priv
);
1179 ttm_bo_swapout_all(&dev_priv
->bdev
);
1182 case PM_POST_HIBERNATION
:
1183 case PM_POST_SUSPEND
:
1184 case PM_POST_RESTORE
:
1185 ttm_suspend_unlock(&vmaster
->lock
);
1188 case PM_RESTORE_PREPARE
:
1197 * These might not be needed with the virtual SVGA device.
1200 static int vmw_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1202 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1203 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1205 if (dev_priv
->num_3d_resources
!= 0) {
1206 DRM_INFO("Can't suspend or hibernate "
1207 "while 3D resources are active.\n");
1211 pci_save_state(pdev
);
1212 pci_disable_device(pdev
);
1213 pci_set_power_state(pdev
, PCI_D3hot
);
1217 static int vmw_pci_resume(struct pci_dev
*pdev
)
1219 pci_set_power_state(pdev
, PCI_D0
);
1220 pci_restore_state(pdev
);
1221 return pci_enable_device(pdev
);
1224 static int vmw_pm_suspend(struct device
*kdev
)
1226 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1227 struct pm_message dummy
;
1231 return vmw_pci_suspend(pdev
, dummy
);
1234 static int vmw_pm_resume(struct device
*kdev
)
1236 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1238 return vmw_pci_resume(pdev
);
1241 static int vmw_pm_prepare(struct device
*kdev
)
1243 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1244 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1245 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1248 * Release 3d reference held by fbdev and potentially
1251 dev_priv
->suspended
= true;
1252 if (dev_priv
->enable_fb
)
1253 vmw_3d_resource_dec(dev_priv
, true);
1255 if (dev_priv
->num_3d_resources
!= 0) {
1257 DRM_INFO("Can't suspend or hibernate "
1258 "while 3D resources are active.\n");
1260 if (dev_priv
->enable_fb
)
1261 vmw_3d_resource_inc(dev_priv
, true);
1262 dev_priv
->suspended
= false;
1269 static void vmw_pm_complete(struct device
*kdev
)
1271 struct pci_dev
*pdev
= to_pci_dev(kdev
);
1272 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1273 struct vmw_private
*dev_priv
= vmw_priv(dev
);
1275 mutex_lock(&dev_priv
->hw_mutex
);
1276 vmw_write(dev_priv
, SVGA_REG_ID
, SVGA_ID_2
);
1277 (void) vmw_read(dev_priv
, SVGA_REG_ID
);
1278 mutex_unlock(&dev_priv
->hw_mutex
);
1281 * Reclaim 3d reference held by fbdev and potentially
1284 if (dev_priv
->enable_fb
)
1285 vmw_3d_resource_inc(dev_priv
, false);
1287 dev_priv
->suspended
= false;
1290 static const struct dev_pm_ops vmw_pm_ops
= {
1291 .prepare
= vmw_pm_prepare
,
1292 .complete
= vmw_pm_complete
,
1293 .suspend
= vmw_pm_suspend
,
1294 .resume
= vmw_pm_resume
,
1297 static const struct file_operations vmwgfx_driver_fops
= {
1298 .owner
= THIS_MODULE
,
1300 .release
= drm_release
,
1301 .unlocked_ioctl
= vmw_unlocked_ioctl
,
1303 .poll
= vmw_fops_poll
,
1304 .read
= vmw_fops_read
,
1305 #if defined(CONFIG_COMPAT)
1306 .compat_ioctl
= drm_compat_ioctl
,
1308 .llseek
= noop_llseek
,
1311 static struct drm_driver driver
= {
1312 .driver_features
= DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
|
1313 DRIVER_MODESET
| DRIVER_PRIME
,
1314 .load
= vmw_driver_load
,
1315 .unload
= vmw_driver_unload
,
1316 .lastclose
= vmw_lastclose
,
1317 .irq_preinstall
= vmw_irq_preinstall
,
1318 .irq_postinstall
= vmw_irq_postinstall
,
1319 .irq_uninstall
= vmw_irq_uninstall
,
1320 .irq_handler
= vmw_irq_handler
,
1321 .get_vblank_counter
= vmw_get_vblank_counter
,
1322 .enable_vblank
= vmw_enable_vblank
,
1323 .disable_vblank
= vmw_disable_vblank
,
1324 .ioctls
= vmw_ioctls
,
1325 .num_ioctls
= DRM_ARRAY_SIZE(vmw_ioctls
),
1326 .master_create
= vmw_master_create
,
1327 .master_destroy
= vmw_master_destroy
,
1328 .master_set
= vmw_master_set
,
1329 .master_drop
= vmw_master_drop
,
1330 .open
= vmw_driver_open
,
1331 .preclose
= vmw_preclose
,
1332 .postclose
= vmw_postclose
,
1334 .dumb_create
= vmw_dumb_create
,
1335 .dumb_map_offset
= vmw_dumb_map_offset
,
1336 .dumb_destroy
= vmw_dumb_destroy
,
1338 .prime_fd_to_handle
= vmw_prime_fd_to_handle
,
1339 .prime_handle_to_fd
= vmw_prime_handle_to_fd
,
1341 .fops
= &vmwgfx_driver_fops
,
1342 .name
= VMWGFX_DRIVER_NAME
,
1343 .desc
= VMWGFX_DRIVER_DESC
,
1344 .date
= VMWGFX_DRIVER_DATE
,
1345 .major
= VMWGFX_DRIVER_MAJOR
,
1346 .minor
= VMWGFX_DRIVER_MINOR
,
1347 .patchlevel
= VMWGFX_DRIVER_PATCHLEVEL
1350 static struct pci_driver vmw_pci_driver
= {
1351 .name
= VMWGFX_DRIVER_NAME
,
1352 .id_table
= vmw_pci_id_list
,
1354 .remove
= vmw_remove
,
1360 static int vmw_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1362 return drm_get_pci_dev(pdev
, ent
, &driver
);
1365 static int __init
vmwgfx_init(void)
1368 ret
= drm_pci_init(&driver
, &vmw_pci_driver
);
1370 DRM_ERROR("Failed initializing DRM.\n");
1374 static void __exit
vmwgfx_exit(void)
1376 drm_pci_exit(&driver
, &vmw_pci_driver
);
1379 module_init(vmwgfx_init
);
1380 module_exit(vmwgfx_exit
);
1382 MODULE_AUTHOR("VMware Inc. and others");
1383 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1384 MODULE_LICENSE("GPL and additional rights");
1385 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR
) "."
1386 __stringify(VMWGFX_DRIVER_MINOR
) "."
1387 __stringify(VMWGFX_DRIVER_PATCHLEVEL
) "."