drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

   1 /**************************************************************************
   2  *
   3  * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27 #include <linux/module.h>
  28
  29 #include <drm/drmP.h>
  30 #include "vmwgfx_drv.h"
  31 #include <drm/ttm/ttm_placement.h>
  32 #include <drm/ttm/ttm_bo_driver.h>
  33 #include <drm/ttm/ttm_object.h>
  34 #include <drm/ttm/ttm_module.h>
  35 #include <linux/dma_remapping.h>
  36
  37 #define VMWGFX_DRIVER_NAME "vmwgfx"
  38 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
  39 #define VMWGFX_CHIP_SVGAII 0
  40 #define VMW_FB_RESERVATION 0
  41
  42 #define VMW_MIN_INITIAL_WIDTH 800
  43 #define VMW_MIN_INITIAL_HEIGHT 600
  44
  45
  46 /**
  47  * Fully encoded drm commands. Might move to vmw_drm.h
  48  */
  49
  50 #define DRM_IOCTL_VMW_GET_PARAM                                 \
  51         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM,          \
  52                  struct drm_vmw_getparam_arg)
  53 #define DRM_IOCTL_VMW_ALLOC_DMABUF                              \
  54         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF,       \
  55                 union drm_vmw_alloc_dmabuf_arg)
  56 #define DRM_IOCTL_VMW_UNREF_DMABUF                              \
  57         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF,        \
  58                 struct drm_vmw_unref_dmabuf_arg)
  59 #define DRM_IOCTL_VMW_CURSOR_BYPASS                             \
  60         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS,       \
  61                  struct drm_vmw_cursor_bypass_arg)
  62
  63 #define DRM_IOCTL_VMW_CONTROL_STREAM                            \
  64         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM,      \
  65                  struct drm_vmw_control_stream_arg)
  66 #define DRM_IOCTL_VMW_CLAIM_STREAM                              \
  67         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM,        \
  68                  struct drm_vmw_stream_arg)
  69 #define DRM_IOCTL_VMW_UNREF_STREAM                              \
  70         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM,        \
  71                  struct drm_vmw_stream_arg)
  72
  73 #define DRM_IOCTL_VMW_CREATE_CONTEXT                            \
  74         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT,      \
  75                 struct drm_vmw_context_arg)
  76 #define DRM_IOCTL_VMW_UNREF_CONTEXT                             \
  77         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT,       \
  78                 struct drm_vmw_context_arg)
  79 #define DRM_IOCTL_VMW_CREATE_SURFACE                            \
  80         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE,     \
  81                  union drm_vmw_surface_create_arg)
  82 #define DRM_IOCTL_VMW_UNREF_SURFACE                             \
  83         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE,       \
  84                  struct drm_vmw_surface_arg)
  85 #define DRM_IOCTL_VMW_REF_SURFACE                               \
  86         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE,        \
  87                  union drm_vmw_surface_reference_arg)
  88 #define DRM_IOCTL_VMW_EXECBUF                                   \
  89         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF,             \
  90                 struct drm_vmw_execbuf_arg)
  91 #define DRM_IOCTL_VMW_GET_3D_CAP                                \
  92         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP,          \
  93                  struct drm_vmw_get_3d_cap_arg)
  94 #define DRM_IOCTL_VMW_FENCE_WAIT                                \
  95         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT,         \
  96                  struct drm_vmw_fence_wait_arg)
  97 #define DRM_IOCTL_VMW_FENCE_SIGNALED                            \
  98         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED,     \
  99                  struct drm_vmw_fence_signaled_arg)
 100 #define DRM_IOCTL_VMW_FENCE_UNREF                               \
 101         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF,         \
 102                  struct drm_vmw_fence_arg)
 103 #define DRM_IOCTL_VMW_FENCE_EVENT                               \
 104         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT,         \
 105                  struct drm_vmw_fence_event_arg)
 106 #define DRM_IOCTL_VMW_PRESENT                                   \
 107         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT,             \
 108                  struct drm_vmw_present_arg)
 109 #define DRM_IOCTL_VMW_PRESENT_READBACK                          \
 110         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK,    \
 111                  struct drm_vmw_present_readback_arg)
 112 #define DRM_IOCTL_VMW_UPDATE_LAYOUT                             \
 113         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT,       \
 114                  struct drm_vmw_update_layout_arg)
 115
 116 /**
 117  * The core DRM version of this macro doesn't account for
 118  * DRM_COMMAND_BASE.
 119  */
 120
 121 #define VMW_IOCTL_DEF(ioctl, func, flags) \
 122   [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
 123
 124 /**
 125  * Ioctl definitions.
 126  */
 127
 128 static const struct drm_ioctl_desc vmw_ioctls[] = {
 129         VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
 130                       DRM_AUTH | DRM_UNLOCKED),
 131         VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
 132                       DRM_AUTH | DRM_UNLOCKED),
 133         VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
 134                       DRM_AUTH | DRM_UNLOCKED),
 135         VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
 136                       vmw_kms_cursor_bypass_ioctl,
 137                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 138
 139         VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
 140                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 141         VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
 142                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 143         VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
 144                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 145
 146         VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
 147                       DRM_AUTH | DRM_UNLOCKED),
 148         VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
 149                       DRM_AUTH | DRM_UNLOCKED),
 150         VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
 151                       DRM_AUTH | DRM_UNLOCKED),
 152         VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
 153                       DRM_AUTH | DRM_UNLOCKED),
 154         VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
 155                       DRM_AUTH | DRM_UNLOCKED),
 156         VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
 157                       DRM_AUTH | DRM_UNLOCKED),
 158         VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
 159                       DRM_AUTH | DRM_UNLOCKED),
 160         VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
 161                       vmw_fence_obj_signaled_ioctl,
 162                       DRM_AUTH | DRM_UNLOCKED),
 163         VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
 164                       DRM_AUTH | DRM_UNLOCKED),
 165         VMW_IOCTL_DEF(VMW_FENCE_EVENT,
 166                       vmw_fence_event_ioctl,
 167                       DRM_AUTH | DRM_UNLOCKED),
 168         VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
 169                       DRM_AUTH | DRM_UNLOCKED),
 170
 171         /* these allow direct access to the framebuffers mark as master only */
 172         VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
 173                       DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
 174         VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
 175                       vmw_present_readback_ioctl,
 176                       DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
 177         VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
 178                       vmw_kms_update_layout_ioctl,
 179                       DRM_MASTER | DRM_UNLOCKED),
 180 };
 181
 182 static struct pci_device_id vmw_pci_id_list[] = {
 183         {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
 184         {0, 0, 0}
 185 };
 186 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
 187
 188 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
 189 static int vmw_force_iommu;
 190 static int vmw_restrict_iommu;
 191 static int vmw_force_coherent;
 192 static int vmw_restrict_dma_mask;
 193
 194 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
 195 static void vmw_master_init(struct vmw_master *);
 196 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
 197                               void *ptr);
 198
 199 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
 200 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
 201 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
 202 module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
 203 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
 204 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
 205 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
 206 module_param_named(force_coherent, vmw_force_coherent, int, 0600);
 207 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
 208 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
 209
 210
 211 static void vmw_print_capabilities(uint32_t capabilities)
 212 {
 213         DRM_INFO("Capabilities:\n");
 214         if (capabilities & SVGA_CAP_RECT_COPY)
 215                 DRM_INFO("  Rect copy.\n");
 216         if (capabilities & SVGA_CAP_CURSOR)
 217                 DRM_INFO("  Cursor.\n");
 218         if (capabilities & SVGA_CAP_CURSOR_BYPASS)
 219                 DRM_INFO("  Cursor bypass.\n");
 220         if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
 221                 DRM_INFO("  Cursor bypass 2.\n");
 222         if (capabilities & SVGA_CAP_8BIT_EMULATION)
 223                 DRM_INFO("  8bit emulation.\n");
 224         if (capabilities & SVGA_CAP_ALPHA_CURSOR)
 225                 DRM_INFO("  Alpha cursor.\n");
 226         if (capabilities & SVGA_CAP_3D)
 227                 DRM_INFO("  3D.\n");
 228         if (capabilities & SVGA_CAP_EXTENDED_FIFO)
 229                 DRM_INFO("  Extended Fifo.\n");
 230         if (capabilities & SVGA_CAP_MULTIMON)
 231                 DRM_INFO("  Multimon.\n");
 232         if (capabilities & SVGA_CAP_PITCHLOCK)
 233                 DRM_INFO("  Pitchlock.\n");
 234         if (capabilities & SVGA_CAP_IRQMASK)
 235                 DRM_INFO("  Irq mask.\n");
 236         if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
 237                 DRM_INFO("  Display Topology.\n");
 238         if (capabilities & SVGA_CAP_GMR)
 239                 DRM_INFO("  GMR.\n");
 240         if (capabilities & SVGA_CAP_TRACES)
 241                 DRM_INFO("  Traces.\n");
 242         if (capabilities & SVGA_CAP_GMR2)
 243                 DRM_INFO("  GMR2.\n");
 244         if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
 245                 DRM_INFO("  Screen Object 2.\n");
 246         if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
 247                 DRM_INFO("  Command Buffers.\n");
 248         if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
 249                 DRM_INFO("  Command Buffers 2.\n");
 250         if (capabilities & SVGA_CAP_GBOBJECTS)
 251                 DRM_INFO("  Guest Backed Resources.\n");
 252 }
 253
 254
 255 /**
 256  * vmw_execbuf_prepare_dummy_query - Initialize a query result structure at
 257  * the start of a buffer object.
 258  *
 259  * @dev_priv: The device private structure.
 260  *
 261  * This function will idle the buffer using an uninterruptible wait, then
 262  * map the first page and initialize a pending occlusion query result structure,
 263  * Finally it will unmap the buffer.
 264  *
 265  * TODO: Since we're only mapping a single page, we should optimize the map
 266  * to use kmap_atomic / iomap_atomic.
 267  */
 268 static void vmw_dummy_query_bo_prepare(struct vmw_private *dev_priv)
 269 {
 270         struct ttm_bo_kmap_obj map;
 271         volatile SVGA3dQueryResult *result;
 272         bool dummy;
 273         int ret;
 274         struct ttm_bo_device *bdev = &dev_priv->bdev;
 275         struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
 276
 277         ttm_bo_reserve(bo, false, false, false, 0);
 278         spin_lock(&bdev->fence_lock);
 279         ret = ttm_bo_wait(bo, false, false, false);
 280         spin_unlock(&bdev->fence_lock);
 281         if (unlikely(ret != 0))
 282                 (void) vmw_fallback_wait(dev_priv, false, true, 0, false,
 283                                          10*HZ);
 284
 285         ret = ttm_bo_kmap(bo, 0, 1, &map);
 286         if (likely(ret == 0)) {
 287                 result = ttm_kmap_obj_virtual(&map, &dummy);
 288                 result->totalSize = sizeof(*result);
 289                 result->state = SVGA3D_QUERYSTATE_PENDING;
 290                 result->result32 = 0xff;
 291                 ttm_bo_kunmap(&map);
 292         } else
 293                 DRM_ERROR("Dummy query buffer map failed.\n");
 294         ttm_bo_unreserve(bo);
 295 }
 296
 297
 298 /**
 299  * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
 300  *
 301  * @dev_priv: A device private structure.
 302  *
 303  * This function creates a small buffer object that holds the query
 304  * result for dummy queries emitted as query barriers.
 305  * No interruptible waits are done within this function.
 306  *
 307  * Returns an error if bo creation fails.
 308  */
 309 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
 310 {
 311         return ttm_bo_create(&dev_priv->bdev,
 312                              PAGE_SIZE,
 313                              ttm_bo_type_device,
 314                              &vmw_vram_sys_placement,
 315                              0, false, NULL,
 316                              &dev_priv->dummy_query_bo);
 317 }
 318
 319
 320 static int vmw_request_device(struct vmw_private *dev_priv)
 321 {
 322         int ret;
 323
 324         ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
 325         if (unlikely(ret != 0)) {
 326                 DRM_ERROR("Unable to initialize FIFO.\n");
 327                 return ret;
 328         }
 329         vmw_fence_fifo_up(dev_priv->fman);
 330         if (dev_priv->has_mob) {
 331                 ret = vmw_otables_setup(dev_priv);
 332                 if (unlikely(ret != 0)) {
 333                         DRM_ERROR("Unable to initialize "
 334                                   "guest Memory OBjects.\n");
 335                         goto out_no_mob;
 336                 }
 337         }
 338         ret = vmw_dummy_query_bo_create(dev_priv);
 339         if (unlikely(ret != 0))
 340                 goto out_no_query_bo;
 341         vmw_dummy_query_bo_prepare(dev_priv);
 342
 343         return 0;
 344
 345 out_no_query_bo:
 346         if (dev_priv->has_mob)
 347                 vmw_otables_takedown(dev_priv);
 348 out_no_mob:
 349         vmw_fence_fifo_down(dev_priv->fman);
 350         vmw_fifo_release(dev_priv, &dev_priv->fifo);
 351         return ret;
 352 }
 353
 354 static void vmw_release_device(struct vmw_private *dev_priv)
 355 {
 356         /*
 357          * Previous destructions should've released
 358          * the pinned bo.
 359          */
 360
 361         BUG_ON(dev_priv->pinned_bo != NULL);
 362
 363         ttm_bo_unref(&dev_priv->dummy_query_bo);
 364         if (dev_priv->has_mob)
 365                 vmw_otables_takedown(dev_priv);
 366         vmw_fence_fifo_down(dev_priv->fman);
 367         vmw_fifo_release(dev_priv, &dev_priv->fifo);
 368 }
 369
 370
 371 /**
 372  * Increase the 3d resource refcount.
 373  * If the count was prevously zero, initialize the fifo, switching to svga
 374  * mode. Note that the master holds a ref as well, and may request an
 375  * explicit switch to svga mode if fb is not running, using @unhide_svga.
 376  */
 377 int vmw_3d_resource_inc(struct vmw_private *dev_priv,
 378                         bool unhide_svga)
 379 {
 380         int ret = 0;
 381
 382         mutex_lock(&dev_priv->release_mutex);
 383         if (unlikely(dev_priv->num_3d_resources++ == 0)) {
 384                 ret = vmw_request_device(dev_priv);
 385                 if (unlikely(ret != 0))
 386                         --dev_priv->num_3d_resources;
 387         } else if (unhide_svga) {
 388                 mutex_lock(&dev_priv->hw_mutex);
 389                 vmw_write(dev_priv, SVGA_REG_ENABLE,
 390                           vmw_read(dev_priv, SVGA_REG_ENABLE) &
 391                           ~SVGA_REG_ENABLE_HIDE);
 392                 mutex_unlock(&dev_priv->hw_mutex);
 393         }
 394
 395         mutex_unlock(&dev_priv->release_mutex);
 396         return ret;
 397 }
 398
 399 /**
 400  * Decrease the 3d resource refcount.
 401  * If the count reaches zero, disable the fifo, switching to vga mode.
 402  * Note that the master holds a refcount as well, and may request an
 403  * explicit switch to vga mode when it releases its refcount to account
 404  * for the situation of an X server vt switch to VGA with 3d resources
 405  * active.
 406  */
 407 void vmw_3d_resource_dec(struct vmw_private *dev_priv,
 408                          bool hide_svga)
 409 {
 410         int32_t n3d;
 411
 412         mutex_lock(&dev_priv->release_mutex);
 413         if (unlikely(--dev_priv->num_3d_resources == 0))
 414                 vmw_release_device(dev_priv);
 415         else if (hide_svga) {
 416                 mutex_lock(&dev_priv->hw_mutex);
 417                 vmw_write(dev_priv, SVGA_REG_ENABLE,
 418                           vmw_read(dev_priv, SVGA_REG_ENABLE) |
 419                           SVGA_REG_ENABLE_HIDE);
 420                 mutex_unlock(&dev_priv->hw_mutex);
 421         }
 422
 423         n3d = (int32_t) dev_priv->num_3d_resources;
 424         mutex_unlock(&dev_priv->release_mutex);
 425
 426         BUG_ON(n3d < 0);
 427 }
 428
 429 /**
 430  * Sets the initial_[width|height] fields on the given vmw_private.
 431  *
 432  * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
 433  * clamping the value to fb_max_[width|height] fields and the
 434  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
 435  * If the values appear to be invalid, set them to
 436  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
 437  */
 438 static void vmw_get_initial_size(struct vmw_private *dev_priv)
 439 {
 440         uint32_t width;
 441         uint32_t height;
 442
 443         width = vmw_read(dev_priv, SVGA_REG_WIDTH);
 444         height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
 445
 446         width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
 447         height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
 448
 449         if (width > dev_priv->fb_max_width ||
 450             height > dev_priv->fb_max_height) {
 451
 452                 /*
 453                  * This is a host error and shouldn't occur.
 454                  */
 455
 456                 width = VMW_MIN_INITIAL_WIDTH;
 457                 height = VMW_MIN_INITIAL_HEIGHT;
 458         }
 459
 460         dev_priv->initial_width = width;
 461         dev_priv->initial_height = height;
 462 }
 463
 464 /**
 465  * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
 466  * system.
 467  *
 468  * @dev_priv: Pointer to a struct vmw_private
 469  *
 470  * This functions tries to determine the IOMMU setup and what actions
 471  * need to be taken by the driver to make system pages visible to the
 472  * device.
 473  * If this function decides that DMA is not possible, it returns -EINVAL.
 474  * The driver may then try to disable features of the device that require
 475  * DMA.
 476  */
 477 static int vmw_dma_select_mode(struct vmw_private *dev_priv)
 478 {
 479         static const char *names[vmw_dma_map_max] = {
 480                 [vmw_dma_phys] = "Using physical TTM page addresses.",
 481                 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
 482                 [vmw_dma_map_populate] = "Keeping DMA mappings.",
 483                 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
 484 #ifdef CONFIG_X86
 485         const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
 486
 487 #ifdef CONFIG_INTEL_IOMMU
 488         if (intel_iommu_enabled) {
 489                 dev_priv->map_mode = vmw_dma_map_populate;
 490                 goto out_fixup;
 491         }
 492 #endif
 493
 494         if (!(vmw_force_iommu || vmw_force_coherent)) {
 495                 dev_priv->map_mode = vmw_dma_phys;
 496                 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
 497                 return 0;
 498         }
 499
 500         dev_priv->map_mode = vmw_dma_map_populate;
 501
 502         if (dma_ops->sync_single_for_cpu)
 503                 dev_priv->map_mode = vmw_dma_alloc_coherent;
 504 #ifdef CONFIG_SWIOTLB
 505         if (swiotlb_nr_tbl() == 0)
 506                 dev_priv->map_mode = vmw_dma_map_populate;
 507 #endif
 508
 509 #ifdef CONFIG_INTEL_IOMMU
 510 out_fixup:
 511 #endif
 512         if (dev_priv->map_mode == vmw_dma_map_populate &&
 513             vmw_restrict_iommu)
 514                 dev_priv->map_mode = vmw_dma_map_bind;
 515
 516         if (vmw_force_coherent)
 517                 dev_priv->map_mode = vmw_dma_alloc_coherent;
 518
 519 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
 520         /*
 521          * No coherent page pool
 522          */
 523         if (dev_priv->map_mode == vmw_dma_alloc_coherent)
 524                 return -EINVAL;
 525 #endif
 526
 527 #else /* CONFIG_X86 */
 528         dev_priv->map_mode = vmw_dma_map_populate;
 529 #endif /* CONFIG_X86 */
 530
 531         DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
 532
 533         return 0;
 534 }
 535
 536 /**
 537  * vmw_dma_masks - set required page- and dma masks
 538  *
 539  * @dev: Pointer to struct drm-device
 540  *
 541  * With 32-bit we can only handle 32 bit PFNs. Optionally set that
 542  * restriction also for 64-bit systems.
 543  */
 544 #ifdef CONFIG_INTEL_IOMMU
 545 static int vmw_dma_masks(struct vmw_private *dev_priv)
 546 {
 547         struct drm_device *dev = dev_priv->dev;
 548
 549         if (intel_iommu_enabled &&
 550             (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
 551                 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
 552                 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
 553         }
 554         return 0;
 555 }
 556 #else
 557 static int vmw_dma_masks(struct vmw_private *dev_priv)
 558 {
 559         return 0;
 560 }
 561 #endif
 562
 563 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
 564 {
 565         struct vmw_private *dev_priv;
 566         int ret;
 567         uint32_t svga_id;
 568         enum vmw_res_type i;
 569         bool refuse_dma = false;
 570
 571         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 572         if (unlikely(dev_priv == NULL)) {
 573                 DRM_ERROR("Failed allocating a device private struct.\n");
 574                 return -ENOMEM;
 575         }
 576
 577         pci_set_master(dev->pdev);
 578
 579         dev_priv->dev = dev;
 580         dev_priv->vmw_chipset = chipset;
 581         dev_priv->last_read_seqno = (uint32_t) -100;
 582         mutex_init(&dev_priv->hw_mutex);
 583         mutex_init(&dev_priv->cmdbuf_mutex);
 584         mutex_init(&dev_priv->release_mutex);
 585         rwlock_init(&dev_priv->resource_lock);
 586
 587         for (i = vmw_res_context; i < vmw_res_max; ++i) {
 588                 idr_init(&dev_priv->res_idr[i]);
 589                 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
 590         }
 591
 592         mutex_init(&dev_priv->init_mutex);
 593         init_waitqueue_head(&dev_priv->fence_queue);
 594         init_waitqueue_head(&dev_priv->fifo_queue);
 595         dev_priv->fence_queue_waiters = 0;
 596         atomic_set(&dev_priv->fifo_queue_waiters, 0);
 597
 598         dev_priv->used_memory_size = 0;
 599
 600         dev_priv->io_start = pci_resource_start(dev->pdev, 0);
 601         dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
 602         dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
 603
 604         dev_priv->enable_fb = enable_fbdev;
 605
 606         mutex_lock(&dev_priv->hw_mutex);
 607
 608         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
 609         svga_id = vmw_read(dev_priv, SVGA_REG_ID);
 610         if (svga_id != SVGA_ID_2) {
 611                 ret = -ENOSYS;
 612                 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
 613                 mutex_unlock(&dev_priv->hw_mutex);
 614                 goto out_err0;
 615         }
 616
 617         dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
 618         ret = vmw_dma_select_mode(dev_priv);
 619         if (unlikely(ret != 0)) {
 620                 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
 621                 refuse_dma = true;
 622         }
 623
 624         dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
 625         dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
 626         dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
 627         dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
 628
 629         vmw_get_initial_size(dev_priv);
 630
 631         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 632                 dev_priv->max_gmr_ids =
 633                         vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
 634                 dev_priv->max_gmr_pages =
 635                         vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
 636                 dev_priv->memory_size =
 637                         vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
 638                 dev_priv->memory_size -= dev_priv->vram_size;
 639         } else {
 640                 /*
 641                  * An arbitrary limit of 512MiB on surface
 642                  * memory. But all HWV8 hardware supports GMR2.
 643                  */
 644                 dev_priv->memory_size = 512*1024*1024;
 645         }
 646         dev_priv->max_mob_pages = 0;
 647         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
 648                 uint64_t mem_size =
 649                         vmw_read(dev_priv,
 650                                  SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
 651
 652                 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
 653                 dev_priv->prim_bb_mem =
 654                         vmw_read(dev_priv,
 655                                  SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
 656         } else
 657                 dev_priv->prim_bb_mem = dev_priv->vram_size;
 658
 659         ret = vmw_dma_masks(dev_priv);
 660         if (unlikely(ret != 0))
 661                 goto out_err0;
 662
 663         if (unlikely(dev_priv->prim_bb_mem < dev_priv->vram_size))
 664                 dev_priv->prim_bb_mem = dev_priv->vram_size;
 665
 666         mutex_unlock(&dev_priv->hw_mutex);
 667
 668         vmw_print_capabilities(dev_priv->capabilities);
 669
 670         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 671                 DRM_INFO("Max GMR ids is %u\n",
 672                          (unsigned)dev_priv->max_gmr_ids);
 673                 DRM_INFO("Max number of GMR pages is %u\n",
 674                          (unsigned)dev_priv->max_gmr_pages);
 675                 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
 676                          (unsigned)dev_priv->memory_size / 1024);
 677         }
 678         DRM_INFO("Maximum display memory size is %u kiB\n",
 679                  dev_priv->prim_bb_mem / 1024);
 680         DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
 681                  dev_priv->vram_start, dev_priv->vram_size / 1024);
 682         DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
 683                  dev_priv->mmio_start, dev_priv->mmio_size / 1024);
 684
 685         ret = vmw_ttm_global_init(dev_priv);
 686         if (unlikely(ret != 0))
 687                 goto out_err0;
 688
 689
 690         vmw_master_init(&dev_priv->fbdev_master);
 691         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
 692         dev_priv->active_master = &dev_priv->fbdev_master;
 693
 694
 695         ret = ttm_bo_device_init(&dev_priv->bdev,
 696                                  dev_priv->bo_global_ref.ref.object,
 697                                  &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET,
 698                                  false);
 699         if (unlikely(ret != 0)) {
 700                 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
 701                 goto out_err1;
 702         }
 703
 704         ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
 705                              (dev_priv->vram_size >> PAGE_SHIFT));
 706         if (unlikely(ret != 0)) {
 707                 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
 708                 goto out_err2;
 709         }
 710
 711         dev_priv->has_gmr = true;
 712         if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
 713             refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
 714                                          VMW_PL_GMR) != 0) {
 715                 DRM_INFO("No GMR memory available. "
 716                          "Graphics memory resources are very limited.\n");
 717                 dev_priv->has_gmr = false;
 718         }
 719
 720         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
 721                 dev_priv->has_mob = true;
 722                 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
 723                                    VMW_PL_MOB) != 0) {
 724                         DRM_INFO("No MOB memory available. "
 725                                  "3D will be disabled.\n");
 726                         dev_priv->has_mob = false;
 727                 }
 728         }
 729
 730         dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start,
 731                                                dev_priv->mmio_size);
 732
 733         dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
 734                                          dev_priv->mmio_size);
 735
 736         if (unlikely(dev_priv->mmio_virt == NULL)) {
 737                 ret = -ENOMEM;
 738                 DRM_ERROR("Failed mapping MMIO.\n");
 739                 goto out_err3;
 740         }
 741
 742         /* Need mmio memory to check for fifo pitchlock cap. */
 743         if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
 744             !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
 745             !vmw_fifo_have_pitchlock(dev_priv)) {
 746                 ret = -ENOSYS;
 747                 DRM_ERROR("Hardware has no pitchlock\n");
 748                 goto out_err4;
 749         }
 750
 751         dev_priv->tdev = ttm_object_device_init
 752                 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
 753
 754         if (unlikely(dev_priv->tdev == NULL)) {
 755                 DRM_ERROR("Unable to initialize TTM object management.\n");
 756                 ret = -ENOMEM;
 757                 goto out_err4;
 758         }
 759
 760         dev->dev_private = dev_priv;
 761
 762         ret = pci_request_regions(dev->pdev, "vmwgfx probe");
 763         dev_priv->stealth = (ret != 0);
 764         if (dev_priv->stealth) {
 765                 /**
 766                  * Request at least the mmio PCI resource.
 767                  */
 768
 769                 DRM_INFO("It appears like vesafb is loaded. "
 770                          "Ignore above error if any.\n");
 771                 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
 772                 if (unlikely(ret != 0)) {
 773                         DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
 774                         goto out_no_device;
 775                 }
 776         }
 777
 778         if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
 779                 ret = drm_irq_install(dev);
 780                 if (ret != 0) {
 781                         DRM_ERROR("Failed installing irq: %d\n", ret);
 782                         goto out_no_irq;
 783                 }
 784         }
 785
 786         dev_priv->fman = vmw_fence_manager_init(dev_priv);
 787         if (unlikely(dev_priv->fman == NULL)) {
 788                 ret = -ENOMEM;
 789                 goto out_no_fman;
 790         }
 791
 792         vmw_kms_save_vga(dev_priv);
 793
 794         /* Start kms and overlay systems, needs fifo. */
 795         ret = vmw_kms_init(dev_priv);
 796         if (unlikely(ret != 0))
 797                 goto out_no_kms;
 798         vmw_overlay_init(dev_priv);
 799
 800         if (dev_priv->enable_fb) {
 801                 ret = vmw_3d_resource_inc(dev_priv, true);
 802                 if (unlikely(ret != 0))
 803                         goto out_no_fifo;
 804                 vmw_fb_init(dev_priv);
 805         }
 806
 807         dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
 808         register_pm_notifier(&dev_priv->pm_nb);
 809
 810         return 0;
 811
 812 out_no_fifo:
 813         vmw_overlay_close(dev_priv);
 814         vmw_kms_close(dev_priv);
 815 out_no_kms:
 816         vmw_kms_restore_vga(dev_priv);
 817         vmw_fence_manager_takedown(dev_priv->fman);
 818 out_no_fman:
 819         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
 820                 drm_irq_uninstall(dev_priv->dev);
 821 out_no_irq:
 822         if (dev_priv->stealth)
 823                 pci_release_region(dev->pdev, 2);
 824         else
 825                 pci_release_regions(dev->pdev);
 826 out_no_device:
 827         ttm_object_device_release(&dev_priv->tdev);
 828 out_err4:
 829         iounmap(dev_priv->mmio_virt);
 830 out_err3:
 831         arch_phys_wc_del(dev_priv->mmio_mtrr);
 832         if (dev_priv->has_mob)
 833                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
 834         if (dev_priv->has_gmr)
 835                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
 836         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
 837 out_err2:
 838         (void)ttm_bo_device_release(&dev_priv->bdev);
 839 out_err1:
 840         vmw_ttm_global_release(dev_priv);
 841 out_err0:
 842         for (i = vmw_res_context; i < vmw_res_max; ++i)
 843                 idr_destroy(&dev_priv->res_idr[i]);
 844
 845         kfree(dev_priv);
 846         return ret;
 847 }
 848
 849 static int vmw_driver_unload(struct drm_device *dev)
 850 {
 851         struct vmw_private *dev_priv = vmw_priv(dev);
 852         enum vmw_res_type i;
 853
 854         unregister_pm_notifier(&dev_priv->pm_nb);
 855
 856         if (dev_priv->ctx.res_ht_initialized)
 857                 drm_ht_remove(&dev_priv->ctx.res_ht);
 858         if (dev_priv->ctx.cmd_bounce)
 859                 vfree(dev_priv->ctx.cmd_bounce);
 860         if (dev_priv->enable_fb) {
 861                 vmw_fb_close(dev_priv);
 862                 vmw_kms_restore_vga(dev_priv);
 863                 vmw_3d_resource_dec(dev_priv, false);
 864         }
 865         vmw_kms_close(dev_priv);
 866         vmw_overlay_close(dev_priv);
 867         vmw_fence_manager_takedown(dev_priv->fman);
 868         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
 869                 drm_irq_uninstall(dev_priv->dev);
 870         if (dev_priv->stealth)
 871                 pci_release_region(dev->pdev, 2);
 872         else
 873                 pci_release_regions(dev->pdev);
 874
 875         ttm_object_device_release(&dev_priv->tdev);
 876         iounmap(dev_priv->mmio_virt);
 877         arch_phys_wc_del(dev_priv->mmio_mtrr);
 878         if (dev_priv->has_mob)
 879                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
 880         if (dev_priv->has_gmr)
 881                 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
 882         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
 883         (void)ttm_bo_device_release(&dev_priv->bdev);
 884         vmw_ttm_global_release(dev_priv);
 885
 886         for (i = vmw_res_context; i < vmw_res_max; ++i)
 887                 idr_destroy(&dev_priv->res_idr[i]);
 888
 889         kfree(dev_priv);
 890
 891         return 0;
 892 }
 893
 894 static void vmw_preclose(struct drm_device *dev,
 895                          struct drm_file *file_priv)
 896 {
 897         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
 898         struct vmw_private *dev_priv = vmw_priv(dev);
 899
 900         vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events);
 901 }
 902
 903 static void vmw_postclose(struct drm_device *dev,
 904                          struct drm_file *file_priv)
 905 {
 906         struct vmw_fpriv *vmw_fp;
 907
 908         vmw_fp = vmw_fpriv(file_priv);
 909
 910         if (vmw_fp->locked_master) {
 911                 struct vmw_master *vmaster =
 912                         vmw_master(vmw_fp->locked_master);
 913
 914                 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
 915                 ttm_vt_unlock(&vmaster->lock);
 916                 drm_master_put(&vmw_fp->locked_master);
 917         }
 918
 919         ttm_object_file_release(&vmw_fp->tfile);
 920         kfree(vmw_fp);
 921 }
 922
 923 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
 924 {
 925         struct vmw_private *dev_priv = vmw_priv(dev);
 926         struct vmw_fpriv *vmw_fp;
 927         int ret = -ENOMEM;
 928
 929         vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
 930         if (unlikely(vmw_fp == NULL))
 931                 return ret;
 932
 933         INIT_LIST_HEAD(&vmw_fp->fence_events);
 934         vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
 935         if (unlikely(vmw_fp->tfile == NULL))
 936                 goto out_no_tfile;
 937
 938         file_priv->driver_priv = vmw_fp;
 939         dev_priv->bdev.dev_mapping = dev->dev_mapping;
 940
 941         return 0;
 942
 943 out_no_tfile:
 944         kfree(vmw_fp);
 945         return ret;
 946 }
 947
 948 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
 949                                unsigned long arg)
 950 {
 951         struct drm_file *file_priv = filp->private_data;
 952         struct drm_device *dev = file_priv->minor->dev;
 953         unsigned int nr = DRM_IOCTL_NR(cmd);
 954
 955         /*
 956          * Do extra checking on driver private ioctls.
 957          */
 958
 959         if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
 960             && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
 961                 const struct drm_ioctl_desc *ioctl =
 962                     &vmw_ioctls[nr - DRM_COMMAND_BASE];
 963
 964                 if (unlikely(ioctl->cmd_drv != cmd)) {
 965                         DRM_ERROR("Invalid command format, ioctl %d\n",
 966                                   nr - DRM_COMMAND_BASE);
 967                         return -EINVAL;
 968                 }
 969         }
 970
 971         return drm_ioctl(filp, cmd, arg);
 972 }
 973
 974 static void vmw_lastclose(struct drm_device *dev)
 975 {
 976         struct drm_crtc *crtc;
 977         struct drm_mode_set set;
 978         int ret;
 979
 980         set.x = 0;
 981         set.y = 0;
 982         set.fb = NULL;
 983         set.mode = NULL;
 984         set.connectors = NULL;
 985         set.num_connectors = 0;
 986
 987         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 988                 set.crtc = crtc;
 989                 ret = drm_mode_set_config_internal(&set);
 990                 WARN_ON(ret != 0);
 991         }
 992
 993 }
 994
 995 static void vmw_master_init(struct vmw_master *vmaster)
 996 {
 997         ttm_lock_init(&vmaster->lock);
 998         INIT_LIST_HEAD(&vmaster->fb_surf);
 999         mutex_init(&vmaster->fb_surf_mutex);
1000 }
1001
1002 static int vmw_master_create(struct drm_device *dev,
1003                              struct drm_master *master)
1004 {
1005         struct vmw_master *vmaster;
1006
1007         vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1008         if (unlikely(vmaster == NULL))
1009                 return -ENOMEM;
1010
1011         vmw_master_init(vmaster);
1012         ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1013         master->driver_priv = vmaster;
1014
1015         return 0;
1016 }
1017
1018 static void vmw_master_destroy(struct drm_device *dev,
1019                                struct drm_master *master)
1020 {
1021         struct vmw_master *vmaster = vmw_master(master);
1022
1023         master->driver_priv = NULL;
1024         kfree(vmaster);
1025 }
1026
1027
1028 static int vmw_master_set(struct drm_device *dev,
1029                           struct drm_file *file_priv,
1030                           bool from_open)
1031 {
1032         struct vmw_private *dev_priv = vmw_priv(dev);
1033         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1034         struct vmw_master *active = dev_priv->active_master;
1035         struct vmw_master *vmaster = vmw_master(file_priv->master);
1036         int ret = 0;
1037
1038         if (!dev_priv->enable_fb) {
1039                 ret = vmw_3d_resource_inc(dev_priv, true);
1040                 if (unlikely(ret != 0))
1041                         return ret;
1042                 vmw_kms_save_vga(dev_priv);
1043                 mutex_lock(&dev_priv->hw_mutex);
1044                 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
1045                 mutex_unlock(&dev_priv->hw_mutex);
1046         }
1047
1048         if (active) {
1049                 BUG_ON(active != &dev_priv->fbdev_master);
1050                 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1051                 if (unlikely(ret != 0))
1052                         goto out_no_active_lock;
1053
1054                 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1055                 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1056                 if (unlikely(ret != 0)) {
1057                         DRM_ERROR("Unable to clean VRAM on "
1058                                   "master drop.\n");
1059                 }
1060
1061                 dev_priv->active_master = NULL;
1062         }
1063
1064         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1065         if (!from_open) {
1066                 ttm_vt_unlock(&vmaster->lock);
1067                 BUG_ON(vmw_fp->locked_master != file_priv->master);
1068                 drm_master_put(&vmw_fp->locked_master);
1069         }
1070
1071         dev_priv->active_master = vmaster;
1072
1073         return 0;
1074
1075 out_no_active_lock:
1076         if (!dev_priv->enable_fb) {
1077                 vmw_kms_restore_vga(dev_priv);
1078                 vmw_3d_resource_dec(dev_priv, true);
1079                 mutex_lock(&dev_priv->hw_mutex);
1080                 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1081                 mutex_unlock(&dev_priv->hw_mutex);
1082         }
1083         return ret;
1084 }
1085
1086 static void vmw_master_drop(struct drm_device *dev,
1087                             struct drm_file *file_priv,
1088                             bool from_release)
1089 {
1090         struct vmw_private *dev_priv = vmw_priv(dev);
1091         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1092         struct vmw_master *vmaster = vmw_master(file_priv->master);
1093         int ret;
1094
1095         /**
1096          * Make sure the master doesn't disappear while we have
1097          * it locked.
1098          */
1099
1100         vmw_fp->locked_master = drm_master_get(file_priv->master);
1101         ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
1102         if (unlikely((ret != 0))) {
1103                 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1104                 drm_master_put(&vmw_fp->locked_master);
1105         }
1106
1107         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1108         vmw_execbuf_release_pinned_bo(dev_priv);
1109
1110         if (!dev_priv->enable_fb) {
1111                 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1112                 if (unlikely(ret != 0))
1113                         DRM_ERROR("Unable to clean VRAM on master drop.\n");
1114                 vmw_kms_restore_vga(dev_priv);
1115                 vmw_3d_resource_dec(dev_priv, true);
1116                 mutex_lock(&dev_priv->hw_mutex);
1117                 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1118                 mutex_unlock(&dev_priv->hw_mutex);
1119         }
1120
1121         dev_priv->active_master = &dev_priv->fbdev_master;
1122         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1123         ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1124
1125         if (dev_priv->enable_fb)
1126                 vmw_fb_on(dev_priv);
1127 }
1128
1129
1130 static void vmw_remove(struct pci_dev *pdev)
1131 {
1132         struct drm_device *dev = pci_get_drvdata(pdev);
1133
1134         drm_put_dev(dev);
1135 }
1136
1137 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1138                               void *ptr)
1139 {
1140         struct vmw_private *dev_priv =
1141                 container_of(nb, struct vmw_private, pm_nb);
1142         struct vmw_master *vmaster = dev_priv->active_master;
1143
1144         switch (val) {
1145         case PM_HIBERNATION_PREPARE:
1146         case PM_SUSPEND_PREPARE:
1147                 ttm_suspend_lock(&vmaster->lock);
1148
1149                 /**
1150                  * This empties VRAM and unbinds all GMR bindings.
1151                  * Buffer contents is moved to swappable memory.
1152                  */
1153                 vmw_execbuf_release_pinned_bo(dev_priv);
1154                 vmw_resource_evict_all(dev_priv);
1155                 ttm_bo_swapout_all(&dev_priv->bdev);
1156
1157                 break;
1158         case PM_POST_HIBERNATION:
1159         case PM_POST_SUSPEND:
1160         case PM_POST_RESTORE:
1161                 ttm_suspend_unlock(&vmaster->lock);
1162
1163                 break;
1164         case PM_RESTORE_PREPARE:
1165                 break;
1166         default:
1167                 break;
1168         }
1169         return 0;
1170 }
1171
1172 /**
1173  * These might not be needed with the virtual SVGA device.
1174  */
1175
1176 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1177 {
1178         struct drm_device *dev = pci_get_drvdata(pdev);
1179         struct vmw_private *dev_priv = vmw_priv(dev);
1180
1181         if (dev_priv->num_3d_resources != 0) {
1182                 DRM_INFO("Can't suspend or hibernate "
1183                          "while 3D resources are active.\n");
1184                 return -EBUSY;
1185         }
1186
1187         pci_save_state(pdev);
1188         pci_disable_device(pdev);
1189         pci_set_power_state(pdev, PCI_D3hot);
1190         return 0;
1191 }
1192
1193 static int vmw_pci_resume(struct pci_dev *pdev)
1194 {
1195         pci_set_power_state(pdev, PCI_D0);
1196         pci_restore_state(pdev);
1197         return pci_enable_device(pdev);
1198 }
1199
1200 static int vmw_pm_suspend(struct device *kdev)
1201 {
1202         struct pci_dev *pdev = to_pci_dev(kdev);
1203         struct pm_message dummy;
1204
1205         dummy.event = 0;
1206
1207         return vmw_pci_suspend(pdev, dummy);
1208 }
1209
1210 static int vmw_pm_resume(struct device *kdev)
1211 {
1212         struct pci_dev *pdev = to_pci_dev(kdev);
1213
1214         return vmw_pci_resume(pdev);
1215 }
1216
1217 static int vmw_pm_prepare(struct device *kdev)
1218 {
1219         struct pci_dev *pdev = to_pci_dev(kdev);
1220         struct drm_device *dev = pci_get_drvdata(pdev);
1221         struct vmw_private *dev_priv = vmw_priv(dev);
1222
1223         /**
1224          * Release 3d reference held by fbdev and potentially
1225          * stop fifo.
1226          */
1227         dev_priv->suspended = true;
1228         if (dev_priv->enable_fb)
1229                         vmw_3d_resource_dec(dev_priv, true);
1230
1231         if (dev_priv->num_3d_resources != 0) {
1232
1233                 DRM_INFO("Can't suspend or hibernate "
1234                          "while 3D resources are active.\n");
1235
1236                 if (dev_priv->enable_fb)
1237                         vmw_3d_resource_inc(dev_priv, true);
1238                 dev_priv->suspended = false;
1239                 return -EBUSY;
1240         }
1241
1242         return 0;
1243 }
1244
1245 static void vmw_pm_complete(struct device *kdev)
1246 {
1247         struct pci_dev *pdev = to_pci_dev(kdev);
1248         struct drm_device *dev = pci_get_drvdata(pdev);
1249         struct vmw_private *dev_priv = vmw_priv(dev);
1250
1251         mutex_lock(&dev_priv->hw_mutex);
1252         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1253         (void) vmw_read(dev_priv, SVGA_REG_ID);
1254         mutex_unlock(&dev_priv->hw_mutex);
1255
1256         /**
1257          * Reclaim 3d reference held by fbdev and potentially
1258          * start fifo.
1259          */
1260         if (dev_priv->enable_fb)
1261                         vmw_3d_resource_inc(dev_priv, false);
1262
1263         dev_priv->suspended = false;
1264 }
1265
1266 static const struct dev_pm_ops vmw_pm_ops = {
1267         .prepare = vmw_pm_prepare,
1268         .complete = vmw_pm_complete,
1269         .suspend = vmw_pm_suspend,
1270         .resume = vmw_pm_resume,
1271 };
1272
1273 static const struct file_operations vmwgfx_driver_fops = {
1274         .owner = THIS_MODULE,
1275         .open = drm_open,
1276         .release = drm_release,
1277         .unlocked_ioctl = vmw_unlocked_ioctl,
1278         .mmap = vmw_mmap,
1279         .poll = vmw_fops_poll,
1280         .read = vmw_fops_read,
1281 #if defined(CONFIG_COMPAT)
1282         .compat_ioctl = drm_compat_ioctl,
1283 #endif
1284         .llseek = noop_llseek,
1285 };
1286
1287 static struct drm_driver driver = {
1288         .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1289         DRIVER_MODESET | DRIVER_PRIME,
1290         .load = vmw_driver_load,
1291         .unload = vmw_driver_unload,
1292         .lastclose = vmw_lastclose,
1293         .irq_preinstall = vmw_irq_preinstall,
1294         .irq_postinstall = vmw_irq_postinstall,
1295         .irq_uninstall = vmw_irq_uninstall,
1296         .irq_handler = vmw_irq_handler,
1297         .get_vblank_counter = vmw_get_vblank_counter,
1298         .enable_vblank = vmw_enable_vblank,
1299         .disable_vblank = vmw_disable_vblank,
1300         .ioctls = vmw_ioctls,
1301         .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
1302         .master_create = vmw_master_create,
1303         .master_destroy = vmw_master_destroy,
1304         .master_set = vmw_master_set,
1305         .master_drop = vmw_master_drop,
1306         .open = vmw_driver_open,
1307         .preclose = vmw_preclose,
1308         .postclose = vmw_postclose,
1309
1310         .dumb_create = vmw_dumb_create,
1311         .dumb_map_offset = vmw_dumb_map_offset,
1312         .dumb_destroy = vmw_dumb_destroy,
1313
1314         .prime_fd_to_handle = vmw_prime_fd_to_handle,
1315         .prime_handle_to_fd = vmw_prime_handle_to_fd,
1316
1317         .fops = &vmwgfx_driver_fops,
1318         .name = VMWGFX_DRIVER_NAME,
1319         .desc = VMWGFX_DRIVER_DESC,
1320         .date = VMWGFX_DRIVER_DATE,
1321         .major = VMWGFX_DRIVER_MAJOR,
1322         .minor = VMWGFX_DRIVER_MINOR,
1323         .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1324 };
1325
1326 static struct pci_driver vmw_pci_driver = {
1327         .name = VMWGFX_DRIVER_NAME,
1328         .id_table = vmw_pci_id_list,
1329         .probe = vmw_probe,
1330         .remove = vmw_remove,
1331         .driver = {
1332                 .pm = &vmw_pm_ops
1333         }
1334 };
1335
1336 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1337 {
1338         return drm_get_pci_dev(pdev, ent, &driver);
1339 }
1340
1341 static int __init vmwgfx_init(void)
1342 {
1343         int ret;
1344         ret = drm_pci_init(&driver, &vmw_pci_driver);
1345         if (ret)
1346                 DRM_ERROR("Failed initializing DRM.\n");
1347         return ret;
1348 }
1349
1350 static void __exit vmwgfx_exit(void)
1351 {
1352         drm_pci_exit(&driver, &vmw_pci_driver);
1353 }
1354
1355 module_init(vmwgfx_init);
1356 module_exit(vmwgfx_exit);
1357
1358 MODULE_AUTHOR("VMware Inc. and others");
1359 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1360 MODULE_LICENSE("GPL and additional rights");
1361 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1362                __stringify(VMWGFX_DRIVER_MINOR) "."
1363                __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1364                "0");