1 /**************************************************************************
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "vmwgfx_drv.h"
30 #include "ttm/ttm_placement.h"
32 bool vmw_fifo_have_3d(struct vmw_private
*dev_priv
)
34 __le32 __iomem
*fifo_mem
= dev_priv
->mmio_virt
;
35 uint32_t fifo_min
, hwversion
;
37 if (!(dev_priv
->capabilities
& SVGA_CAP_EXTENDED_FIFO
))
40 fifo_min
= ioread32(fifo_mem
+ SVGA_FIFO_MIN
);
41 if (fifo_min
<= SVGA_FIFO_3D_HWVERSION
* sizeof(unsigned int))
44 hwversion
= ioread32(fifo_mem
+ SVGA_FIFO_3D_HWVERSION
);
48 if (hwversion
< SVGA3D_HWVERSION_WS65_B1
)
54 bool vmw_fifo_have_pitchlock(struct vmw_private
*dev_priv
)
56 __le32 __iomem
*fifo_mem
= dev_priv
->mmio_virt
;
59 if (!(dev_priv
->capabilities
& SVGA_CAP_EXTENDED_FIFO
))
62 caps
= ioread32(fifo_mem
+ SVGA_FIFO_CAPABILITIES
);
63 if (caps
& SVGA_FIFO_CAP_PITCHLOCK
)
69 int vmw_fifo_init(struct vmw_private
*dev_priv
, struct vmw_fifo_state
*fifo
)
71 __le32 __iomem
*fifo_mem
= dev_priv
->mmio_virt
;
76 fifo
->static_buffer_size
= VMWGFX_FIFO_STATIC_SIZE
;
77 fifo
->static_buffer
= vmalloc(fifo
->static_buffer_size
);
78 if (unlikely(fifo
->static_buffer
== NULL
))
81 fifo
->dynamic_buffer
= NULL
;
82 fifo
->reserved_size
= 0;
83 fifo
->using_bounce_buffer
= false;
85 mutex_init(&fifo
->fifo_mutex
);
86 init_rwsem(&fifo
->rwsem
);
89 * Allow mapping the first page read-only to user-space.
92 DRM_INFO("width %d\n", vmw_read(dev_priv
, SVGA_REG_WIDTH
));
93 DRM_INFO("height %d\n", vmw_read(dev_priv
, SVGA_REG_HEIGHT
));
94 DRM_INFO("bpp %d\n", vmw_read(dev_priv
, SVGA_REG_BITS_PER_PIXEL
));
96 mutex_lock(&dev_priv
->hw_mutex
);
97 dev_priv
->enable_state
= vmw_read(dev_priv
, SVGA_REG_ENABLE
);
98 dev_priv
->config_done_state
= vmw_read(dev_priv
, SVGA_REG_CONFIG_DONE
);
99 dev_priv
->traces_state
= vmw_read(dev_priv
, SVGA_REG_TRACES
);
100 vmw_write(dev_priv
, SVGA_REG_ENABLE
, 1);
103 if (dev_priv
->capabilities
& SVGA_CAP_EXTENDED_FIFO
)
104 min
= vmw_read(dev_priv
, SVGA_REG_MEM_REGS
);
110 iowrite32(min
, fifo_mem
+ SVGA_FIFO_MIN
);
111 iowrite32(dev_priv
->mmio_size
, fifo_mem
+ SVGA_FIFO_MAX
);
113 iowrite32(min
, fifo_mem
+ SVGA_FIFO_NEXT_CMD
);
114 iowrite32(min
, fifo_mem
+ SVGA_FIFO_STOP
);
115 iowrite32(0, fifo_mem
+ SVGA_FIFO_BUSY
);
118 vmw_write(dev_priv
, SVGA_REG_CONFIG_DONE
, 1);
119 mutex_unlock(&dev_priv
->hw_mutex
);
121 max
= ioread32(fifo_mem
+ SVGA_FIFO_MAX
);
122 min
= ioread32(fifo_mem
+ SVGA_FIFO_MIN
);
123 fifo
->capabilities
= ioread32(fifo_mem
+ SVGA_FIFO_CAPABILITIES
);
125 DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
128 (unsigned int) fifo
->capabilities
);
130 atomic_set(&dev_priv
->marker_seq
, dev_priv
->last_read_seqno
);
131 iowrite32(dev_priv
->last_read_seqno
, fifo_mem
+ SVGA_FIFO_FENCE
);
132 vmw_marker_queue_init(&fifo
->marker_queue
);
133 return vmw_fifo_send_fence(dev_priv
, &dummy
);
136 void vmw_fifo_ping_host(struct vmw_private
*dev_priv
, uint32_t reason
)
138 __le32 __iomem
*fifo_mem
= dev_priv
->mmio_virt
;
140 mutex_lock(&dev_priv
->hw_mutex
);
142 if (unlikely(ioread32(fifo_mem
+ SVGA_FIFO_BUSY
) == 0)) {
143 iowrite32(1, fifo_mem
+ SVGA_FIFO_BUSY
);
144 vmw_write(dev_priv
, SVGA_REG_SYNC
, reason
);
147 mutex_unlock(&dev_priv
->hw_mutex
);
150 void vmw_fifo_release(struct vmw_private
*dev_priv
, struct vmw_fifo_state
*fifo
)
152 __le32 __iomem
*fifo_mem
= dev_priv
->mmio_virt
;
154 mutex_lock(&dev_priv
->hw_mutex
);
156 while (vmw_read(dev_priv
, SVGA_REG_BUSY
) != 0)
157 vmw_write(dev_priv
, SVGA_REG_SYNC
, SVGA_SYNC_GENERIC
);
159 dev_priv
->last_read_seqno
= ioread32(fifo_mem
+ SVGA_FIFO_FENCE
);
161 vmw_write(dev_priv
, SVGA_REG_CONFIG_DONE
,
162 dev_priv
->config_done_state
);
163 vmw_write(dev_priv
, SVGA_REG_ENABLE
,
164 dev_priv
->enable_state
);
165 vmw_write(dev_priv
, SVGA_REG_TRACES
,
166 dev_priv
->traces_state
);
168 mutex_unlock(&dev_priv
->hw_mutex
);
169 vmw_marker_queue_takedown(&fifo
->marker_queue
);
171 if (likely(fifo
->static_buffer
!= NULL
)) {
172 vfree(fifo
->static_buffer
);
173 fifo
->static_buffer
= NULL
;
176 if (likely(fifo
->dynamic_buffer
!= NULL
)) {
177 vfree(fifo
->dynamic_buffer
);
178 fifo
->dynamic_buffer
= NULL
;
182 static bool vmw_fifo_is_full(struct vmw_private
*dev_priv
, uint32_t bytes
)
184 __le32 __iomem
*fifo_mem
= dev_priv
->mmio_virt
;
185 uint32_t max
= ioread32(fifo_mem
+ SVGA_FIFO_MAX
);
186 uint32_t next_cmd
= ioread32(fifo_mem
+ SVGA_FIFO_NEXT_CMD
);
187 uint32_t min
= ioread32(fifo_mem
+ SVGA_FIFO_MIN
);
188 uint32_t stop
= ioread32(fifo_mem
+ SVGA_FIFO_STOP
);
190 return ((max
- next_cmd
) + (stop
- min
) <= bytes
);
193 static int vmw_fifo_wait_noirq(struct vmw_private
*dev_priv
,
194 uint32_t bytes
, bool interruptible
,
195 unsigned long timeout
)
198 unsigned long end_jiffies
= jiffies
+ timeout
;
201 DRM_INFO("Fifo wait noirq.\n");
204 prepare_to_wait(&dev_priv
->fifo_queue
, &__wait
,
206 TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
207 if (!vmw_fifo_is_full(dev_priv
, bytes
))
209 if (time_after_eq(jiffies
, end_jiffies
)) {
211 DRM_ERROR("SVGA device lockup.\n");
215 if (interruptible
&& signal_pending(current
)) {
220 finish_wait(&dev_priv
->fifo_queue
, &__wait
);
221 wake_up_all(&dev_priv
->fifo_queue
);
222 DRM_INFO("Fifo noirq exit.\n");
226 static int vmw_fifo_wait(struct vmw_private
*dev_priv
,
227 uint32_t bytes
, bool interruptible
,
228 unsigned long timeout
)
231 unsigned long irq_flags
;
233 if (likely(!vmw_fifo_is_full(dev_priv
, bytes
)))
236 vmw_fifo_ping_host(dev_priv
, SVGA_SYNC_FIFOFULL
);
237 if (!(dev_priv
->capabilities
& SVGA_CAP_IRQMASK
))
238 return vmw_fifo_wait_noirq(dev_priv
, bytes
,
239 interruptible
, timeout
);
241 mutex_lock(&dev_priv
->hw_mutex
);
242 if (atomic_add_return(1, &dev_priv
->fifo_queue_waiters
) > 0) {
243 spin_lock_irqsave(&dev_priv
->irq_lock
, irq_flags
);
244 outl(SVGA_IRQFLAG_FIFO_PROGRESS
,
245 dev_priv
->io_start
+ VMWGFX_IRQSTATUS_PORT
);
246 vmw_write(dev_priv
, SVGA_REG_IRQMASK
,
247 vmw_read(dev_priv
, SVGA_REG_IRQMASK
) |
248 SVGA_IRQFLAG_FIFO_PROGRESS
);
249 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irq_flags
);
251 mutex_unlock(&dev_priv
->hw_mutex
);
254 ret
= wait_event_interruptible_timeout
255 (dev_priv
->fifo_queue
,
256 !vmw_fifo_is_full(dev_priv
, bytes
), timeout
);
258 ret
= wait_event_timeout
259 (dev_priv
->fifo_queue
,
260 !vmw_fifo_is_full(dev_priv
, bytes
), timeout
);
262 if (unlikely(ret
== 0))
264 else if (likely(ret
> 0))
267 mutex_lock(&dev_priv
->hw_mutex
);
268 if (atomic_dec_and_test(&dev_priv
->fifo_queue_waiters
)) {
269 spin_lock_irqsave(&dev_priv
->irq_lock
, irq_flags
);
270 vmw_write(dev_priv
, SVGA_REG_IRQMASK
,
271 vmw_read(dev_priv
, SVGA_REG_IRQMASK
) &
272 ~SVGA_IRQFLAG_FIFO_PROGRESS
);
273 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irq_flags
);
275 mutex_unlock(&dev_priv
->hw_mutex
);
280 void *vmw_fifo_reserve(struct vmw_private
*dev_priv
, uint32_t bytes
)
282 struct vmw_fifo_state
*fifo_state
= &dev_priv
->fifo
;
283 __le32 __iomem
*fifo_mem
= dev_priv
->mmio_virt
;
287 uint32_t reserveable
= fifo_state
->capabilities
& SVGA_FIFO_CAP_RESERVE
;
290 mutex_lock(&fifo_state
->fifo_mutex
);
291 max
= ioread32(fifo_mem
+ SVGA_FIFO_MAX
);
292 min
= ioread32(fifo_mem
+ SVGA_FIFO_MIN
);
293 next_cmd
= ioread32(fifo_mem
+ SVGA_FIFO_NEXT_CMD
);
295 if (unlikely(bytes
>= (max
- min
)))
298 BUG_ON(fifo_state
->reserved_size
!= 0);
299 BUG_ON(fifo_state
->dynamic_buffer
!= NULL
);
301 fifo_state
->reserved_size
= bytes
;
304 uint32_t stop
= ioread32(fifo_mem
+ SVGA_FIFO_STOP
);
305 bool need_bounce
= false;
306 bool reserve_in_place
= false;
308 if (next_cmd
>= stop
) {
309 if (likely((next_cmd
+ bytes
< max
||
310 (next_cmd
+ bytes
== max
&& stop
> min
))))
311 reserve_in_place
= true;
313 else if (vmw_fifo_is_full(dev_priv
, bytes
)) {
314 ret
= vmw_fifo_wait(dev_priv
, bytes
,
316 if (unlikely(ret
!= 0))
323 if (likely((next_cmd
+ bytes
< stop
)))
324 reserve_in_place
= true;
326 ret
= vmw_fifo_wait(dev_priv
, bytes
,
328 if (unlikely(ret
!= 0))
333 if (reserve_in_place
) {
334 if (reserveable
|| bytes
<= sizeof(uint32_t)) {
335 fifo_state
->using_bounce_buffer
= false;
338 iowrite32(bytes
, fifo_mem
+
340 return fifo_mem
+ (next_cmd
>> 2);
347 fifo_state
->using_bounce_buffer
= true;
348 if (bytes
< fifo_state
->static_buffer_size
)
349 return fifo_state
->static_buffer
;
351 fifo_state
->dynamic_buffer
= vmalloc(bytes
);
352 return fifo_state
->dynamic_buffer
;
357 fifo_state
->reserved_size
= 0;
358 mutex_unlock(&fifo_state
->fifo_mutex
);
362 static void vmw_fifo_res_copy(struct vmw_fifo_state
*fifo_state
,
363 __le32 __iomem
*fifo_mem
,
365 uint32_t max
, uint32_t min
, uint32_t bytes
)
367 uint32_t chunk_size
= max
- next_cmd
;
369 uint32_t *buffer
= (fifo_state
->dynamic_buffer
!= NULL
) ?
370 fifo_state
->dynamic_buffer
: fifo_state
->static_buffer
;
372 if (bytes
< chunk_size
)
375 iowrite32(bytes
, fifo_mem
+ SVGA_FIFO_RESERVED
);
377 memcpy_toio(fifo_mem
+ (next_cmd
>> 2), buffer
, chunk_size
);
378 rest
= bytes
- chunk_size
;
380 memcpy_toio(fifo_mem
+ (min
>> 2), buffer
+ (chunk_size
>> 2),
384 static void vmw_fifo_slow_copy(struct vmw_fifo_state
*fifo_state
,
385 __le32 __iomem
*fifo_mem
,
387 uint32_t max
, uint32_t min
, uint32_t bytes
)
389 uint32_t *buffer
= (fifo_state
->dynamic_buffer
!= NULL
) ?
390 fifo_state
->dynamic_buffer
: fifo_state
->static_buffer
;
393 iowrite32(*buffer
++, fifo_mem
+ (next_cmd
>> 2));
394 next_cmd
+= sizeof(uint32_t);
395 if (unlikely(next_cmd
== max
))
398 iowrite32(next_cmd
, fifo_mem
+ SVGA_FIFO_NEXT_CMD
);
400 bytes
-= sizeof(uint32_t);
404 void vmw_fifo_commit(struct vmw_private
*dev_priv
, uint32_t bytes
)
406 struct vmw_fifo_state
*fifo_state
= &dev_priv
->fifo
;
407 __le32 __iomem
*fifo_mem
= dev_priv
->mmio_virt
;
408 uint32_t next_cmd
= ioread32(fifo_mem
+ SVGA_FIFO_NEXT_CMD
);
409 uint32_t max
= ioread32(fifo_mem
+ SVGA_FIFO_MAX
);
410 uint32_t min
= ioread32(fifo_mem
+ SVGA_FIFO_MIN
);
411 bool reserveable
= fifo_state
->capabilities
& SVGA_FIFO_CAP_RESERVE
;
413 BUG_ON((bytes
& 3) != 0);
414 BUG_ON(bytes
> fifo_state
->reserved_size
);
416 fifo_state
->reserved_size
= 0;
418 if (fifo_state
->using_bounce_buffer
) {
420 vmw_fifo_res_copy(fifo_state
, fifo_mem
,
421 next_cmd
, max
, min
, bytes
);
423 vmw_fifo_slow_copy(fifo_state
, fifo_mem
,
424 next_cmd
, max
, min
, bytes
);
426 if (fifo_state
->dynamic_buffer
) {
427 vfree(fifo_state
->dynamic_buffer
);
428 fifo_state
->dynamic_buffer
= NULL
;
433 down_write(&fifo_state
->rwsem
);
434 if (fifo_state
->using_bounce_buffer
|| reserveable
) {
437 next_cmd
-= max
- min
;
439 iowrite32(next_cmd
, fifo_mem
+ SVGA_FIFO_NEXT_CMD
);
443 iowrite32(0, fifo_mem
+ SVGA_FIFO_RESERVED
);
445 up_write(&fifo_state
->rwsem
);
446 vmw_fifo_ping_host(dev_priv
, SVGA_SYNC_GENERIC
);
447 mutex_unlock(&fifo_state
->fifo_mutex
);
450 int vmw_fifo_send_fence(struct vmw_private
*dev_priv
, uint32_t *seqno
)
452 struct vmw_fifo_state
*fifo_state
= &dev_priv
->fifo
;
453 struct svga_fifo_cmd_fence
*cmd_fence
;
456 uint32_t bytes
= sizeof(__le32
) + sizeof(*cmd_fence
);
458 fm
= vmw_fifo_reserve(dev_priv
, bytes
);
459 if (unlikely(fm
== NULL
)) {
460 *seqno
= atomic_read(&dev_priv
->marker_seq
);
462 (void)vmw_fallback_wait(dev_priv
, false, true, *seqno
,
468 *seqno
= atomic_add_return(1, &dev_priv
->marker_seq
);
469 } while (*seqno
== 0);
471 if (!(fifo_state
->capabilities
& SVGA_FIFO_CAP_FENCE
)) {
474 * Don't request hardware to send a fence. The
475 * waiting code in vmwgfx_irq.c will emulate this.
478 vmw_fifo_commit(dev_priv
, 0);
482 *(__le32
*) fm
= cpu_to_le32(SVGA_CMD_FENCE
);
483 cmd_fence
= (struct svga_fifo_cmd_fence
*)
484 ((unsigned long)fm
+ sizeof(__le32
));
486 iowrite32(*seqno
, &cmd_fence
->fence
);
487 vmw_fifo_commit(dev_priv
, bytes
);
488 (void) vmw_marker_push(&fifo_state
->marker_queue
, *seqno
);
489 vmw_update_seqno(dev_priv
, fifo_state
);