drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c

   1 /**************************************************************************
   2  *
   3  * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "vmwgfx_drv.h"
  29 #include <drm/drmP.h>
  30 #include <drm/ttm/ttm_placement.h>
  31
  32 bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
  33 {
  34         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  35         uint32_t fifo_min, hwversion;
  36         const struct vmw_fifo_state *fifo = &dev_priv->fifo;
  37
  38         if (!(dev_priv->capabilities & SVGA_CAP_3D))
  39                 return false;
  40
  41         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
  42                 uint32_t result;
  43
  44                 if (!dev_priv->has_mob)
  45                         return false;
  46
  47                 spin_lock(&dev_priv->cap_lock);
  48                 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D);
  49                 result = vmw_read(dev_priv, SVGA_REG_DEV_CAP);
  50                 spin_unlock(&dev_priv->cap_lock);
  51
  52                 return (result != 0);
  53         }
  54
  55         if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
  56                 return false;
  57
  58         fifo_min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
  59         if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
  60                 return false;
  61
  62         hwversion = ioread32(fifo_mem +
  63                              ((fifo->capabilities &
  64                                SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
  65                               SVGA_FIFO_3D_HWVERSION_REVISED :
  66                               SVGA_FIFO_3D_HWVERSION));
  67
  68         if (hwversion == 0)
  69                 return false;
  70
  71         if (hwversion < SVGA3D_HWVERSION_WS8_B1)
  72                 return false;
  73
  74         /* Legacy Display Unit does not support surfaces */
  75         if (dev_priv->active_display_unit == vmw_du_legacy)
  76                 return false;
  77
  78         return true;
  79 }
  80
  81 bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
  82 {
  83         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  84         uint32_t caps;
  85
  86         if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
  87                 return false;
  88
  89         caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
  90         if (caps & SVGA_FIFO_CAP_PITCHLOCK)
  91                 return true;
  92
  93         return false;
  94 }
  95
  96 int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
  97 {
  98         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  99         uint32_t max;
 100         uint32_t min;
 101
 102         fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
 103         fifo->static_buffer = vmalloc(fifo->static_buffer_size);
 104         if (unlikely(fifo->static_buffer == NULL))
 105                 return -ENOMEM;
 106
 107         fifo->dynamic_buffer = NULL;
 108         fifo->reserved_size = 0;
 109         fifo->using_bounce_buffer = false;
 110
 111         mutex_init(&fifo->fifo_mutex);
 112         init_rwsem(&fifo->rwsem);
 113
 114         DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
 115         DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
 116         DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
 117
 118         dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
 119         dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
 120         dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
 121
 122         vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE_HIDE);
 123         vmw_write(dev_priv, SVGA_REG_TRACES, 0);
 124
 125         min = 4;
 126         if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
 127                 min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
 128         min <<= 2;
 129
 130         if (min < PAGE_SIZE)
 131                 min = PAGE_SIZE;
 132
 133         iowrite32(min, fifo_mem + SVGA_FIFO_MIN);
 134         iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
 135         wmb();
 136         iowrite32(min,  fifo_mem + SVGA_FIFO_NEXT_CMD);
 137         iowrite32(min,  fifo_mem + SVGA_FIFO_STOP);
 138         iowrite32(0, fifo_mem + SVGA_FIFO_BUSY);
 139         mb();
 140
 141         vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
 142
 143         max = ioread32(fifo_mem + SVGA_FIFO_MAX);
 144         min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
 145         fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
 146
 147         DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
 148                  (unsigned int) max,
 149                  (unsigned int) min,
 150                  (unsigned int) fifo->capabilities);
 151
 152         atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
 153         iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
 154         vmw_marker_queue_init(&fifo->marker_queue);
 155
 156         return 0;
 157 }
 158
 159 void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
 160 {
 161         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 162         static DEFINE_SPINLOCK(ping_lock);
 163         unsigned long irq_flags;
 164
 165         /*
 166          * The ping_lock is needed because we don't have an atomic
 167          * test-and-set of the SVGA_FIFO_BUSY register.
 168          */
 169         spin_lock_irqsave(&ping_lock, irq_flags);
 170         if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) {
 171                 iowrite32(1, fifo_mem + SVGA_FIFO_BUSY);
 172                 vmw_write(dev_priv, SVGA_REG_SYNC, reason);
 173         }
 174         spin_unlock_irqrestore(&ping_lock, irq_flags);
 175 }
 176
 177 void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
 178 {
 179         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 180
 181         vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
 182         while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
 183                 ;
 184
 185         dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE);
 186
 187         vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
 188                   dev_priv->config_done_state);
 189         vmw_write(dev_priv, SVGA_REG_ENABLE,
 190                   dev_priv->enable_state);
 191         vmw_write(dev_priv, SVGA_REG_TRACES,
 192                   dev_priv->traces_state);
 193
 194         vmw_marker_queue_takedown(&fifo->marker_queue);
 195
 196         if (likely(fifo->static_buffer != NULL)) {
 197                 vfree(fifo->static_buffer);
 198                 fifo->static_buffer = NULL;
 199         }
 200
 201         if (likely(fifo->dynamic_buffer != NULL)) {
 202                 vfree(fifo->dynamic_buffer);
 203                 fifo->dynamic_buffer = NULL;
 204         }
 205 }
 206
 207 static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
 208 {
 209         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 210         uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
 211         uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
 212         uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
 213         uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
 214
 215         return ((max - next_cmd) + (stop - min) <= bytes);
 216 }
 217
 218 static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
 219                                uint32_t bytes, bool interruptible,
 220                                unsigned long timeout)
 221 {
 222         int ret = 0;
 223         unsigned long end_jiffies = jiffies + timeout;
 224         DEFINE_WAIT(__wait);
 225
 226         DRM_INFO("Fifo wait noirq.\n");
 227
 228         for (;;) {
 229                 prepare_to_wait(&dev_priv->fifo_queue, &__wait,
 230                                 (interruptible) ?
 231                                 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
 232                 if (!vmw_fifo_is_full(dev_priv, bytes))
 233                         break;
 234                 if (time_after_eq(jiffies, end_jiffies)) {
 235                         ret = -EBUSY;
 236                         DRM_ERROR("SVGA device lockup.\n");
 237                         break;
 238                 }
 239                 schedule_timeout(1);
 240                 if (interruptible && signal_pending(current)) {
 241                         ret = -ERESTARTSYS;
 242                         break;
 243                 }
 244         }
 245         finish_wait(&dev_priv->fifo_queue, &__wait);
 246         wake_up_all(&dev_priv->fifo_queue);
 247         DRM_INFO("Fifo noirq exit.\n");
 248         return ret;
 249 }
 250
 251 static int vmw_fifo_wait(struct vmw_private *dev_priv,
 252                          uint32_t bytes, bool interruptible,
 253                          unsigned long timeout)
 254 {
 255         long ret = 1L;
 256         unsigned long irq_flags;
 257
 258         if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
 259                 return 0;
 260
 261         vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
 262         if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
 263                 return vmw_fifo_wait_noirq(dev_priv, bytes,
 264                                            interruptible, timeout);
 265
 266         spin_lock(&dev_priv->waiter_lock);
 267         if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) {
 268                 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
 269                 outl(SVGA_IRQFLAG_FIFO_PROGRESS,
 270                      dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
 271                 dev_priv->irq_mask |= SVGA_IRQFLAG_FIFO_PROGRESS;
 272                 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
 273                 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
 274         }
 275         spin_unlock(&dev_priv->waiter_lock);
 276
 277         if (interruptible)
 278                 ret = wait_event_interruptible_timeout
 279                     (dev_priv->fifo_queue,
 280                      !vmw_fifo_is_full(dev_priv, bytes), timeout);
 281         else
 282                 ret = wait_event_timeout
 283                     (dev_priv->fifo_queue,
 284                      !vmw_fifo_is_full(dev_priv, bytes), timeout);
 285
 286         if (unlikely(ret == 0))
 287                 ret = -EBUSY;
 288         else if (likely(ret > 0))
 289                 ret = 0;
 290
 291         spin_lock(&dev_priv->waiter_lock);
 292         if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) {
 293                 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
 294                 dev_priv->irq_mask &= ~SVGA_IRQFLAG_FIFO_PROGRESS;
 295                 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
 296                 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
 297         }
 298         spin_unlock(&dev_priv->waiter_lock);
 299
 300         return ret;
 301 }
 302
 303 /**
 304  * Reserve @bytes number of bytes in the fifo.
 305  *
 306  * This function will return NULL (error) on two conditions:
 307  *  If it timeouts waiting for fifo space, or if @bytes is larger than the
 308  *   available fifo space.
 309  *
 310  * Returns:
 311  *   Pointer to the fifo, or null on error (possible hardware hang).
 312  */
 313 static void *vmw_local_fifo_reserve(struct vmw_private *dev_priv,
 314                                     uint32_t bytes)
 315 {
 316         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
 317         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 318         uint32_t max;
 319         uint32_t min;
 320         uint32_t next_cmd;
 321         uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
 322         int ret;
 323
 324         mutex_lock(&fifo_state->fifo_mutex);
 325         max = ioread32(fifo_mem + SVGA_FIFO_MAX);
 326         min = ioread32(fifo_mem + SVGA_FIFO_MIN);
 327         next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
 328
 329         if (unlikely(bytes >= (max - min)))
 330                 goto out_err;
 331
 332         BUG_ON(fifo_state->reserved_size != 0);
 333         BUG_ON(fifo_state->dynamic_buffer != NULL);
 334
 335         fifo_state->reserved_size = bytes;
 336
 337         while (1) {
 338                 uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
 339                 bool need_bounce = false;
 340                 bool reserve_in_place = false;
 341
 342                 if (next_cmd >= stop) {
 343                         if (likely((next_cmd + bytes < max ||
 344                                     (next_cmd + bytes == max && stop > min))))
 345                                 reserve_in_place = true;
 346
 347                         else if (vmw_fifo_is_full(dev_priv, bytes)) {
 348                                 ret = vmw_fifo_wait(dev_priv, bytes,
 349                                                     false, 3 * HZ);
 350                                 if (unlikely(ret != 0))
 351                                         goto out_err;
 352                         } else
 353                                 need_bounce = true;
 354
 355                 } else {
 356
 357                         if (likely((next_cmd + bytes < stop)))
 358                                 reserve_in_place = true;
 359                         else {
 360                                 ret = vmw_fifo_wait(dev_priv, bytes,
 361                                                     false, 3 * HZ);
 362                                 if (unlikely(ret != 0))
 363                                         goto out_err;
 364                         }
 365                 }
 366
 367                 if (reserve_in_place) {
 368                         if (reserveable || bytes <= sizeof(uint32_t)) {
 369                                 fifo_state->using_bounce_buffer = false;
 370
 371                                 if (reserveable)
 372                                         iowrite32(bytes, fifo_mem +
 373                                                   SVGA_FIFO_RESERVED);
 374                                 return fifo_mem + (next_cmd >> 2);
 375                         } else {
 376                                 need_bounce = true;
 377                         }
 378                 }
 379
 380                 if (need_bounce) {
 381                         fifo_state->using_bounce_buffer = true;
 382                         if (bytes < fifo_state->static_buffer_size)
 383                                 return fifo_state->static_buffer;
 384                         else {
 385                                 fifo_state->dynamic_buffer = vmalloc(bytes);
 386                                 return fifo_state->dynamic_buffer;
 387                         }
 388                 }
 389         }
 390 out_err:
 391         fifo_state->reserved_size = 0;
 392         mutex_unlock(&fifo_state->fifo_mutex);
 393
 394         return NULL;
 395 }
 396
 397 void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes)
 398 {
 399         void *ret;
 400
 401         if (dev_priv->cman)
 402                 ret = vmw_cmdbuf_reserve(dev_priv->cman, bytes,
 403                                          SVGA3D_INVALID_ID, false, NULL);
 404         else
 405                 ret = vmw_local_fifo_reserve(dev_priv, bytes);
 406         if (IS_ERR_OR_NULL(ret)) {
 407                 DRM_ERROR("Fifo reserve failure of %u bytes.\n",
 408                           (unsigned) bytes);
 409                 dump_stack();
 410                 return NULL;
 411         }
 412
 413         return ret;
 414 }
 415
 416 static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
 417                               __le32 __iomem *fifo_mem,
 418                               uint32_t next_cmd,
 419                               uint32_t max, uint32_t min, uint32_t bytes)
 420 {
 421         uint32_t chunk_size = max - next_cmd;
 422         uint32_t rest;
 423         uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
 424             fifo_state->dynamic_buffer : fifo_state->static_buffer;
 425
 426         if (bytes < chunk_size)
 427                 chunk_size = bytes;
 428
 429         iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED);
 430         mb();
 431         memcpy_toio(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
 432         rest = bytes - chunk_size;
 433         if (rest)
 434                 memcpy_toio(fifo_mem + (min >> 2), buffer + (chunk_size >> 2),
 435                             rest);
 436 }
 437
 438 static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
 439                                __le32 __iomem *fifo_mem,
 440                                uint32_t next_cmd,
 441                                uint32_t max, uint32_t min, uint32_t bytes)
 442 {
 443         uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
 444             fifo_state->dynamic_buffer : fifo_state->static_buffer;
 445
 446         while (bytes > 0) {
 447                 iowrite32(*buffer++, fifo_mem + (next_cmd >> 2));
 448                 next_cmd += sizeof(uint32_t);
 449                 if (unlikely(next_cmd == max))
 450                         next_cmd = min;
 451                 mb();
 452                 iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
 453                 mb();
 454                 bytes -= sizeof(uint32_t);
 455         }
 456 }
 457
 458 void vmw_local_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
 459 {
 460         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
 461         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 462         uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
 463         uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
 464         uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
 465         bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
 466
 467         BUG_ON((bytes & 3) != 0);
 468         BUG_ON(bytes > fifo_state->reserved_size);
 469
 470         fifo_state->reserved_size = 0;
 471
 472         if (fifo_state->using_bounce_buffer) {
 473                 if (reserveable)
 474                         vmw_fifo_res_copy(fifo_state, fifo_mem,
 475                                           next_cmd, max, min, bytes);
 476                 else
 477                         vmw_fifo_slow_copy(fifo_state, fifo_mem,
 478                                            next_cmd, max, min, bytes);
 479
 480                 if (fifo_state->dynamic_buffer) {
 481                         vfree(fifo_state->dynamic_buffer);
 482                         fifo_state->dynamic_buffer = NULL;
 483                 }
 484
 485         }
 486
 487         down_write(&fifo_state->rwsem);
 488         if (fifo_state->using_bounce_buffer || reserveable) {
 489                 next_cmd += bytes;
 490                 if (next_cmd >= max)
 491                         next_cmd -= max - min;
 492                 mb();
 493                 iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
 494         }
 495
 496         if (reserveable)
 497                 iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED);
 498         mb();
 499         up_write(&fifo_state->rwsem);
 500         vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
 501         mutex_unlock(&fifo_state->fifo_mutex);
 502 }
 503
 504 void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
 505 {
 506         if (dev_priv->cman)
 507                 vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, false);
 508         else
 509                 vmw_local_fifo_commit(dev_priv, bytes);
 510 }
 511
 512
 513 /**
 514  * vmw_fifo_commit_flush - Commit fifo space and flush any buffered commands.
 515  *
 516  * @dev_priv: Pointer to device private structure.
 517  * @bytes: Number of bytes to commit.
 518  */
 519 static void vmw_fifo_commit_flush(struct vmw_private *dev_priv, uint32_t bytes)
 520 {
 521         if (dev_priv->cman)
 522                 vmw_cmdbuf_commit(dev_priv->cman, bytes, NULL, true);
 523         else
 524                 vmw_local_fifo_commit(dev_priv, bytes);
 525 }
 526
 527 /**
 528  * vmw_fifo_flush - Flush any buffered commands and make sure command processing
 529  * starts.
 530  *
 531  * @dev_priv: Pointer to device private structure.
 532  * @interruptible: Whether to wait interruptible if function needs to sleep.
 533  */
 534 int vmw_fifo_flush(struct vmw_private *dev_priv, bool interruptible)
 535 {
 536         might_sleep();
 537
 538         if (dev_priv->cman)
 539                 return vmw_cmdbuf_cur_flush(dev_priv->cman, interruptible);
 540         else
 541                 return 0;
 542 }
 543
 544 int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno)
 545 {
 546         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
 547         struct svga_fifo_cmd_fence *cmd_fence;
 548         void *fm;
 549         int ret = 0;
 550         uint32_t bytes = sizeof(__le32) + sizeof(*cmd_fence);
 551
 552         fm = vmw_fifo_reserve(dev_priv, bytes);
 553         if (unlikely(fm == NULL)) {
 554                 *seqno = atomic_read(&dev_priv->marker_seq);
 555                 ret = -ENOMEM;
 556                 (void)vmw_fallback_wait(dev_priv, false, true, *seqno,
 557                                         false, 3*HZ);
 558                 goto out_err;
 559         }
 560
 561         do {
 562                 *seqno = atomic_add_return(1, &dev_priv->marker_seq);
 563         } while (*seqno == 0);
 564
 565         if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {
 566
 567                 /*
 568                  * Don't request hardware to send a fence. The
 569                  * waiting code in vmwgfx_irq.c will emulate this.
 570                  */
 571
 572                 vmw_fifo_commit(dev_priv, 0);
 573                 return 0;
 574         }
 575
 576         *(__le32 *) fm = cpu_to_le32(SVGA_CMD_FENCE);
 577         cmd_fence = (struct svga_fifo_cmd_fence *)
 578             ((unsigned long)fm + sizeof(__le32));
 579
 580         iowrite32(*seqno, &cmd_fence->fence);
 581         vmw_fifo_commit_flush(dev_priv, bytes);
 582         (void) vmw_marker_push(&fifo_state->marker_queue, *seqno);
 583         vmw_update_seqno(dev_priv, fifo_state);
 584
 585 out_err:
 586         return ret;
 587 }
 588
 589 /**
 590  * vmw_fifo_emit_dummy_legacy_query - emits a dummy query to the fifo using
 591  * legacy query commands.
 592  *
 593  * @dev_priv: The device private structure.
 594  * @cid: The hardware context id used for the query.
 595  *
 596  * See the vmw_fifo_emit_dummy_query documentation.
 597  */
 598 static int vmw_fifo_emit_dummy_legacy_query(struct vmw_private *dev_priv,
 599                                             uint32_t cid)
 600 {
 601         /*
 602          * A query wait without a preceding query end will
 603          * actually finish all queries for this cid
 604          * without writing to the query result structure.
 605          */
 606
 607         struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base;
 608         struct {
 609                 SVGA3dCmdHeader header;
 610                 SVGA3dCmdWaitForQuery body;
 611         } *cmd;
 612
 613         cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
 614
 615         if (unlikely(cmd == NULL)) {
 616                 DRM_ERROR("Out of fifo space for dummy query.\n");
 617                 return -ENOMEM;
 618         }
 619
 620         cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY;
 621         cmd->header.size = sizeof(cmd->body);
 622         cmd->body.cid = cid;
 623         cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
 624
 625         if (bo->mem.mem_type == TTM_PL_VRAM) {
 626                 cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER;
 627                 cmd->body.guestResult.offset = bo->offset;
 628         } else {
 629                 cmd->body.guestResult.gmrId = bo->mem.start;
 630                 cmd->body.guestResult.offset = 0;
 631         }
 632
 633         vmw_fifo_commit(dev_priv, sizeof(*cmd));
 634
 635         return 0;
 636 }
 637
 638 /**
 639  * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
 640  * guest-backed resource query commands.
 641  *
 642  * @dev_priv: The device private structure.
 643  * @cid: The hardware context id used for the query.
 644  *
 645  * See the vmw_fifo_emit_dummy_query documentation.
 646  */
 647 static int vmw_fifo_emit_dummy_gb_query(struct vmw_private *dev_priv,
 648                                         uint32_t cid)
 649 {
 650         /*
 651          * A query wait without a preceding query end will
 652          * actually finish all queries for this cid
 653          * without writing to the query result structure.
 654          */
 655
 656         struct ttm_buffer_object *bo = &dev_priv->dummy_query_bo->base;
 657         struct {
 658                 SVGA3dCmdHeader header;
 659                 SVGA3dCmdWaitForGBQuery body;
 660         } *cmd;
 661
 662         cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
 663
 664         if (unlikely(cmd == NULL)) {
 665                 DRM_ERROR("Out of fifo space for dummy query.\n");
 666                 return -ENOMEM;
 667         }
 668
 669         cmd->header.id = SVGA_3D_CMD_WAIT_FOR_GB_QUERY;
 670         cmd->header.size = sizeof(cmd->body);
 671         cmd->body.cid = cid;
 672         cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
 673         BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
 674         cmd->body.mobid = bo->mem.start;
 675         cmd->body.offset = 0;
 676
 677         vmw_fifo_commit(dev_priv, sizeof(*cmd));
 678
 679         return 0;
 680 }
 681
 682
 683 /**
 684  * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
 685  * appropriate resource query commands.
 686  *
 687  * @dev_priv: The device private structure.
 688  * @cid: The hardware context id used for the query.
 689  *
 690  * This function is used to emit a dummy occlusion query with
 691  * no primitives rendered between query begin and query end.
 692  * It's used to provide a query barrier, in order to know that when
 693  * this query is finished, all preceding queries are also finished.
 694  *
 695  * A Query results structure should have been initialized at the start
 696  * of the dev_priv->dummy_query_bo buffer object. And that buffer object
 697  * must also be either reserved or pinned when this function is called.
 698  *
 699  * Returns -ENOMEM on failure to reserve fifo space.
 700  */
 701 int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,
 702                               uint32_t cid)
 703 {
 704         if (dev_priv->has_mob)
 705                 return vmw_fifo_emit_dummy_gb_query(dev_priv, cid);
 706
 707         return vmw_fifo_emit_dummy_legacy_query(dev_priv, cid);
 708 }