1 /**************************************************************************
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "vmwgfx_drv.h"
30 #include "ttm/ttm_placement.h"
32 bool vmw_fifo_have_3d(struct vmw_private
*dev_priv
)
34 __le32 __iomem
*fifo_mem
= dev_priv
->mmio_virt
;
35 uint32_t fifo_min
, hwversion
;
37 if (!(dev_priv
->capabilities
& SVGA_CAP_EXTENDED_FIFO
))
40 fifo_min
= ioread32(fifo_mem
+ SVGA_FIFO_MIN
);
41 if (fifo_min
<= SVGA_FIFO_3D_HWVERSION
* sizeof(unsigned int))
44 hwversion
= ioread32(fifo_mem
+ SVGA_FIFO_3D_HWVERSION
);
48 if (hwversion
< SVGA3D_HWVERSION_WS65_B1
)
54 bool vmw_fifo_have_pitchlock(struct vmw_private
*dev_priv
)
56 __le32 __iomem
*fifo_mem
= dev_priv
->mmio_virt
;
59 if (!(dev_priv
->capabilities
& SVGA_CAP_EXTENDED_FIFO
))
62 caps
= ioread32(fifo_mem
+ SVGA_FIFO_CAPABILITIES
);
63 if (caps
& SVGA_FIFO_CAP_PITCHLOCK
)
69 int vmw_fifo_init(struct vmw_private
*dev_priv
, struct vmw_fifo_state
*fifo
)
71 __le32 __iomem
*fifo_mem
= dev_priv
->mmio_virt
;
77 fifo
->static_buffer_size
= VMWGFX_FIFO_STATIC_SIZE
;
78 fifo
->static_buffer
= vmalloc(fifo
->static_buffer_size
);
79 if (unlikely(fifo
->static_buffer
== NULL
))
82 fifo
->last_buffer_size
= VMWGFX_FIFO_STATIC_SIZE
;
83 fifo
->last_data_size
= 0;
84 fifo
->last_buffer_add
= false;
85 fifo
->last_buffer
= vmalloc(fifo
->last_buffer_size
);
86 if (unlikely(fifo
->last_buffer
== NULL
)) {
91 fifo
->dynamic_buffer
= NULL
;
92 fifo
->reserved_size
= 0;
93 fifo
->using_bounce_buffer
= false;
95 mutex_init(&fifo
->fifo_mutex
);
96 init_rwsem(&fifo
->rwsem
);
99 * Allow mapping the first page read-only to user-space.
102 DRM_INFO("width %d\n", vmw_read(dev_priv
, SVGA_REG_WIDTH
));
103 DRM_INFO("height %d\n", vmw_read(dev_priv
, SVGA_REG_HEIGHT
));
104 DRM_INFO("bpp %d\n", vmw_read(dev_priv
, SVGA_REG_BITS_PER_PIXEL
));
106 mutex_lock(&dev_priv
->hw_mutex
);
107 dev_priv
->enable_state
= vmw_read(dev_priv
, SVGA_REG_ENABLE
);
108 dev_priv
->config_done_state
= vmw_read(dev_priv
, SVGA_REG_CONFIG_DONE
);
109 vmw_write(dev_priv
, SVGA_REG_ENABLE
, 1);
112 if (dev_priv
->capabilities
& SVGA_CAP_EXTENDED_FIFO
)
113 min
= vmw_read(dev_priv
, SVGA_REG_MEM_REGS
);
119 iowrite32(min
, fifo_mem
+ SVGA_FIFO_MIN
);
120 iowrite32(dev_priv
->mmio_size
, fifo_mem
+ SVGA_FIFO_MAX
);
122 iowrite32(min
, fifo_mem
+ SVGA_FIFO_NEXT_CMD
);
123 iowrite32(min
, fifo_mem
+ SVGA_FIFO_STOP
);
124 iowrite32(0, fifo_mem
+ SVGA_FIFO_BUSY
);
127 vmw_write(dev_priv
, SVGA_REG_CONFIG_DONE
, 1);
128 mutex_unlock(&dev_priv
->hw_mutex
);
130 max
= ioread32(fifo_mem
+ SVGA_FIFO_MAX
);
131 min
= ioread32(fifo_mem
+ SVGA_FIFO_MIN
);
132 fifo
->capabilities
= ioread32(fifo_mem
+ SVGA_FIFO_CAPABILITIES
);
134 DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
137 (unsigned int) fifo
->capabilities
);
139 atomic_set(&dev_priv
->fence_seq
, dev_priv
->last_read_sequence
);
140 iowrite32(dev_priv
->last_read_sequence
, fifo_mem
+ SVGA_FIFO_FENCE
);
141 vmw_fence_queue_init(&fifo
->fence_queue
);
142 return vmw_fifo_send_fence(dev_priv
, &dummy
);
144 vfree(fifo
->static_buffer
);
145 fifo
->static_buffer
= NULL
;
149 void vmw_fifo_ping_host(struct vmw_private
*dev_priv
, uint32_t reason
)
151 __le32 __iomem
*fifo_mem
= dev_priv
->mmio_virt
;
153 mutex_lock(&dev_priv
->hw_mutex
);
155 if (unlikely(ioread32(fifo_mem
+ SVGA_FIFO_BUSY
) == 0)) {
156 iowrite32(1, fifo_mem
+ SVGA_FIFO_BUSY
);
157 vmw_write(dev_priv
, SVGA_REG_SYNC
, reason
);
160 mutex_unlock(&dev_priv
->hw_mutex
);
163 void vmw_fifo_release(struct vmw_private
*dev_priv
, struct vmw_fifo_state
*fifo
)
165 __le32 __iomem
*fifo_mem
= dev_priv
->mmio_virt
;
167 mutex_lock(&dev_priv
->hw_mutex
);
169 while (vmw_read(dev_priv
, SVGA_REG_BUSY
) != 0)
170 vmw_write(dev_priv
, SVGA_REG_SYNC
, SVGA_SYNC_GENERIC
);
172 dev_priv
->last_read_sequence
= ioread32(fifo_mem
+ SVGA_FIFO_FENCE
);
174 vmw_write(dev_priv
, SVGA_REG_CONFIG_DONE
,
175 dev_priv
->config_done_state
);
176 vmw_write(dev_priv
, SVGA_REG_ENABLE
,
177 dev_priv
->enable_state
);
179 mutex_unlock(&dev_priv
->hw_mutex
);
180 vmw_fence_queue_takedown(&fifo
->fence_queue
);
182 if (likely(fifo
->last_buffer
!= NULL
)) {
183 vfree(fifo
->last_buffer
);
184 fifo
->last_buffer
= NULL
;
187 if (likely(fifo
->static_buffer
!= NULL
)) {
188 vfree(fifo
->static_buffer
);
189 fifo
->static_buffer
= NULL
;
192 if (likely(fifo
->dynamic_buffer
!= NULL
)) {
193 vfree(fifo
->dynamic_buffer
);
194 fifo
->dynamic_buffer
= NULL
;
198 static bool vmw_fifo_is_full(struct vmw_private
*dev_priv
, uint32_t bytes
)
200 __le32 __iomem
*fifo_mem
= dev_priv
->mmio_virt
;
201 uint32_t max
= ioread32(fifo_mem
+ SVGA_FIFO_MAX
);
202 uint32_t next_cmd
= ioread32(fifo_mem
+ SVGA_FIFO_NEXT_CMD
);
203 uint32_t min
= ioread32(fifo_mem
+ SVGA_FIFO_MIN
);
204 uint32_t stop
= ioread32(fifo_mem
+ SVGA_FIFO_STOP
);
206 return ((max
- next_cmd
) + (stop
- min
) <= bytes
);
209 static int vmw_fifo_wait_noirq(struct vmw_private
*dev_priv
,
210 uint32_t bytes
, bool interruptible
,
211 unsigned long timeout
)
214 unsigned long end_jiffies
= jiffies
+ timeout
;
217 DRM_INFO("Fifo wait noirq.\n");
220 prepare_to_wait(&dev_priv
->fifo_queue
, &__wait
,
222 TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
223 if (!vmw_fifo_is_full(dev_priv
, bytes
))
225 if (time_after_eq(jiffies
, end_jiffies
)) {
227 DRM_ERROR("SVGA device lockup.\n");
231 if (interruptible
&& signal_pending(current
)) {
236 finish_wait(&dev_priv
->fifo_queue
, &__wait
);
237 wake_up_all(&dev_priv
->fifo_queue
);
238 DRM_INFO("Fifo noirq exit.\n");
242 static int vmw_fifo_wait(struct vmw_private
*dev_priv
,
243 uint32_t bytes
, bool interruptible
,
244 unsigned long timeout
)
247 unsigned long irq_flags
;
249 if (likely(!vmw_fifo_is_full(dev_priv
, bytes
)))
252 vmw_fifo_ping_host(dev_priv
, SVGA_SYNC_FIFOFULL
);
253 if (!(dev_priv
->capabilities
& SVGA_CAP_IRQMASK
))
254 return vmw_fifo_wait_noirq(dev_priv
, bytes
,
255 interruptible
, timeout
);
257 mutex_lock(&dev_priv
->hw_mutex
);
258 if (atomic_add_return(1, &dev_priv
->fifo_queue_waiters
) > 0) {
259 spin_lock_irqsave(&dev_priv
->irq_lock
, irq_flags
);
260 outl(SVGA_IRQFLAG_FIFO_PROGRESS
,
261 dev_priv
->io_start
+ VMWGFX_IRQSTATUS_PORT
);
262 vmw_write(dev_priv
, SVGA_REG_IRQMASK
,
263 vmw_read(dev_priv
, SVGA_REG_IRQMASK
) |
264 SVGA_IRQFLAG_FIFO_PROGRESS
);
265 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irq_flags
);
267 mutex_unlock(&dev_priv
->hw_mutex
);
270 ret
= wait_event_interruptible_timeout
271 (dev_priv
->fifo_queue
,
272 !vmw_fifo_is_full(dev_priv
, bytes
), timeout
);
274 ret
= wait_event_timeout
275 (dev_priv
->fifo_queue
,
276 !vmw_fifo_is_full(dev_priv
, bytes
), timeout
);
278 if (unlikely(ret
== 0))
280 else if (likely(ret
> 0))
283 mutex_lock(&dev_priv
->hw_mutex
);
284 if (atomic_dec_and_test(&dev_priv
->fifo_queue_waiters
)) {
285 spin_lock_irqsave(&dev_priv
->irq_lock
, irq_flags
);
286 vmw_write(dev_priv
, SVGA_REG_IRQMASK
,
287 vmw_read(dev_priv
, SVGA_REG_IRQMASK
) &
288 ~SVGA_IRQFLAG_FIFO_PROGRESS
);
289 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irq_flags
);
291 mutex_unlock(&dev_priv
->hw_mutex
);
296 void *vmw_fifo_reserve(struct vmw_private
*dev_priv
, uint32_t bytes
)
298 struct vmw_fifo_state
*fifo_state
= &dev_priv
->fifo
;
299 __le32 __iomem
*fifo_mem
= dev_priv
->mmio_virt
;
303 uint32_t reserveable
= fifo_state
->capabilities
& SVGA_FIFO_CAP_RESERVE
;
306 mutex_lock(&fifo_state
->fifo_mutex
);
307 max
= ioread32(fifo_mem
+ SVGA_FIFO_MAX
);
308 min
= ioread32(fifo_mem
+ SVGA_FIFO_MIN
);
309 next_cmd
= ioread32(fifo_mem
+ SVGA_FIFO_NEXT_CMD
);
311 if (unlikely(bytes
>= (max
- min
)))
314 BUG_ON(fifo_state
->reserved_size
!= 0);
315 BUG_ON(fifo_state
->dynamic_buffer
!= NULL
);
317 fifo_state
->reserved_size
= bytes
;
320 uint32_t stop
= ioread32(fifo_mem
+ SVGA_FIFO_STOP
);
321 bool need_bounce
= false;
322 bool reserve_in_place
= false;
324 if (next_cmd
>= stop
) {
325 if (likely((next_cmd
+ bytes
< max
||
326 (next_cmd
+ bytes
== max
&& stop
> min
))))
327 reserve_in_place
= true;
329 else if (vmw_fifo_is_full(dev_priv
, bytes
)) {
330 ret
= vmw_fifo_wait(dev_priv
, bytes
,
332 if (unlikely(ret
!= 0))
339 if (likely((next_cmd
+ bytes
< stop
)))
340 reserve_in_place
= true;
342 ret
= vmw_fifo_wait(dev_priv
, bytes
,
344 if (unlikely(ret
!= 0))
349 if (reserve_in_place
) {
350 if (reserveable
|| bytes
<= sizeof(uint32_t)) {
351 fifo_state
->using_bounce_buffer
= false;
354 iowrite32(bytes
, fifo_mem
+
356 return fifo_mem
+ (next_cmd
>> 2);
363 fifo_state
->using_bounce_buffer
= true;
364 if (bytes
< fifo_state
->static_buffer_size
)
365 return fifo_state
->static_buffer
;
367 fifo_state
->dynamic_buffer
= vmalloc(bytes
);
368 return fifo_state
->dynamic_buffer
;
373 fifo_state
->reserved_size
= 0;
374 mutex_unlock(&fifo_state
->fifo_mutex
);
378 static void vmw_fifo_res_copy(struct vmw_fifo_state
*fifo_state
,
379 __le32 __iomem
*fifo_mem
,
381 uint32_t max
, uint32_t min
, uint32_t bytes
)
383 uint32_t chunk_size
= max
- next_cmd
;
385 uint32_t *buffer
= (fifo_state
->dynamic_buffer
!= NULL
) ?
386 fifo_state
->dynamic_buffer
: fifo_state
->static_buffer
;
388 if (bytes
< chunk_size
)
391 iowrite32(bytes
, fifo_mem
+ SVGA_FIFO_RESERVED
);
393 memcpy_toio(fifo_mem
+ (next_cmd
>> 2), buffer
, chunk_size
);
394 rest
= bytes
- chunk_size
;
396 memcpy_toio(fifo_mem
+ (min
>> 2), buffer
+ (chunk_size
>> 2),
400 static void vmw_fifo_slow_copy(struct vmw_fifo_state
*fifo_state
,
401 __le32 __iomem
*fifo_mem
,
403 uint32_t max
, uint32_t min
, uint32_t bytes
)
405 uint32_t *buffer
= (fifo_state
->dynamic_buffer
!= NULL
) ?
406 fifo_state
->dynamic_buffer
: fifo_state
->static_buffer
;
409 iowrite32(*buffer
++, fifo_mem
+ (next_cmd
>> 2));
410 next_cmd
+= sizeof(uint32_t);
411 if (unlikely(next_cmd
== max
))
414 iowrite32(next_cmd
, fifo_mem
+ SVGA_FIFO_NEXT_CMD
);
416 bytes
-= sizeof(uint32_t);
420 void vmw_fifo_commit(struct vmw_private
*dev_priv
, uint32_t bytes
)
422 struct vmw_fifo_state
*fifo_state
= &dev_priv
->fifo
;
423 __le32 __iomem
*fifo_mem
= dev_priv
->mmio_virt
;
424 uint32_t next_cmd
= ioread32(fifo_mem
+ SVGA_FIFO_NEXT_CMD
);
425 uint32_t max
= ioread32(fifo_mem
+ SVGA_FIFO_MAX
);
426 uint32_t min
= ioread32(fifo_mem
+ SVGA_FIFO_MIN
);
427 bool reserveable
= fifo_state
->capabilities
& SVGA_FIFO_CAP_RESERVE
;
429 BUG_ON((bytes
& 3) != 0);
430 BUG_ON(bytes
> fifo_state
->reserved_size
);
432 fifo_state
->reserved_size
= 0;
434 if (fifo_state
->using_bounce_buffer
) {
436 vmw_fifo_res_copy(fifo_state
, fifo_mem
,
437 next_cmd
, max
, min
, bytes
);
439 vmw_fifo_slow_copy(fifo_state
, fifo_mem
,
440 next_cmd
, max
, min
, bytes
);
442 if (fifo_state
->dynamic_buffer
) {
443 vfree(fifo_state
->dynamic_buffer
);
444 fifo_state
->dynamic_buffer
= NULL
;
449 down_write(&fifo_state
->rwsem
);
450 if (fifo_state
->using_bounce_buffer
|| reserveable
) {
453 next_cmd
-= max
- min
;
455 iowrite32(next_cmd
, fifo_mem
+ SVGA_FIFO_NEXT_CMD
);
459 iowrite32(0, fifo_mem
+ SVGA_FIFO_RESERVED
);
461 up_write(&fifo_state
->rwsem
);
462 vmw_fifo_ping_host(dev_priv
, SVGA_SYNC_GENERIC
);
463 mutex_unlock(&fifo_state
->fifo_mutex
);
466 int vmw_fifo_send_fence(struct vmw_private
*dev_priv
, uint32_t *sequence
)
468 struct vmw_fifo_state
*fifo_state
= &dev_priv
->fifo
;
469 struct svga_fifo_cmd_fence
*cmd_fence
;
472 uint32_t bytes
= sizeof(__le32
) + sizeof(*cmd_fence
);
474 fm
= vmw_fifo_reserve(dev_priv
, bytes
);
475 if (unlikely(fm
== NULL
)) {
476 *sequence
= atomic_read(&dev_priv
->fence_seq
);
478 (void)vmw_fallback_wait(dev_priv
, false, true, *sequence
,
484 *sequence
= atomic_add_return(1, &dev_priv
->fence_seq
);
485 } while (*sequence
== 0);
487 if (!(fifo_state
->capabilities
& SVGA_FIFO_CAP_FENCE
)) {
490 * Don't request hardware to send a fence. The
491 * waiting code in vmwgfx_irq.c will emulate this.
494 vmw_fifo_commit(dev_priv
, 0);
498 *(__le32
*) fm
= cpu_to_le32(SVGA_CMD_FENCE
);
499 cmd_fence
= (struct svga_fifo_cmd_fence
*)
500 ((unsigned long)fm
+ sizeof(__le32
));
502 iowrite32(*sequence
, &cmd_fence
->fence
);
503 fifo_state
->last_buffer_add
= true;
504 vmw_fifo_commit(dev_priv
, bytes
);
505 fifo_state
->last_buffer_add
= false;
506 (void) vmw_fence_push(&fifo_state
->fence_queue
, *sequence
);
507 vmw_update_sequence(dev_priv
, fifo_state
);
514 * Map the first page of the FIFO read-only to user-space.
517 static int vmw_fifo_vm_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
520 unsigned long address
= (unsigned long)vmf
->virtual_address
;
522 if (address
!= vma
->vm_start
)
523 return VM_FAULT_SIGBUS
;
525 ret
= vm_insert_pfn(vma
, address
, vma
->vm_pgoff
);
526 if (likely(ret
== -EBUSY
|| ret
== 0))
527 return VM_FAULT_NOPAGE
;
528 else if (ret
== -ENOMEM
)
531 return VM_FAULT_SIGBUS
;
534 static struct vm_operations_struct vmw_fifo_vm_ops
= {
535 .fault
= vmw_fifo_vm_fault
,
540 int vmw_fifo_mmap(struct file
*filp
, struct vm_area_struct
*vma
)
542 struct drm_file
*file_priv
;
543 struct vmw_private
*dev_priv
;
545 file_priv
= filp
->private_data
;
546 dev_priv
= vmw_priv(file_priv
->minor
->dev
);
548 if (vma
->vm_pgoff
!= (dev_priv
->mmio_start
>> PAGE_SHIFT
) ||
549 (vma
->vm_end
- vma
->vm_start
) != PAGE_SIZE
)
552 vma
->vm_flags
&= ~(VM_WRITE
| VM_MAYWRITE
);
553 vma
->vm_flags
|= VM_IO
| VM_PFNMAP
| VM_DONTEXPAND
| VM_SHARED
;
554 vma
->vm_page_prot
= vm_get_page_prot(vma
->vm_flags
);
555 vma
->vm_page_prot
= ttm_io_prot(TTM_PL_FLAG_UNCACHED
,
557 vma
->vm_ops
= &vmw_fifo_vm_ops
;