drivers/hwmon/coretemp.c

   1 /*
   2  * coretemp.c - Linux kernel module for hardware monitoring
   3  *
   4  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   5  *
   6  * Inspired from many hwmon drivers
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20  * 02110-1301 USA.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/slab.h>
  27 #include <linux/jiffies.h>
  28 #include <linux/hwmon.h>
  29 #include <linux/sysfs.h>
  30 #include <linux/hwmon-sysfs.h>
  31 #include <linux/err.h>
  32 #include <linux/mutex.h>
  33 #include <linux/list.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/cpu.h>
  36 #include <linux/pci.h>
  37 #include <asm/msr.h>
  38 #include <asm/processor.h>
  39
  40 #define DRVNAME "coretemp"
  41
  42 typedef enum { SHOW_TEMP, SHOW_TJMAX, SHOW_TTARGET, SHOW_LABEL,
  43                 SHOW_NAME } SHOW;
  44
  45 /*
  46  * Functions declaration
  47  */
  48
  49 static struct coretemp_data *coretemp_update_device(struct device *dev);
  50
  51 struct coretemp_data {
  52         struct device *hwmon_dev;
  53         struct mutex update_lock;
  54         const char *name;
  55         u32 id;
  56         char valid;             /* zero until following fields are valid */
  57         unsigned long last_updated;     /* in jiffies */
  58         int temp;
  59         int tjmax;
  60         int ttarget;
  61         u8 alarm;
  62 };
  63
  64 /*
  65  * Sysfs stuff
  66  */
  67
  68 static ssize_t show_name(struct device *dev, struct device_attribute
  69                           *devattr, char *buf)
  70 {
  71         int ret;
  72         struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  73         struct coretemp_data *data = dev_get_drvdata(dev);
  74
  75         if (attr->index == SHOW_NAME)
  76                 ret = sprintf(buf, "%s\n", data->name);
  77         else    /* show label */
  78                 ret = sprintf(buf, "Core %d\n", data->id);
  79         return ret;
  80 }
  81
  82 static ssize_t show_alarm(struct device *dev, struct device_attribute
  83                           *devattr, char *buf)
  84 {
  85         struct coretemp_data *data = coretemp_update_device(dev);
  86         /* read the Out-of-spec log, never clear */
  87         return sprintf(buf, "%d\n", data->alarm);
  88 }
  89
  90 static ssize_t show_temp(struct device *dev,
  91                          struct device_attribute *devattr, char *buf)
  92 {
  93         struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  94         struct coretemp_data *data = coretemp_update_device(dev);
  95         int err;
  96
  97         if (attr->index == SHOW_TEMP)
  98                 err = data->valid ? sprintf(buf, "%d\n", data->temp) : -EAGAIN;
  99         else if (attr->index == SHOW_TJMAX)
 100                 err = sprintf(buf, "%d\n", data->tjmax);
 101         else
 102                 err = sprintf(buf, "%d\n", data->ttarget);
 103         return err;
 104 }
 105
 106 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL,
 107                           SHOW_TEMP);
 108 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp, NULL,
 109                           SHOW_TJMAX);
 110 static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, show_temp, NULL,
 111                           SHOW_TTARGET);
 112 static DEVICE_ATTR(temp1_crit_alarm, S_IRUGO, show_alarm, NULL);
 113 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, show_name, NULL, SHOW_LABEL);
 114 static SENSOR_DEVICE_ATTR(name, S_IRUGO, show_name, NULL, SHOW_NAME);
 115
 116 static struct attribute *coretemp_attributes[] = {
 117         &sensor_dev_attr_name.dev_attr.attr,
 118         &sensor_dev_attr_temp1_label.dev_attr.attr,
 119         &dev_attr_temp1_crit_alarm.attr,
 120         &sensor_dev_attr_temp1_input.dev_attr.attr,
 121         &sensor_dev_attr_temp1_crit.dev_attr.attr,
 122         NULL
 123 };
 124
 125 static const struct attribute_group coretemp_group = {
 126         .attrs = coretemp_attributes,
 127 };
 128
 129 static struct coretemp_data *coretemp_update_device(struct device *dev)
 130 {
 131         struct coretemp_data *data = dev_get_drvdata(dev);
 132
 133         mutex_lock(&data->update_lock);
 134
 135         if (!data->valid || time_after(jiffies, data->last_updated + HZ)) {
 136                 u32 eax, edx;
 137
 138                 data->valid = 0;
 139                 rdmsr_on_cpu(data->id, MSR_IA32_THERM_STATUS, &eax, &edx);
 140                 data->alarm = (eax >> 5) & 1;
 141                 /* update only if data has been valid */
 142                 if (eax & 0x80000000) {
 143                         data->temp = data->tjmax - (((eax >> 16)
 144                                                         & 0x7f) * 1000);
 145                         data->valid = 1;
 146                 } else {
 147                         dev_dbg(dev, "Temperature data invalid (0x%x)\n", eax);
 148                 }
 149                 data->last_updated = jiffies;
 150         }
 151
 152         mutex_unlock(&data->update_lock);
 153         return data;
 154 }
 155
 156 static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
 157 {
 158         /* The 100C is default for both mobile and non mobile CPUs */
 159
 160         int tjmax = 100000;
 161         int tjmax_ee = 85000;
 162         int usemsr_ee = 1;
 163         int err;
 164         u32 eax, edx;
 165         struct pci_dev *host_bridge;
 166
 167         /* Early chips have no MSR for TjMax */
 168
 169         if ((c->x86_model == 0xf) && (c->x86_mask < 4)) {
 170                 usemsr_ee = 0;
 171         }
 172
 173         /* Atom CPUs */
 174
 175         if (c->x86_model == 0x1c) {
 176                 usemsr_ee = 0;
 177
 178                 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 179
 180                 if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL
 181                     && (host_bridge->device == 0xa000   /* NM10 based nettop */
 182                     || host_bridge->device == 0xa010))  /* NM10 based netbook */
 183                         tjmax = 100000;
 184                 else
 185                         tjmax = 90000;
 186
 187                 pci_dev_put(host_bridge);
 188         }
 189
 190         if ((c->x86_model > 0xe) && (usemsr_ee)) {
 191                 u8 platform_id;
 192
 193                 /* Now we can detect the mobile CPU using Intel provided table
 194                    http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
 195                    For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU
 196                 */
 197
 198                 err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx);
 199                 if (err) {
 200                         dev_warn(dev,
 201                                  "Unable to access MSR 0x17, assuming desktop"
 202                                  " CPU\n");
 203                         usemsr_ee = 0;
 204                 } else if (c->x86_model < 0x17 && !(eax & 0x10000000)) {
 205                         /* Trust bit 28 up to Penryn, I could not find any
 206                            documentation on that; if you happen to know
 207                            someone at Intel please ask */
 208                         usemsr_ee = 0;
 209                 } else {
 210                         /* Platform ID bits 52:50 (EDX starts at bit 32) */
 211                         platform_id = (edx >> 18) & 0x7;
 212
 213                         /* Mobile Penryn CPU seems to be platform ID 7 or 5
 214                           (guesswork) */
 215                         if ((c->x86_model == 0x17) &&
 216                             ((platform_id == 5) || (platform_id == 7))) {
 217                                 /* If MSR EE bit is set, set it to 90 degrees C,
 218                                    otherwise 105 degrees C */
 219                                 tjmax_ee = 90000;
 220                                 tjmax = 105000;
 221                         }
 222                 }
 223         }
 224
 225         if (usemsr_ee) {
 226
 227                 err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx);
 228                 if (err) {
 229                         dev_warn(dev,
 230                                  "Unable to access MSR 0xEE, for Tjmax, left"
 231                                  " at default\n");
 232                 } else if (eax & 0x40000000) {
 233                         tjmax = tjmax_ee;
 234                 }
 235         /* if we dont use msr EE it means we are desktop CPU (with exeception
 236            of Atom) */
 237         } else if (tjmax == 100000) {
 238                 dev_warn(dev, "Using relative temperature scale!\n");
 239         }
 240
 241         return tjmax;
 242 }
 243
 244 static int __devinit get_tjmax(struct cpuinfo_x86 *c, u32 id,
 245                                struct device *dev)
 246 {
 247         /* The 100C is default for both mobile and non mobile CPUs */
 248         int err;
 249         u32 eax, edx;
 250         u32 val;
 251
 252         /* A new feature of current Intel(R) processors, the
 253            IA32_TEMPERATURE_TARGET contains the TjMax value */
 254         err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
 255         if (err) {
 256                 dev_warn(dev, "Unable to read TjMax from CPU.\n");
 257         } else {
 258                 val = (eax >> 16) & 0xff;
 259                 /*
 260                  * If the TjMax is not plausible, an assumption
 261                  * will be used
 262                  */
 263                 if ((val > 80) && (val < 120)) {
 264                         dev_info(dev, "TjMax is %d C.\n", val);
 265                         return val * 1000;
 266                 }
 267         }
 268
 269         /*
 270          * An assumption is made for early CPUs and unreadable MSR.
 271          * NOTE: the given value may not be correct.
 272          */
 273
 274         switch (c->x86_model) {
 275         case 0xe:
 276         case 0xf:
 277         case 0x16:
 278         case 0x1a:
 279                 dev_warn(dev, "TjMax is assumed as 100 C!\n");
 280                 return 100000;
 281                 break;
 282         case 0x17:
 283         case 0x1c:              /* Atom CPUs */
 284                 return adjust_tjmax(c, id, dev);
 285                 break;
 286         default:
 287                 dev_warn(dev, "CPU (model=0x%x) is not supported yet,"
 288                         " using default TjMax of 100C.\n", c->x86_model);
 289                 return 100000;
 290         }
 291 }
 292
 293 static int __devinit coretemp_probe(struct platform_device *pdev)
 294 {
 295         struct coretemp_data *data;
 296         struct cpuinfo_x86 *c = &cpu_data(pdev->id);
 297         int err;
 298         u32 eax, edx;
 299
 300         if (!(data = kzalloc(sizeof(struct coretemp_data), GFP_KERNEL))) {
 301                 err = -ENOMEM;
 302                 dev_err(&pdev->dev, "Out of memory\n");
 303                 goto exit;
 304         }
 305
 306         data->id = pdev->id;
 307         data->name = "coretemp";
 308         mutex_init(&data->update_lock);
 309
 310         /* test if we can access the THERM_STATUS MSR */
 311         err = rdmsr_safe_on_cpu(data->id, MSR_IA32_THERM_STATUS, &eax, &edx);
 312         if (err) {
 313                 dev_err(&pdev->dev,
 314                         "Unable to access THERM_STATUS MSR, giving up\n");
 315                 goto exit_free;
 316         }
 317
 318         /* Check if we have problem with errata AE18 of Core processors:
 319            Readings might stop update when processor visited too deep sleep,
 320            fixed for stepping D0 (6EC).
 321         */
 322
 323         if ((c->x86_model == 0xe) && (c->x86_mask < 0xc)) {
 324                 /* check for microcode update */
 325                 rdmsr_on_cpu(data->id, MSR_IA32_UCODE_REV, &eax, &edx);
 326                 if (edx < 0x39) {
 327                         err = -ENODEV;
 328                         dev_err(&pdev->dev,
 329                                 "Errata AE18 not fixed, update BIOS or "
 330                                 "microcode of the CPU!\n");
 331                         goto exit_free;
 332                 }
 333         }
 334
 335         data->tjmax = get_tjmax(c, data->id, &pdev->dev);
 336         platform_set_drvdata(pdev, data);
 337
 338         /*
 339          * read the still undocumented IA32_TEMPERATURE_TARGET. It exists
 340          * on older CPUs but not in this register,
 341          * Atoms don't have it either.
 342          */
 343
 344         if ((c->x86_model > 0xe) && (c->x86_model != 0x1c)) {
 345                 err = rdmsr_safe_on_cpu(data->id, MSR_IA32_TEMPERATURE_TARGET,
 346                     &eax, &edx);
 347                 if (err) {
 348                         dev_warn(&pdev->dev, "Unable to read"
 349                                         " IA32_TEMPERATURE_TARGET MSR\n");
 350                 } else {
 351                         data->ttarget = data->tjmax -
 352                                         (((eax >> 8) & 0xff) * 1000);
 353                         err = device_create_file(&pdev->dev,
 354                                         &sensor_dev_attr_temp1_max.dev_attr);
 355                         if (err)
 356                                 goto exit_free;
 357                 }
 358         }
 359
 360         if ((err = sysfs_create_group(&pdev->dev.kobj, &coretemp_group)))
 361                 goto exit_dev;
 362
 363         data->hwmon_dev = hwmon_device_register(&pdev->dev);
 364         if (IS_ERR(data->hwmon_dev)) {
 365                 err = PTR_ERR(data->hwmon_dev);
 366                 dev_err(&pdev->dev, "Class registration failed (%d)\n",
 367                         err);
 368                 goto exit_class;
 369         }
 370
 371         return 0;
 372
 373 exit_class:
 374         sysfs_remove_group(&pdev->dev.kobj, &coretemp_group);
 375 exit_dev:
 376         device_remove_file(&pdev->dev, &sensor_dev_attr_temp1_max.dev_attr);
 377 exit_free:
 378         kfree(data);
 379 exit:
 380         return err;
 381 }
 382
 383 static int __devexit coretemp_remove(struct platform_device *pdev)
 384 {
 385         struct coretemp_data *data = platform_get_drvdata(pdev);
 386
 387         hwmon_device_unregister(data->hwmon_dev);
 388         sysfs_remove_group(&pdev->dev.kobj, &coretemp_group);
 389         device_remove_file(&pdev->dev, &sensor_dev_attr_temp1_max.dev_attr);
 390         platform_set_drvdata(pdev, NULL);
 391         kfree(data);
 392         return 0;
 393 }
 394
 395 static struct platform_driver coretemp_driver = {
 396         .driver = {
 397                 .owner = THIS_MODULE,
 398                 .name = DRVNAME,
 399         },
 400         .probe = coretemp_probe,
 401         .remove = __devexit_p(coretemp_remove),
 402 };
 403
 404 struct pdev_entry {
 405         struct list_head list;
 406         struct platform_device *pdev;
 407         unsigned int cpu;
 408 };
 409
 410 static LIST_HEAD(pdev_list);
 411 static DEFINE_MUTEX(pdev_list_mutex);
 412
 413 static int __cpuinit coretemp_device_add(unsigned int cpu)
 414 {
 415         int err;
 416         struct platform_device *pdev;
 417         struct pdev_entry *pdev_entry;
 418
 419         pdev = platform_device_alloc(DRVNAME, cpu);
 420         if (!pdev) {
 421                 err = -ENOMEM;
 422                 printk(KERN_ERR DRVNAME ": Device allocation failed\n");
 423                 goto exit;
 424         }
 425
 426         pdev_entry = kzalloc(sizeof(struct pdev_entry), GFP_KERNEL);
 427         if (!pdev_entry) {
 428                 err = -ENOMEM;
 429                 goto exit_device_put;
 430         }
 431
 432         err = platform_device_add(pdev);
 433         if (err) {
 434                 printk(KERN_ERR DRVNAME ": Device addition failed (%d)\n",
 435                        err);
 436                 goto exit_device_free;
 437         }
 438
 439         pdev_entry->pdev = pdev;
 440         pdev_entry->cpu = cpu;
 441         mutex_lock(&pdev_list_mutex);
 442         list_add_tail(&pdev_entry->list, &pdev_list);
 443         mutex_unlock(&pdev_list_mutex);
 444
 445         return 0;
 446
 447 exit_device_free:
 448         kfree(pdev_entry);
 449 exit_device_put:
 450         platform_device_put(pdev);
 451 exit:
 452         return err;
 453 }
 454
 455 #ifdef CONFIG_HOTPLUG_CPU
 456 static void coretemp_device_remove(unsigned int cpu)
 457 {
 458         struct pdev_entry *p, *n;
 459         mutex_lock(&pdev_list_mutex);
 460         list_for_each_entry_safe(p, n, &pdev_list, list) {
 461                 if (p->cpu == cpu) {
 462                         platform_device_unregister(p->pdev);
 463                         list_del(&p->list);
 464                         kfree(p);
 465                 }
 466         }
 467         mutex_unlock(&pdev_list_mutex);
 468 }
 469
 470 static int __cpuinit coretemp_cpu_callback(struct notifier_block *nfb,
 471                                  unsigned long action, void *hcpu)
 472 {
 473         unsigned int cpu = (unsigned long) hcpu;
 474
 475         switch (action) {
 476         case CPU_ONLINE:
 477         case CPU_DOWN_FAILED:
 478                 coretemp_device_add(cpu);
 479                 break;
 480         case CPU_DOWN_PREPARE:
 481                 coretemp_device_remove(cpu);
 482                 break;
 483         }
 484         return NOTIFY_OK;
 485 }
 486
 487 static struct notifier_block coretemp_cpu_notifier __refdata = {
 488         .notifier_call = coretemp_cpu_callback,
 489 };
 490 #endif                          /* !CONFIG_HOTPLUG_CPU */
 491
 492 static int __init coretemp_init(void)
 493 {
 494         int i, err = -ENODEV;
 495         struct pdev_entry *p, *n;
 496
 497         /* quick check if we run Intel */
 498         if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL)
 499                 goto exit;
 500
 501         err = platform_driver_register(&coretemp_driver);
 502         if (err)
 503                 goto exit;
 504
 505         for_each_online_cpu(i) {
 506                 struct cpuinfo_x86 *c = &cpu_data(i);
 507                 /*
 508                  * CPUID.06H.EAX[0] indicates whether the CPU has thermal
 509                  * sensors. We check this bit only, all the early CPUs
 510                  * without thermal sensors will be filtered out.
 511                  */
 512                 if (c->cpuid_level >= 6 && (cpuid_eax(0x06) & 0x01)) {
 513                         err = coretemp_device_add(i);
 514                         if (err)
 515                                 goto exit_devices_unreg;
 516
 517                 } else {
 518                         printk(KERN_INFO DRVNAME ": CPU (model=0x%x)"
 519                                 " has no thermal sensor.\n", c->x86_model);
 520                 }
 521         }
 522         if (list_empty(&pdev_list)) {
 523                 err = -ENODEV;
 524                 goto exit_driver_unreg;
 525         }
 526
 527 #ifdef CONFIG_HOTPLUG_CPU
 528         register_hotcpu_notifier(&coretemp_cpu_notifier);
 529 #endif
 530         return 0;
 531
 532 exit_devices_unreg:
 533         mutex_lock(&pdev_list_mutex);
 534         list_for_each_entry_safe(p, n, &pdev_list, list) {
 535                 platform_device_unregister(p->pdev);
 536                 list_del(&p->list);
 537                 kfree(p);
 538         }
 539         mutex_unlock(&pdev_list_mutex);
 540 exit_driver_unreg:
 541         platform_driver_unregister(&coretemp_driver);
 542 exit:
 543         return err;
 544 }
 545
 546 static void __exit coretemp_exit(void)
 547 {
 548         struct pdev_entry *p, *n;
 549 #ifdef CONFIG_HOTPLUG_CPU
 550         unregister_hotcpu_notifier(&coretemp_cpu_notifier);
 551 #endif
 552         mutex_lock(&pdev_list_mutex);
 553         list_for_each_entry_safe(p, n, &pdev_list, list) {
 554                 platform_device_unregister(p->pdev);
 555                 list_del(&p->list);
 556                 kfree(p);
 557         }
 558         mutex_unlock(&pdev_list_mutex);
 559         platform_driver_unregister(&coretemp_driver);
 560 }
 561
 562 MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>");
 563 MODULE_DESCRIPTION("Intel Core temperature monitor");
 564 MODULE_LICENSE("GPL");
 565
 566 module_init(coretemp_init)
 567 module_exit(coretemp_exit)