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hwmon: VRM is not read from registers
[deliverable/linux.git] / drivers / hwmon / w83627hf.c
1 /*
2 w83627hf.c - Part of lm_sensors, Linux kernel modules for hardware
3 monitoring
4 Copyright (c) 1998 - 2003 Frodo Looijaard <frodol@dds.nl>,
5 Philip Edelbrock <phil@netroedge.com>,
6 and Mark Studebaker <mdsxyz123@yahoo.com>
7 Ported to 2.6 by Bernhard C. Schrenk <clemy@clemy.org>
8 Copyright (c) 2007 Jean Delvare <khali@linux-fr.org>
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 /*
26 Supports following chips:
27
28 Chip #vin #fanin #pwm #temp wchipid vendid i2c ISA
29 w83627hf 9 3 2 3 0x20 0x5ca3 no yes(LPC)
30 w83627thf 7 3 3 3 0x90 0x5ca3 no yes(LPC)
31 w83637hf 7 3 3 3 0x80 0x5ca3 no yes(LPC)
32 w83687thf 7 3 3 3 0x90 0x5ca3 no yes(LPC)
33 w83697hf 8 2 2 2 0x60 0x5ca3 no yes(LPC)
34
35 For other winbond chips, and for i2c support in the above chips,
36 use w83781d.c.
37
38 Note: automatic ("cruise") fan control for 697, 637 & 627thf not
39 supported yet.
40 */
41
42 #include <linux/module.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/jiffies.h>
46 #include <linux/platform_device.h>
47 #include <linux/hwmon.h>
48 #include <linux/hwmon-vid.h>
49 #include <linux/err.h>
50 #include <linux/mutex.h>
51 #include <linux/ioport.h>
52 #include <asm/io.h>
53 #include "lm75.h"
54
55 static struct platform_device *pdev;
56
57 #define DRVNAME "w83627hf"
58 enum chips { w83627hf, w83627thf, w83697hf, w83637hf, w83687thf };
59
60 static u16 force_addr;
61 module_param(force_addr, ushort, 0);
62 MODULE_PARM_DESC(force_addr,
63 "Initialize the base address of the sensors");
64 static u8 force_i2c = 0x1f;
65 module_param(force_i2c, byte, 0);
66 MODULE_PARM_DESC(force_i2c,
67 "Initialize the i2c address of the sensors");
68
69 static int reset;
70 module_param(reset, bool, 0);
71 MODULE_PARM_DESC(reset, "Set to one to reset chip on load");
72
73 static int init = 1;
74 module_param(init, bool, 0);
75 MODULE_PARM_DESC(init, "Set to zero to bypass chip initialization");
76
77 /* modified from kernel/include/traps.c */
78 static int REG; /* The register to read/write */
79 #define DEV 0x07 /* Register: Logical device select */
80 static int VAL; /* The value to read/write */
81
82 /* logical device numbers for superio_select (below) */
83 #define W83627HF_LD_FDC 0x00
84 #define W83627HF_LD_PRT 0x01
85 #define W83627HF_LD_UART1 0x02
86 #define W83627HF_LD_UART2 0x03
87 #define W83627HF_LD_KBC 0x05
88 #define W83627HF_LD_CIR 0x06 /* w83627hf only */
89 #define W83627HF_LD_GAME 0x07
90 #define W83627HF_LD_MIDI 0x07
91 #define W83627HF_LD_GPIO1 0x07
92 #define W83627HF_LD_GPIO5 0x07 /* w83627thf only */
93 #define W83627HF_LD_GPIO2 0x08
94 #define W83627HF_LD_GPIO3 0x09
95 #define W83627HF_LD_GPIO4 0x09 /* w83627thf only */
96 #define W83627HF_LD_ACPI 0x0a
97 #define W83627HF_LD_HWM 0x0b
98
99 #define DEVID 0x20 /* Register: Device ID */
100
101 #define W83627THF_GPIO5_EN 0x30 /* w83627thf only */
102 #define W83627THF_GPIO5_IOSR 0xf3 /* w83627thf only */
103 #define W83627THF_GPIO5_DR 0xf4 /* w83627thf only */
104
105 #define W83687THF_VID_EN 0x29 /* w83687thf only */
106 #define W83687THF_VID_CFG 0xF0 /* w83687thf only */
107 #define W83687THF_VID_DATA 0xF1 /* w83687thf only */
108
109 static inline void
110 superio_outb(int reg, int val)
111 {
112 outb(reg, REG);
113 outb(val, VAL);
114 }
115
116 static inline int
117 superio_inb(int reg)
118 {
119 outb(reg, REG);
120 return inb(VAL);
121 }
122
123 static inline void
124 superio_select(int ld)
125 {
126 outb(DEV, REG);
127 outb(ld, VAL);
128 }
129
130 static inline void
131 superio_enter(void)
132 {
133 outb(0x87, REG);
134 outb(0x87, REG);
135 }
136
137 static inline void
138 superio_exit(void)
139 {
140 outb(0xAA, REG);
141 }
142
143 #define W627_DEVID 0x52
144 #define W627THF_DEVID 0x82
145 #define W697_DEVID 0x60
146 #define W637_DEVID 0x70
147 #define W687THF_DEVID 0x85
148 #define WINB_ACT_REG 0x30
149 #define WINB_BASE_REG 0x60
150 /* Constants specified below */
151
152 /* Alignment of the base address */
153 #define WINB_ALIGNMENT ~7
154
155 /* Offset & size of I/O region we are interested in */
156 #define WINB_REGION_OFFSET 5
157 #define WINB_REGION_SIZE 2
158
159 /* Where are the sensors address/data registers relative to the region offset */
160 #define W83781D_ADDR_REG_OFFSET 0
161 #define W83781D_DATA_REG_OFFSET 1
162
163 /* The W83781D registers */
164 /* The W83782D registers for nr=7,8 are in bank 5 */
165 #define W83781D_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
166 (0x554 + (((nr) - 7) * 2)))
167 #define W83781D_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
168 (0x555 + (((nr) - 7) * 2)))
169 #define W83781D_REG_IN(nr) ((nr < 7) ? (0x20 + (nr)) : \
170 (0x550 + (nr) - 7))
171
172 #define W83781D_REG_FAN_MIN(nr) (0x3a + (nr))
173 #define W83781D_REG_FAN(nr) (0x27 + (nr))
174
175 #define W83781D_REG_TEMP2_CONFIG 0x152
176 #define W83781D_REG_TEMP3_CONFIG 0x252
177 #define W83781D_REG_TEMP(nr) ((nr == 3) ? (0x0250) : \
178 ((nr == 2) ? (0x0150) : \
179 (0x27)))
180 #define W83781D_REG_TEMP_HYST(nr) ((nr == 3) ? (0x253) : \
181 ((nr == 2) ? (0x153) : \
182 (0x3A)))
183 #define W83781D_REG_TEMP_OVER(nr) ((nr == 3) ? (0x255) : \
184 ((nr == 2) ? (0x155) : \
185 (0x39)))
186
187 #define W83781D_REG_BANK 0x4E
188
189 #define W83781D_REG_CONFIG 0x40
190 #define W83781D_REG_ALARM1 0x459
191 #define W83781D_REG_ALARM2 0x45A
192 #define W83781D_REG_ALARM3 0x45B
193
194 #define W83781D_REG_BEEP_CONFIG 0x4D
195 #define W83781D_REG_BEEP_INTS1 0x56
196 #define W83781D_REG_BEEP_INTS2 0x57
197 #define W83781D_REG_BEEP_INTS3 0x453
198
199 #define W83781D_REG_VID_FANDIV 0x47
200
201 #define W83781D_REG_CHIPID 0x49
202 #define W83781D_REG_WCHIPID 0x58
203 #define W83781D_REG_CHIPMAN 0x4F
204 #define W83781D_REG_PIN 0x4B
205
206 #define W83781D_REG_VBAT 0x5D
207
208 #define W83627HF_REG_PWM1 0x5A
209 #define W83627HF_REG_PWM2 0x5B
210
211 #define W83627THF_REG_PWM1 0x01 /* 697HF/637HF/687THF too */
212 #define W83627THF_REG_PWM2 0x03 /* 697HF/637HF/687THF too */
213 #define W83627THF_REG_PWM3 0x11 /* 637HF/687THF too */
214
215 #define W83627THF_REG_VRM_OVT_CFG 0x18 /* 637HF/687THF too */
216
217 static const u8 regpwm_627hf[] = { W83627HF_REG_PWM1, W83627HF_REG_PWM2 };
218 static const u8 regpwm[] = { W83627THF_REG_PWM1, W83627THF_REG_PWM2,
219 W83627THF_REG_PWM3 };
220 #define W836X7HF_REG_PWM(type, nr) (((type) == w83627hf) ? \
221 regpwm_627hf[(nr) - 1] : regpwm[(nr) - 1])
222
223 #define W83627HF_REG_PWM_FREQ 0x5C /* Only for the 627HF */
224
225 #define W83637HF_REG_PWM_FREQ1 0x00 /* 697HF/687THF too */
226 #define W83637HF_REG_PWM_FREQ2 0x02 /* 697HF/687THF too */
227 #define W83637HF_REG_PWM_FREQ3 0x10 /* 687THF too */
228
229 static const u8 W83637HF_REG_PWM_FREQ[] = { W83637HF_REG_PWM_FREQ1,
230 W83637HF_REG_PWM_FREQ2,
231 W83637HF_REG_PWM_FREQ3 };
232
233 #define W83627HF_BASE_PWM_FREQ 46870
234
235 #define W83781D_REG_I2C_ADDR 0x48
236 #define W83781D_REG_I2C_SUBADDR 0x4A
237
238 /* Sensor selection */
239 #define W83781D_REG_SCFG1 0x5D
240 static const u8 BIT_SCFG1[] = { 0x02, 0x04, 0x08 };
241 #define W83781D_REG_SCFG2 0x59
242 static const u8 BIT_SCFG2[] = { 0x10, 0x20, 0x40 };
243 #define W83781D_DEFAULT_BETA 3435
244
245 /* Conversions. Limit checking is only done on the TO_REG
246 variants. Note that you should be a bit careful with which arguments
247 these macros are called: arguments may be evaluated more than once.
248 Fixing this is just not worth it. */
249 #define IN_TO_REG(val) (SENSORS_LIMIT((((val) + 8)/16),0,255))
250 #define IN_FROM_REG(val) ((val) * 16)
251
252 static inline u8 FAN_TO_REG(long rpm, int div)
253 {
254 if (rpm == 0)
255 return 255;
256 rpm = SENSORS_LIMIT(rpm, 1, 1000000);
257 return SENSORS_LIMIT((1350000 + rpm * div / 2) / (rpm * div), 1,
258 254);
259 }
260
261 #define TEMP_MIN (-128000)
262 #define TEMP_MAX ( 127000)
263
264 /* TEMP: 0.001C/bit (-128C to +127C)
265 REG: 1C/bit, two's complement */
266 static u8 TEMP_TO_REG(long temp)
267 {
268 int ntemp = SENSORS_LIMIT(temp, TEMP_MIN, TEMP_MAX);
269 ntemp += (ntemp<0 ? -500 : 500);
270 return (u8)(ntemp / 1000);
271 }
272
273 static int TEMP_FROM_REG(u8 reg)
274 {
275 return (s8)reg * 1000;
276 }
277
278 #define FAN_FROM_REG(val,div) ((val)==0?-1:(val)==255?0:1350000/((val)*(div)))
279
280 #define PWM_TO_REG(val) (SENSORS_LIMIT((val),0,255))
281
282 static inline unsigned long pwm_freq_from_reg_627hf(u8 reg)
283 {
284 unsigned long freq;
285 freq = W83627HF_BASE_PWM_FREQ >> reg;
286 return freq;
287 }
288 static inline u8 pwm_freq_to_reg_627hf(unsigned long val)
289 {
290 u8 i;
291 /* Only 5 dividers (1 2 4 8 16)
292 Search for the nearest available frequency */
293 for (i = 0; i < 4; i++) {
294 if (val > (((W83627HF_BASE_PWM_FREQ >> i) +
295 (W83627HF_BASE_PWM_FREQ >> (i+1))) / 2))
296 break;
297 }
298 return i;
299 }
300
301 static inline unsigned long pwm_freq_from_reg(u8 reg)
302 {
303 /* Clock bit 8 -> 180 kHz or 24 MHz */
304 unsigned long clock = (reg & 0x80) ? 180000UL : 24000000UL;
305
306 reg &= 0x7f;
307 /* This should not happen but anyway... */
308 if (reg == 0)
309 reg++;
310 return (clock / (reg << 8));
311 }
312 static inline u8 pwm_freq_to_reg(unsigned long val)
313 {
314 /* Minimum divider value is 0x01 and maximum is 0x7F */
315 if (val >= 93750) /* The highest we can do */
316 return 0x01;
317 if (val >= 720) /* Use 24 MHz clock */
318 return (24000000UL / (val << 8));
319 if (val < 6) /* The lowest we can do */
320 return 0xFF;
321 else /* Use 180 kHz clock */
322 return (0x80 | (180000UL / (val << 8)));
323 }
324
325 #define BEEP_MASK_FROM_REG(val) (val)
326 #define BEEP_MASK_TO_REG(val) ((val) & 0xffffff)
327 #define BEEP_ENABLE_TO_REG(val) ((val)?1:0)
328 #define BEEP_ENABLE_FROM_REG(val) ((val)?1:0)
329
330 #define DIV_FROM_REG(val) (1 << (val))
331
332 static inline u8 DIV_TO_REG(long val)
333 {
334 int i;
335 val = SENSORS_LIMIT(val, 1, 128) >> 1;
336 for (i = 0; i < 7; i++) {
337 if (val == 0)
338 break;
339 val >>= 1;
340 }
341 return ((u8) i);
342 }
343
344 /* For each registered chip, we need to keep some data in memory.
345 The structure is dynamically allocated. */
346 struct w83627hf_data {
347 unsigned short addr;
348 const char *name;
349 struct device *hwmon_dev;
350 struct mutex lock;
351 enum chips type;
352
353 struct mutex update_lock;
354 char valid; /* !=0 if following fields are valid */
355 unsigned long last_updated; /* In jiffies */
356
357 u8 in[9]; /* Register value */
358 u8 in_max[9]; /* Register value */
359 u8 in_min[9]; /* Register value */
360 u8 fan[3]; /* Register value */
361 u8 fan_min[3]; /* Register value */
362 u8 temp;
363 u8 temp_max; /* Register value */
364 u8 temp_max_hyst; /* Register value */
365 u16 temp_add[2]; /* Register value */
366 u16 temp_max_add[2]; /* Register value */
367 u16 temp_max_hyst_add[2]; /* Register value */
368 u8 fan_div[3]; /* Register encoding, shifted right */
369 u8 vid; /* Register encoding, combined */
370 u32 alarms; /* Register encoding, combined */
371 u32 beep_mask; /* Register encoding, combined */
372 u8 beep_enable; /* Boolean */
373 u8 pwm[3]; /* Register value */
374 u8 pwm_freq[3]; /* Register value */
375 u16 sens[3]; /* 1 = pentium diode; 2 = 3904 diode;
376 4 = thermistor */
377 u8 vrm;
378 u8 vrm_ovt; /* Register value, 627THF/637HF/687THF only */
379 };
380
381 struct w83627hf_sio_data {
382 enum chips type;
383 };
384
385
386 static int w83627hf_probe(struct platform_device *pdev);
387 static int __devexit w83627hf_remove(struct platform_device *pdev);
388
389 static int w83627hf_read_value(struct w83627hf_data *data, u16 reg);
390 static int w83627hf_write_value(struct w83627hf_data *data, u16 reg, u16 value);
391 static struct w83627hf_data *w83627hf_update_device(struct device *dev);
392 static void w83627hf_init_device(struct platform_device *pdev);
393
394 static struct platform_driver w83627hf_driver = {
395 .driver = {
396 .owner = THIS_MODULE,
397 .name = DRVNAME,
398 },
399 .probe = w83627hf_probe,
400 .remove = __devexit_p(w83627hf_remove),
401 };
402
403 /* following are the sysfs callback functions */
404 #define show_in_reg(reg) \
405 static ssize_t show_##reg (struct device *dev, char *buf, int nr) \
406 { \
407 struct w83627hf_data *data = w83627hf_update_device(dev); \
408 return sprintf(buf,"%ld\n", (long)IN_FROM_REG(data->reg[nr])); \
409 }
410 show_in_reg(in)
411 show_in_reg(in_min)
412 show_in_reg(in_max)
413
414 #define store_in_reg(REG, reg) \
415 static ssize_t \
416 store_in_##reg (struct device *dev, const char *buf, size_t count, int nr) \
417 { \
418 struct w83627hf_data *data = dev_get_drvdata(dev); \
419 u32 val; \
420 \
421 val = simple_strtoul(buf, NULL, 10); \
422 \
423 mutex_lock(&data->update_lock); \
424 data->in_##reg[nr] = IN_TO_REG(val); \
425 w83627hf_write_value(data, W83781D_REG_IN_##REG(nr), \
426 data->in_##reg[nr]); \
427 \
428 mutex_unlock(&data->update_lock); \
429 return count; \
430 }
431 store_in_reg(MIN, min)
432 store_in_reg(MAX, max)
433
434 #define sysfs_in_offset(offset) \
435 static ssize_t \
436 show_regs_in_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
437 { \
438 return show_in(dev, buf, offset); \
439 } \
440 static DEVICE_ATTR(in##offset##_input, S_IRUGO, show_regs_in_##offset, NULL);
441
442 #define sysfs_in_reg_offset(reg, offset) \
443 static ssize_t show_regs_in_##reg##offset (struct device *dev, struct device_attribute *attr, char *buf) \
444 { \
445 return show_in_##reg (dev, buf, offset); \
446 } \
447 static ssize_t \
448 store_regs_in_##reg##offset (struct device *dev, struct device_attribute *attr, \
449 const char *buf, size_t count) \
450 { \
451 return store_in_##reg (dev, buf, count, offset); \
452 } \
453 static DEVICE_ATTR(in##offset##_##reg, S_IRUGO| S_IWUSR, \
454 show_regs_in_##reg##offset, store_regs_in_##reg##offset);
455
456 #define sysfs_in_offsets(offset) \
457 sysfs_in_offset(offset) \
458 sysfs_in_reg_offset(min, offset) \
459 sysfs_in_reg_offset(max, offset)
460
461 sysfs_in_offsets(1);
462 sysfs_in_offsets(2);
463 sysfs_in_offsets(3);
464 sysfs_in_offsets(4);
465 sysfs_in_offsets(5);
466 sysfs_in_offsets(6);
467 sysfs_in_offsets(7);
468 sysfs_in_offsets(8);
469
470 /* use a different set of functions for in0 */
471 static ssize_t show_in_0(struct w83627hf_data *data, char *buf, u8 reg)
472 {
473 long in0;
474
475 if ((data->vrm_ovt & 0x01) &&
476 (w83627thf == data->type || w83637hf == data->type
477 || w83687thf == data->type))
478
479 /* use VRM9 calculation */
480 in0 = (long)((reg * 488 + 70000 + 50) / 100);
481 else
482 /* use VRM8 (standard) calculation */
483 in0 = (long)IN_FROM_REG(reg);
484
485 return sprintf(buf,"%ld\n", in0);
486 }
487
488 static ssize_t show_regs_in_0(struct device *dev, struct device_attribute *attr, char *buf)
489 {
490 struct w83627hf_data *data = w83627hf_update_device(dev);
491 return show_in_0(data, buf, data->in[0]);
492 }
493
494 static ssize_t show_regs_in_min0(struct device *dev, struct device_attribute *attr, char *buf)
495 {
496 struct w83627hf_data *data = w83627hf_update_device(dev);
497 return show_in_0(data, buf, data->in_min[0]);
498 }
499
500 static ssize_t show_regs_in_max0(struct device *dev, struct device_attribute *attr, char *buf)
501 {
502 struct w83627hf_data *data = w83627hf_update_device(dev);
503 return show_in_0(data, buf, data->in_max[0]);
504 }
505
506 static ssize_t store_regs_in_min0(struct device *dev, struct device_attribute *attr,
507 const char *buf, size_t count)
508 {
509 struct w83627hf_data *data = dev_get_drvdata(dev);
510 u32 val;
511
512 val = simple_strtoul(buf, NULL, 10);
513
514 mutex_lock(&data->update_lock);
515
516 if ((data->vrm_ovt & 0x01) &&
517 (w83627thf == data->type || w83637hf == data->type
518 || w83687thf == data->type))
519
520 /* use VRM9 calculation */
521 data->in_min[0] =
522 SENSORS_LIMIT(((val * 100) - 70000 + 244) / 488, 0,
523 255);
524 else
525 /* use VRM8 (standard) calculation */
526 data->in_min[0] = IN_TO_REG(val);
527
528 w83627hf_write_value(data, W83781D_REG_IN_MIN(0), data->in_min[0]);
529 mutex_unlock(&data->update_lock);
530 return count;
531 }
532
533 static ssize_t store_regs_in_max0(struct device *dev, struct device_attribute *attr,
534 const char *buf, size_t count)
535 {
536 struct w83627hf_data *data = dev_get_drvdata(dev);
537 u32 val;
538
539 val = simple_strtoul(buf, NULL, 10);
540
541 mutex_lock(&data->update_lock);
542
543 if ((data->vrm_ovt & 0x01) &&
544 (w83627thf == data->type || w83637hf == data->type
545 || w83687thf == data->type))
546
547 /* use VRM9 calculation */
548 data->in_max[0] =
549 SENSORS_LIMIT(((val * 100) - 70000 + 244) / 488, 0,
550 255);
551 else
552 /* use VRM8 (standard) calculation */
553 data->in_max[0] = IN_TO_REG(val);
554
555 w83627hf_write_value(data, W83781D_REG_IN_MAX(0), data->in_max[0]);
556 mutex_unlock(&data->update_lock);
557 return count;
558 }
559
560 static DEVICE_ATTR(in0_input, S_IRUGO, show_regs_in_0, NULL);
561 static DEVICE_ATTR(in0_min, S_IRUGO | S_IWUSR,
562 show_regs_in_min0, store_regs_in_min0);
563 static DEVICE_ATTR(in0_max, S_IRUGO | S_IWUSR,
564 show_regs_in_max0, store_regs_in_max0);
565
566 #define show_fan_reg(reg) \
567 static ssize_t show_##reg (struct device *dev, char *buf, int nr) \
568 { \
569 struct w83627hf_data *data = w83627hf_update_device(dev); \
570 return sprintf(buf,"%ld\n", \
571 FAN_FROM_REG(data->reg[nr-1], \
572 (long)DIV_FROM_REG(data->fan_div[nr-1]))); \
573 }
574 show_fan_reg(fan);
575 show_fan_reg(fan_min);
576
577 static ssize_t
578 store_fan_min(struct device *dev, const char *buf, size_t count, int nr)
579 {
580 struct w83627hf_data *data = dev_get_drvdata(dev);
581 u32 val;
582
583 val = simple_strtoul(buf, NULL, 10);
584
585 mutex_lock(&data->update_lock);
586 data->fan_min[nr - 1] =
587 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr - 1]));
588 w83627hf_write_value(data, W83781D_REG_FAN_MIN(nr),
589 data->fan_min[nr - 1]);
590
591 mutex_unlock(&data->update_lock);
592 return count;
593 }
594
595 #define sysfs_fan_offset(offset) \
596 static ssize_t show_regs_fan_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
597 { \
598 return show_fan(dev, buf, offset); \
599 } \
600 static DEVICE_ATTR(fan##offset##_input, S_IRUGO, show_regs_fan_##offset, NULL);
601
602 #define sysfs_fan_min_offset(offset) \
603 static ssize_t show_regs_fan_min##offset (struct device *dev, struct device_attribute *attr, char *buf) \
604 { \
605 return show_fan_min(dev, buf, offset); \
606 } \
607 static ssize_t \
608 store_regs_fan_min##offset (struct device *dev, struct device_attribute *attr, const char *buf, size_t count) \
609 { \
610 return store_fan_min(dev, buf, count, offset); \
611 } \
612 static DEVICE_ATTR(fan##offset##_min, S_IRUGO | S_IWUSR, \
613 show_regs_fan_min##offset, store_regs_fan_min##offset);
614
615 sysfs_fan_offset(1);
616 sysfs_fan_min_offset(1);
617 sysfs_fan_offset(2);
618 sysfs_fan_min_offset(2);
619 sysfs_fan_offset(3);
620 sysfs_fan_min_offset(3);
621
622 #define show_temp_reg(reg) \
623 static ssize_t show_##reg (struct device *dev, char *buf, int nr) \
624 { \
625 struct w83627hf_data *data = w83627hf_update_device(dev); \
626 if (nr >= 2) { /* TEMP2 and TEMP3 */ \
627 return sprintf(buf,"%ld\n", \
628 (long)LM75_TEMP_FROM_REG(data->reg##_add[nr-2])); \
629 } else { /* TEMP1 */ \
630 return sprintf(buf,"%ld\n", (long)TEMP_FROM_REG(data->reg)); \
631 } \
632 }
633 show_temp_reg(temp);
634 show_temp_reg(temp_max);
635 show_temp_reg(temp_max_hyst);
636
637 #define store_temp_reg(REG, reg) \
638 static ssize_t \
639 store_temp_##reg (struct device *dev, const char *buf, size_t count, int nr) \
640 { \
641 struct w83627hf_data *data = dev_get_drvdata(dev); \
642 long val; \
643 \
644 val = simple_strtol(buf, NULL, 10); \
645 \
646 mutex_lock(&data->update_lock); \
647 \
648 if (nr >= 2) { /* TEMP2 and TEMP3 */ \
649 data->temp_##reg##_add[nr-2] = LM75_TEMP_TO_REG(val); \
650 w83627hf_write_value(data, W83781D_REG_TEMP_##REG(nr), \
651 data->temp_##reg##_add[nr-2]); \
652 } else { /* TEMP1 */ \
653 data->temp_##reg = TEMP_TO_REG(val); \
654 w83627hf_write_value(data, W83781D_REG_TEMP_##REG(nr), \
655 data->temp_##reg); \
656 } \
657 \
658 mutex_unlock(&data->update_lock); \
659 return count; \
660 }
661 store_temp_reg(OVER, max);
662 store_temp_reg(HYST, max_hyst);
663
664 #define sysfs_temp_offset(offset) \
665 static ssize_t \
666 show_regs_temp_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
667 { \
668 return show_temp(dev, buf, offset); \
669 } \
670 static DEVICE_ATTR(temp##offset##_input, S_IRUGO, show_regs_temp_##offset, NULL);
671
672 #define sysfs_temp_reg_offset(reg, offset) \
673 static ssize_t show_regs_temp_##reg##offset (struct device *dev, struct device_attribute *attr, char *buf) \
674 { \
675 return show_temp_##reg (dev, buf, offset); \
676 } \
677 static ssize_t \
678 store_regs_temp_##reg##offset (struct device *dev, struct device_attribute *attr, \
679 const char *buf, size_t count) \
680 { \
681 return store_temp_##reg (dev, buf, count, offset); \
682 } \
683 static DEVICE_ATTR(temp##offset##_##reg, S_IRUGO| S_IWUSR, \
684 show_regs_temp_##reg##offset, store_regs_temp_##reg##offset);
685
686 #define sysfs_temp_offsets(offset) \
687 sysfs_temp_offset(offset) \
688 sysfs_temp_reg_offset(max, offset) \
689 sysfs_temp_reg_offset(max_hyst, offset)
690
691 sysfs_temp_offsets(1);
692 sysfs_temp_offsets(2);
693 sysfs_temp_offsets(3);
694
695 static ssize_t
696 show_vid_reg(struct device *dev, struct device_attribute *attr, char *buf)
697 {
698 struct w83627hf_data *data = w83627hf_update_device(dev);
699 return sprintf(buf, "%ld\n", (long) vid_from_reg(data->vid, data->vrm));
700 }
701 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
702
703 static ssize_t
704 show_vrm_reg(struct device *dev, struct device_attribute *attr, char *buf)
705 {
706 struct w83627hf_data *data = dev_get_drvdata(dev);
707 return sprintf(buf, "%ld\n", (long) data->vrm);
708 }
709 static ssize_t
710 store_vrm_reg(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
711 {
712 struct w83627hf_data *data = dev_get_drvdata(dev);
713 u32 val;
714
715 val = simple_strtoul(buf, NULL, 10);
716 data->vrm = val;
717
718 return count;
719 }
720 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
721
722 static ssize_t
723 show_alarms_reg(struct device *dev, struct device_attribute *attr, char *buf)
724 {
725 struct w83627hf_data *data = w83627hf_update_device(dev);
726 return sprintf(buf, "%ld\n", (long) data->alarms);
727 }
728 static DEVICE_ATTR(alarms, S_IRUGO, show_alarms_reg, NULL);
729
730 #define show_beep_reg(REG, reg) \
731 static ssize_t show_beep_##reg (struct device *dev, struct device_attribute *attr, char *buf) \
732 { \
733 struct w83627hf_data *data = w83627hf_update_device(dev); \
734 return sprintf(buf,"%ld\n", \
735 (long)BEEP_##REG##_FROM_REG(data->beep_##reg)); \
736 }
737 show_beep_reg(ENABLE, enable)
738 show_beep_reg(MASK, mask)
739
740 #define BEEP_ENABLE 0 /* Store beep_enable */
741 #define BEEP_MASK 1 /* Store beep_mask */
742
743 static ssize_t
744 store_beep_reg(struct device *dev, const char *buf, size_t count,
745 int update_mask)
746 {
747 struct w83627hf_data *data = dev_get_drvdata(dev);
748 u32 val, val2;
749
750 val = simple_strtoul(buf, NULL, 10);
751
752 mutex_lock(&data->update_lock);
753
754 if (update_mask == BEEP_MASK) { /* We are storing beep_mask */
755 data->beep_mask = BEEP_MASK_TO_REG(val);
756 w83627hf_write_value(data, W83781D_REG_BEEP_INTS1,
757 data->beep_mask & 0xff);
758 w83627hf_write_value(data, W83781D_REG_BEEP_INTS3,
759 ((data->beep_mask) >> 16) & 0xff);
760 val2 = (data->beep_mask >> 8) & 0x7f;
761 } else { /* We are storing beep_enable */
762 val2 =
763 w83627hf_read_value(data, W83781D_REG_BEEP_INTS2) & 0x7f;
764 data->beep_enable = BEEP_ENABLE_TO_REG(val);
765 }
766
767 w83627hf_write_value(data, W83781D_REG_BEEP_INTS2,
768 val2 | data->beep_enable << 7);
769
770 mutex_unlock(&data->update_lock);
771 return count;
772 }
773
774 #define sysfs_beep(REG, reg) \
775 static ssize_t show_regs_beep_##reg (struct device *dev, struct device_attribute *attr, char *buf) \
776 { \
777 return show_beep_##reg(dev, attr, buf); \
778 } \
779 static ssize_t \
780 store_regs_beep_##reg (struct device *dev, struct device_attribute *attr, const char *buf, size_t count) \
781 { \
782 return store_beep_reg(dev, buf, count, BEEP_##REG); \
783 } \
784 static DEVICE_ATTR(beep_##reg, S_IRUGO | S_IWUSR, \
785 show_regs_beep_##reg, store_regs_beep_##reg);
786
787 sysfs_beep(ENABLE, enable);
788 sysfs_beep(MASK, mask);
789
790 static ssize_t
791 show_fan_div_reg(struct device *dev, char *buf, int nr)
792 {
793 struct w83627hf_data *data = w83627hf_update_device(dev);
794 return sprintf(buf, "%ld\n",
795 (long) DIV_FROM_REG(data->fan_div[nr - 1]));
796 }
797
798 /* Note: we save and restore the fan minimum here, because its value is
799 determined in part by the fan divisor. This follows the principle of
800 least surprise; the user doesn't expect the fan minimum to change just
801 because the divisor changed. */
802 static ssize_t
803 store_fan_div_reg(struct device *dev, const char *buf, size_t count, int nr)
804 {
805 struct w83627hf_data *data = dev_get_drvdata(dev);
806 unsigned long min;
807 u8 reg;
808 unsigned long val = simple_strtoul(buf, NULL, 10);
809
810 mutex_lock(&data->update_lock);
811
812 /* Save fan_min */
813 min = FAN_FROM_REG(data->fan_min[nr],
814 DIV_FROM_REG(data->fan_div[nr]));
815
816 data->fan_div[nr] = DIV_TO_REG(val);
817
818 reg = (w83627hf_read_value(data, nr==2 ? W83781D_REG_PIN : W83781D_REG_VID_FANDIV)
819 & (nr==0 ? 0xcf : 0x3f))
820 | ((data->fan_div[nr] & 0x03) << (nr==0 ? 4 : 6));
821 w83627hf_write_value(data, nr==2 ? W83781D_REG_PIN : W83781D_REG_VID_FANDIV, reg);
822
823 reg = (w83627hf_read_value(data, W83781D_REG_VBAT)
824 & ~(1 << (5 + nr)))
825 | ((data->fan_div[nr] & 0x04) << (3 + nr));
826 w83627hf_write_value(data, W83781D_REG_VBAT, reg);
827
828 /* Restore fan_min */
829 data->fan_min[nr] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
830 w83627hf_write_value(data, W83781D_REG_FAN_MIN(nr+1), data->fan_min[nr]);
831
832 mutex_unlock(&data->update_lock);
833 return count;
834 }
835
836 #define sysfs_fan_div(offset) \
837 static ssize_t show_regs_fan_div_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
838 { \
839 return show_fan_div_reg(dev, buf, offset); \
840 } \
841 static ssize_t \
842 store_regs_fan_div_##offset (struct device *dev, struct device_attribute *attr, \
843 const char *buf, size_t count) \
844 { \
845 return store_fan_div_reg(dev, buf, count, offset - 1); \
846 } \
847 static DEVICE_ATTR(fan##offset##_div, S_IRUGO | S_IWUSR, \
848 show_regs_fan_div_##offset, store_regs_fan_div_##offset);
849
850 sysfs_fan_div(1);
851 sysfs_fan_div(2);
852 sysfs_fan_div(3);
853
854 static ssize_t
855 show_pwm_reg(struct device *dev, char *buf, int nr)
856 {
857 struct w83627hf_data *data = w83627hf_update_device(dev);
858 return sprintf(buf, "%ld\n", (long) data->pwm[nr - 1]);
859 }
860
861 static ssize_t
862 store_pwm_reg(struct device *dev, const char *buf, size_t count, int nr)
863 {
864 struct w83627hf_data *data = dev_get_drvdata(dev);
865 u32 val;
866
867 val = simple_strtoul(buf, NULL, 10);
868
869 mutex_lock(&data->update_lock);
870
871 if (data->type == w83627thf) {
872 /* bits 0-3 are reserved in 627THF */
873 data->pwm[nr - 1] = PWM_TO_REG(val) & 0xf0;
874 w83627hf_write_value(data,
875 W836X7HF_REG_PWM(data->type, nr),
876 data->pwm[nr - 1] |
877 (w83627hf_read_value(data,
878 W836X7HF_REG_PWM(data->type, nr)) & 0x0f));
879 } else {
880 data->pwm[nr - 1] = PWM_TO_REG(val);
881 w83627hf_write_value(data,
882 W836X7HF_REG_PWM(data->type, nr),
883 data->pwm[nr - 1]);
884 }
885
886 mutex_unlock(&data->update_lock);
887 return count;
888 }
889
890 #define sysfs_pwm(offset) \
891 static ssize_t show_regs_pwm_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
892 { \
893 return show_pwm_reg(dev, buf, offset); \
894 } \
895 static ssize_t \
896 store_regs_pwm_##offset (struct device *dev, struct device_attribute *attr, const char *buf, size_t count) \
897 { \
898 return store_pwm_reg(dev, buf, count, offset); \
899 } \
900 static DEVICE_ATTR(pwm##offset, S_IRUGO | S_IWUSR, \
901 show_regs_pwm_##offset, store_regs_pwm_##offset);
902
903 sysfs_pwm(1);
904 sysfs_pwm(2);
905 sysfs_pwm(3);
906
907 static ssize_t
908 show_pwm_freq_reg(struct device *dev, char *buf, int nr)
909 {
910 struct w83627hf_data *data = w83627hf_update_device(dev);
911 if (data->type == w83627hf)
912 return sprintf(buf, "%ld\n",
913 pwm_freq_from_reg_627hf(data->pwm_freq[nr - 1]));
914 else
915 return sprintf(buf, "%ld\n",
916 pwm_freq_from_reg(data->pwm_freq[nr - 1]));
917 }
918
919 static ssize_t
920 store_pwm_freq_reg(struct device *dev, const char *buf, size_t count, int nr)
921 {
922 struct w83627hf_data *data = dev_get_drvdata(dev);
923 static const u8 mask[]={0xF8, 0x8F};
924 u32 val;
925
926 val = simple_strtoul(buf, NULL, 10);
927
928 mutex_lock(&data->update_lock);
929
930 if (data->type == w83627hf) {
931 data->pwm_freq[nr - 1] = pwm_freq_to_reg_627hf(val);
932 w83627hf_write_value(data, W83627HF_REG_PWM_FREQ,
933 (data->pwm_freq[nr - 1] << ((nr - 1)*4)) |
934 (w83627hf_read_value(data,
935 W83627HF_REG_PWM_FREQ) & mask[nr - 1]));
936 } else {
937 data->pwm_freq[nr - 1] = pwm_freq_to_reg(val);
938 w83627hf_write_value(data, W83637HF_REG_PWM_FREQ[nr - 1],
939 data->pwm_freq[nr - 1]);
940 }
941
942 mutex_unlock(&data->update_lock);
943 return count;
944 }
945
946 #define sysfs_pwm_freq(offset) \
947 static ssize_t show_regs_pwm_freq_##offset(struct device *dev, \
948 struct device_attribute *attr, char *buf) \
949 { \
950 return show_pwm_freq_reg(dev, buf, offset); \
951 } \
952 static ssize_t \
953 store_regs_pwm_freq_##offset(struct device *dev, \
954 struct device_attribute *attr, const char *buf, size_t count) \
955 { \
956 return store_pwm_freq_reg(dev, buf, count, offset); \
957 } \
958 static DEVICE_ATTR(pwm##offset##_freq, S_IRUGO | S_IWUSR, \
959 show_regs_pwm_freq_##offset, store_regs_pwm_freq_##offset);
960
961 sysfs_pwm_freq(1);
962 sysfs_pwm_freq(2);
963 sysfs_pwm_freq(3);
964
965 static ssize_t
966 show_sensor_reg(struct device *dev, char *buf, int nr)
967 {
968 struct w83627hf_data *data = w83627hf_update_device(dev);
969 return sprintf(buf, "%ld\n", (long) data->sens[nr - 1]);
970 }
971
972 static ssize_t
973 store_sensor_reg(struct device *dev, const char *buf, size_t count, int nr)
974 {
975 struct w83627hf_data *data = dev_get_drvdata(dev);
976 u32 val, tmp;
977
978 val = simple_strtoul(buf, NULL, 10);
979
980 mutex_lock(&data->update_lock);
981
982 switch (val) {
983 case 1: /* PII/Celeron diode */
984 tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);
985 w83627hf_write_value(data, W83781D_REG_SCFG1,
986 tmp | BIT_SCFG1[nr - 1]);
987 tmp = w83627hf_read_value(data, W83781D_REG_SCFG2);
988 w83627hf_write_value(data, W83781D_REG_SCFG2,
989 tmp | BIT_SCFG2[nr - 1]);
990 data->sens[nr - 1] = val;
991 break;
992 case 2: /* 3904 */
993 tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);
994 w83627hf_write_value(data, W83781D_REG_SCFG1,
995 tmp | BIT_SCFG1[nr - 1]);
996 tmp = w83627hf_read_value(data, W83781D_REG_SCFG2);
997 w83627hf_write_value(data, W83781D_REG_SCFG2,
998 tmp & ~BIT_SCFG2[nr - 1]);
999 data->sens[nr - 1] = val;
1000 break;
1001 case W83781D_DEFAULT_BETA:
1002 dev_warn(dev, "Sensor type %d is deprecated, please use 4 "
1003 "instead\n", W83781D_DEFAULT_BETA);
1004 /* fall through */
1005 case 4: /* thermistor */
1006 tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);
1007 w83627hf_write_value(data, W83781D_REG_SCFG1,
1008 tmp & ~BIT_SCFG1[nr - 1]);
1009 data->sens[nr - 1] = val;
1010 break;
1011 default:
1012 dev_err(dev,
1013 "Invalid sensor type %ld; must be 1, 2, or 4\n",
1014 (long) val);
1015 break;
1016 }
1017
1018 mutex_unlock(&data->update_lock);
1019 return count;
1020 }
1021
1022 #define sysfs_sensor(offset) \
1023 static ssize_t show_regs_sensor_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
1024 { \
1025 return show_sensor_reg(dev, buf, offset); \
1026 } \
1027 static ssize_t \
1028 store_regs_sensor_##offset (struct device *dev, struct device_attribute *attr, const char *buf, size_t count) \
1029 { \
1030 return store_sensor_reg(dev, buf, count, offset); \
1031 } \
1032 static DEVICE_ATTR(temp##offset##_type, S_IRUGO | S_IWUSR, \
1033 show_regs_sensor_##offset, store_regs_sensor_##offset);
1034
1035 sysfs_sensor(1);
1036 sysfs_sensor(2);
1037 sysfs_sensor(3);
1038
1039 static ssize_t show_name(struct device *dev, struct device_attribute
1040 *devattr, char *buf)
1041 {
1042 struct w83627hf_data *data = dev_get_drvdata(dev);
1043
1044 return sprintf(buf, "%s\n", data->name);
1045 }
1046 static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
1047
1048 static int __init w83627hf_find(int sioaddr, unsigned short *addr,
1049 struct w83627hf_sio_data *sio_data)
1050 {
1051 int err = -ENODEV;
1052 u16 val;
1053
1054 static const __initdata char *names[] = {
1055 "W83627HF",
1056 "W83627THF",
1057 "W83697HF",
1058 "W83637HF",
1059 "W83687THF",
1060 };
1061
1062 REG = sioaddr;
1063 VAL = sioaddr + 1;
1064
1065 superio_enter();
1066 val= superio_inb(DEVID);
1067 switch (val) {
1068 case W627_DEVID:
1069 sio_data->type = w83627hf;
1070 break;
1071 case W627THF_DEVID:
1072 sio_data->type = w83627thf;
1073 break;
1074 case W697_DEVID:
1075 sio_data->type = w83697hf;
1076 break;
1077 case W637_DEVID:
1078 sio_data->type = w83637hf;
1079 break;
1080 case W687THF_DEVID:
1081 sio_data->type = w83687thf;
1082 break;
1083 case 0xff: /* No device at all */
1084 goto exit;
1085 default:
1086 pr_debug(DRVNAME ": Unsupported chip (DEVID=0x%02x)\n", val);
1087 goto exit;
1088 }
1089
1090 superio_select(W83627HF_LD_HWM);
1091 force_addr &= WINB_ALIGNMENT;
1092 if (force_addr) {
1093 printk(KERN_WARNING DRVNAME ": Forcing address 0x%x\n",
1094 force_addr);
1095 superio_outb(WINB_BASE_REG, force_addr >> 8);
1096 superio_outb(WINB_BASE_REG + 1, force_addr & 0xff);
1097 }
1098 val = (superio_inb(WINB_BASE_REG) << 8) |
1099 superio_inb(WINB_BASE_REG + 1);
1100 *addr = val & WINB_ALIGNMENT;
1101 if (*addr == 0) {
1102 printk(KERN_WARNING DRVNAME ": Base address not set, "
1103 "skipping\n");
1104 goto exit;
1105 }
1106
1107 val = superio_inb(WINB_ACT_REG);
1108 if (!(val & 0x01)) {
1109 printk(KERN_WARNING DRVNAME ": Enabling HWM logical device\n");
1110 superio_outb(WINB_ACT_REG, val | 0x01);
1111 }
1112
1113 err = 0;
1114 pr_info(DRVNAME ": Found %s chip at %#x\n",
1115 names[sio_data->type], *addr);
1116
1117 exit:
1118 superio_exit();
1119 return err;
1120 }
1121
1122 static struct attribute *w83627hf_attributes[] = {
1123 &dev_attr_in0_input.attr,
1124 &dev_attr_in0_min.attr,
1125 &dev_attr_in0_max.attr,
1126 &dev_attr_in2_input.attr,
1127 &dev_attr_in2_min.attr,
1128 &dev_attr_in2_max.attr,
1129 &dev_attr_in3_input.attr,
1130 &dev_attr_in3_min.attr,
1131 &dev_attr_in3_max.attr,
1132 &dev_attr_in4_input.attr,
1133 &dev_attr_in4_min.attr,
1134 &dev_attr_in4_max.attr,
1135 &dev_attr_in7_input.attr,
1136 &dev_attr_in7_min.attr,
1137 &dev_attr_in7_max.attr,
1138 &dev_attr_in8_input.attr,
1139 &dev_attr_in8_min.attr,
1140 &dev_attr_in8_max.attr,
1141
1142 &dev_attr_fan1_input.attr,
1143 &dev_attr_fan1_min.attr,
1144 &dev_attr_fan1_div.attr,
1145 &dev_attr_fan2_input.attr,
1146 &dev_attr_fan2_min.attr,
1147 &dev_attr_fan2_div.attr,
1148
1149 &dev_attr_temp1_input.attr,
1150 &dev_attr_temp1_max.attr,
1151 &dev_attr_temp1_max_hyst.attr,
1152 &dev_attr_temp1_type.attr,
1153 &dev_attr_temp2_input.attr,
1154 &dev_attr_temp2_max.attr,
1155 &dev_attr_temp2_max_hyst.attr,
1156 &dev_attr_temp2_type.attr,
1157
1158 &dev_attr_alarms.attr,
1159 &dev_attr_beep_enable.attr,
1160 &dev_attr_beep_mask.attr,
1161
1162 &dev_attr_pwm1.attr,
1163 &dev_attr_pwm2.attr,
1164
1165 &dev_attr_name.attr,
1166 NULL
1167 };
1168
1169 static const struct attribute_group w83627hf_group = {
1170 .attrs = w83627hf_attributes,
1171 };
1172
1173 static struct attribute *w83627hf_attributes_opt[] = {
1174 &dev_attr_in1_input.attr,
1175 &dev_attr_in1_min.attr,
1176 &dev_attr_in1_max.attr,
1177 &dev_attr_in5_input.attr,
1178 &dev_attr_in5_min.attr,
1179 &dev_attr_in5_max.attr,
1180 &dev_attr_in6_input.attr,
1181 &dev_attr_in6_min.attr,
1182 &dev_attr_in6_max.attr,
1183
1184 &dev_attr_fan3_input.attr,
1185 &dev_attr_fan3_min.attr,
1186 &dev_attr_fan3_div.attr,
1187
1188 &dev_attr_temp3_input.attr,
1189 &dev_attr_temp3_max.attr,
1190 &dev_attr_temp3_max_hyst.attr,
1191 &dev_attr_temp3_type.attr,
1192
1193 &dev_attr_pwm3.attr,
1194
1195 &dev_attr_pwm1_freq.attr,
1196 &dev_attr_pwm2_freq.attr,
1197 &dev_attr_pwm3_freq.attr,
1198 NULL
1199 };
1200
1201 static const struct attribute_group w83627hf_group_opt = {
1202 .attrs = w83627hf_attributes_opt,
1203 };
1204
1205 static int __devinit w83627hf_probe(struct platform_device *pdev)
1206 {
1207 struct device *dev = &pdev->dev;
1208 struct w83627hf_sio_data *sio_data = dev->platform_data;
1209 struct w83627hf_data *data;
1210 struct resource *res;
1211 int err;
1212
1213 static const char *names[] = {
1214 "w83627hf",
1215 "w83627thf",
1216 "w83697hf",
1217 "w83637hf",
1218 "w83687thf",
1219 };
1220
1221 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1222 if (!request_region(res->start, WINB_REGION_SIZE, DRVNAME)) {
1223 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
1224 (unsigned long)res->start,
1225 (unsigned long)(res->start + WINB_REGION_SIZE - 1));
1226 err = -EBUSY;
1227 goto ERROR0;
1228 }
1229
1230 if (!(data = kzalloc(sizeof(struct w83627hf_data), GFP_KERNEL))) {
1231 err = -ENOMEM;
1232 goto ERROR1;
1233 }
1234 data->addr = res->start;
1235 data->type = sio_data->type;
1236 data->name = names[sio_data->type];
1237 mutex_init(&data->lock);
1238 mutex_init(&data->update_lock);
1239 platform_set_drvdata(pdev, data);
1240
1241 /* Initialize the chip */
1242 w83627hf_init_device(pdev);
1243
1244 /* A few vars need to be filled upon startup */
1245 data->fan_min[0] = w83627hf_read_value(data, W83781D_REG_FAN_MIN(1));
1246 data->fan_min[1] = w83627hf_read_value(data, W83781D_REG_FAN_MIN(2));
1247 data->fan_min[2] = w83627hf_read_value(data, W83781D_REG_FAN_MIN(3));
1248
1249 /* Register common device attributes */
1250 if ((err = sysfs_create_group(&dev->kobj, &w83627hf_group)))
1251 goto ERROR3;
1252
1253 /* Register chip-specific device attributes */
1254 if (data->type == w83627hf || data->type == w83697hf)
1255 if ((err = device_create_file(dev, &dev_attr_in5_input))
1256 || (err = device_create_file(dev, &dev_attr_in5_min))
1257 || (err = device_create_file(dev, &dev_attr_in5_max))
1258 || (err = device_create_file(dev, &dev_attr_in6_input))
1259 || (err = device_create_file(dev, &dev_attr_in6_min))
1260 || (err = device_create_file(dev, &dev_attr_in6_max))
1261 || (err = device_create_file(dev, &dev_attr_pwm1_freq))
1262 || (err = device_create_file(dev, &dev_attr_pwm2_freq)))
1263 goto ERROR4;
1264
1265 if (data->type != w83697hf)
1266 if ((err = device_create_file(dev, &dev_attr_in1_input))
1267 || (err = device_create_file(dev, &dev_attr_in1_min))
1268 || (err = device_create_file(dev, &dev_attr_in1_max))
1269 || (err = device_create_file(dev, &dev_attr_fan3_input))
1270 || (err = device_create_file(dev, &dev_attr_fan3_min))
1271 || (err = device_create_file(dev, &dev_attr_fan3_div))
1272 || (err = device_create_file(dev, &dev_attr_temp3_input))
1273 || (err = device_create_file(dev, &dev_attr_temp3_max))
1274 || (err = device_create_file(dev, &dev_attr_temp3_max_hyst))
1275 || (err = device_create_file(dev, &dev_attr_temp3_type)))
1276 goto ERROR4;
1277
1278 if (data->type != w83697hf && data->vid != 0xff) {
1279 /* Convert VID to voltage based on VRM */
1280 data->vrm = vid_which_vrm();
1281
1282 if ((err = device_create_file(dev, &dev_attr_cpu0_vid))
1283 || (err = device_create_file(dev, &dev_attr_vrm)))
1284 goto ERROR4;
1285 }
1286
1287 if (data->type == w83627thf || data->type == w83637hf
1288 || data->type == w83687thf)
1289 if ((err = device_create_file(dev, &dev_attr_pwm3)))
1290 goto ERROR4;
1291
1292 if (data->type == w83637hf || data->type == w83687thf)
1293 if ((err = device_create_file(dev, &dev_attr_pwm1_freq))
1294 || (err = device_create_file(dev, &dev_attr_pwm2_freq))
1295 || (err = device_create_file(dev, &dev_attr_pwm3_freq)))
1296 goto ERROR4;
1297
1298 data->hwmon_dev = hwmon_device_register(dev);
1299 if (IS_ERR(data->hwmon_dev)) {
1300 err = PTR_ERR(data->hwmon_dev);
1301 goto ERROR4;
1302 }
1303
1304 return 0;
1305
1306 ERROR4:
1307 sysfs_remove_group(&dev->kobj, &w83627hf_group);
1308 sysfs_remove_group(&dev->kobj, &w83627hf_group_opt);
1309 ERROR3:
1310 platform_set_drvdata(pdev, NULL);
1311 kfree(data);
1312 ERROR1:
1313 release_region(res->start, WINB_REGION_SIZE);
1314 ERROR0:
1315 return err;
1316 }
1317
1318 static int __devexit w83627hf_remove(struct platform_device *pdev)
1319 {
1320 struct w83627hf_data *data = platform_get_drvdata(pdev);
1321 struct resource *res;
1322
1323 hwmon_device_unregister(data->hwmon_dev);
1324
1325 sysfs_remove_group(&pdev->dev.kobj, &w83627hf_group);
1326 sysfs_remove_group(&pdev->dev.kobj, &w83627hf_group_opt);
1327 platform_set_drvdata(pdev, NULL);
1328 kfree(data);
1329
1330 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1331 release_region(res->start, WINB_REGION_SIZE);
1332
1333 return 0;
1334 }
1335
1336
1337 static int w83627hf_read_value(struct w83627hf_data *data, u16 reg)
1338 {
1339 int res, word_sized;
1340
1341 mutex_lock(&data->lock);
1342 word_sized = (((reg & 0xff00) == 0x100)
1343 || ((reg & 0xff00) == 0x200))
1344 && (((reg & 0x00ff) == 0x50)
1345 || ((reg & 0x00ff) == 0x53)
1346 || ((reg & 0x00ff) == 0x55));
1347 if (reg & 0xff00) {
1348 outb_p(W83781D_REG_BANK,
1349 data->addr + W83781D_ADDR_REG_OFFSET);
1350 outb_p(reg >> 8,
1351 data->addr + W83781D_DATA_REG_OFFSET);
1352 }
1353 outb_p(reg & 0xff, data->addr + W83781D_ADDR_REG_OFFSET);
1354 res = inb_p(data->addr + W83781D_DATA_REG_OFFSET);
1355 if (word_sized) {
1356 outb_p((reg & 0xff) + 1,
1357 data->addr + W83781D_ADDR_REG_OFFSET);
1358 res =
1359 (res << 8) + inb_p(data->addr +
1360 W83781D_DATA_REG_OFFSET);
1361 }
1362 if (reg & 0xff00) {
1363 outb_p(W83781D_REG_BANK,
1364 data->addr + W83781D_ADDR_REG_OFFSET);
1365 outb_p(0, data->addr + W83781D_DATA_REG_OFFSET);
1366 }
1367 mutex_unlock(&data->lock);
1368 return res;
1369 }
1370
1371 static int __devinit w83627thf_read_gpio5(struct platform_device *pdev)
1372 {
1373 int res = 0xff, sel;
1374
1375 superio_enter();
1376 superio_select(W83627HF_LD_GPIO5);
1377
1378 /* Make sure these GPIO pins are enabled */
1379 if (!(superio_inb(W83627THF_GPIO5_EN) & (1<<3))) {
1380 dev_dbg(&pdev->dev, "GPIO5 disabled, no VID function\n");
1381 goto exit;
1382 }
1383
1384 /* Make sure the pins are configured for input
1385 There must be at least five (VRM 9), and possibly 6 (VRM 10) */
1386 sel = superio_inb(W83627THF_GPIO5_IOSR) & 0x3f;
1387 if ((sel & 0x1f) != 0x1f) {
1388 dev_dbg(&pdev->dev, "GPIO5 not configured for VID "
1389 "function\n");
1390 goto exit;
1391 }
1392
1393 dev_info(&pdev->dev, "Reading VID from GPIO5\n");
1394 res = superio_inb(W83627THF_GPIO5_DR) & sel;
1395
1396 exit:
1397 superio_exit();
1398 return res;
1399 }
1400
1401 static int __devinit w83687thf_read_vid(struct platform_device *pdev)
1402 {
1403 int res = 0xff;
1404
1405 superio_enter();
1406 superio_select(W83627HF_LD_HWM);
1407
1408 /* Make sure these GPIO pins are enabled */
1409 if (!(superio_inb(W83687THF_VID_EN) & (1 << 2))) {
1410 dev_dbg(&pdev->dev, "VID disabled, no VID function\n");
1411 goto exit;
1412 }
1413
1414 /* Make sure the pins are configured for input */
1415 if (!(superio_inb(W83687THF_VID_CFG) & (1 << 4))) {
1416 dev_dbg(&pdev->dev, "VID configured as output, "
1417 "no VID function\n");
1418 goto exit;
1419 }
1420
1421 res = superio_inb(W83687THF_VID_DATA) & 0x3f;
1422
1423 exit:
1424 superio_exit();
1425 return res;
1426 }
1427
1428 static int w83627hf_write_value(struct w83627hf_data *data, u16 reg, u16 value)
1429 {
1430 int word_sized;
1431
1432 mutex_lock(&data->lock);
1433 word_sized = (((reg & 0xff00) == 0x100)
1434 || ((reg & 0xff00) == 0x200))
1435 && (((reg & 0x00ff) == 0x53)
1436 || ((reg & 0x00ff) == 0x55));
1437 if (reg & 0xff00) {
1438 outb_p(W83781D_REG_BANK,
1439 data->addr + W83781D_ADDR_REG_OFFSET);
1440 outb_p(reg >> 8,
1441 data->addr + W83781D_DATA_REG_OFFSET);
1442 }
1443 outb_p(reg & 0xff, data->addr + W83781D_ADDR_REG_OFFSET);
1444 if (word_sized) {
1445 outb_p(value >> 8,
1446 data->addr + W83781D_DATA_REG_OFFSET);
1447 outb_p((reg & 0xff) + 1,
1448 data->addr + W83781D_ADDR_REG_OFFSET);
1449 }
1450 outb_p(value & 0xff,
1451 data->addr + W83781D_DATA_REG_OFFSET);
1452 if (reg & 0xff00) {
1453 outb_p(W83781D_REG_BANK,
1454 data->addr + W83781D_ADDR_REG_OFFSET);
1455 outb_p(0, data->addr + W83781D_DATA_REG_OFFSET);
1456 }
1457 mutex_unlock(&data->lock);
1458 return 0;
1459 }
1460
1461 static void __devinit w83627hf_init_device(struct platform_device *pdev)
1462 {
1463 struct w83627hf_data *data = platform_get_drvdata(pdev);
1464 int i;
1465 enum chips type = data->type;
1466 u8 tmp;
1467
1468 if (reset) {
1469 /* Resetting the chip has been the default for a long time,
1470 but repeatedly caused problems (fans going to full
1471 speed...) so it is now optional. It might even go away if
1472 nobody reports it as being useful, as I see very little
1473 reason why this would be needed at all. */
1474 dev_info(&pdev->dev, "If reset=1 solved a problem you were "
1475 "having, please report!\n");
1476
1477 /* save this register */
1478 i = w83627hf_read_value(data, W83781D_REG_BEEP_CONFIG);
1479 /* Reset all except Watchdog values and last conversion values
1480 This sets fan-divs to 2, among others */
1481 w83627hf_write_value(data, W83781D_REG_CONFIG, 0x80);
1482 /* Restore the register and disable power-on abnormal beep.
1483 This saves FAN 1/2/3 input/output values set by BIOS. */
1484 w83627hf_write_value(data, W83781D_REG_BEEP_CONFIG, i | 0x80);
1485 /* Disable master beep-enable (reset turns it on).
1486 Individual beeps should be reset to off but for some reason
1487 disabling this bit helps some people not get beeped */
1488 w83627hf_write_value(data, W83781D_REG_BEEP_INTS2, 0);
1489 }
1490
1491 /* Minimize conflicts with other winbond i2c-only clients... */
1492 /* disable i2c subclients... how to disable main i2c client?? */
1493 /* force i2c address to relatively uncommon address */
1494 w83627hf_write_value(data, W83781D_REG_I2C_SUBADDR, 0x89);
1495 w83627hf_write_value(data, W83781D_REG_I2C_ADDR, force_i2c);
1496
1497 /* Read VID only once */
1498 if (type == w83627hf || type == w83637hf) {
1499 int lo = w83627hf_read_value(data, W83781D_REG_VID_FANDIV);
1500 int hi = w83627hf_read_value(data, W83781D_REG_CHIPID);
1501 data->vid = (lo & 0x0f) | ((hi & 0x01) << 4);
1502 } else if (type == w83627thf) {
1503 data->vid = w83627thf_read_gpio5(pdev);
1504 } else if (type == w83687thf) {
1505 data->vid = w83687thf_read_vid(pdev);
1506 }
1507
1508 /* Read VRM & OVT Config only once */
1509 if (type == w83627thf || type == w83637hf || type == w83687thf) {
1510 data->vrm_ovt =
1511 w83627hf_read_value(data, W83627THF_REG_VRM_OVT_CFG);
1512 }
1513
1514 tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);
1515 for (i = 1; i <= 3; i++) {
1516 if (!(tmp & BIT_SCFG1[i - 1])) {
1517 data->sens[i - 1] = 4;
1518 } else {
1519 if (w83627hf_read_value
1520 (data,
1521 W83781D_REG_SCFG2) & BIT_SCFG2[i - 1])
1522 data->sens[i - 1] = 1;
1523 else
1524 data->sens[i - 1] = 2;
1525 }
1526 if ((type == w83697hf) && (i == 2))
1527 break;
1528 }
1529
1530 if(init) {
1531 /* Enable temp2 */
1532 tmp = w83627hf_read_value(data, W83781D_REG_TEMP2_CONFIG);
1533 if (tmp & 0x01) {
1534 dev_warn(&pdev->dev, "Enabling temp2, readings "
1535 "might not make sense\n");
1536 w83627hf_write_value(data, W83781D_REG_TEMP2_CONFIG,
1537 tmp & 0xfe);
1538 }
1539
1540 /* Enable temp3 */
1541 if (type != w83697hf) {
1542 tmp = w83627hf_read_value(data,
1543 W83781D_REG_TEMP3_CONFIG);
1544 if (tmp & 0x01) {
1545 dev_warn(&pdev->dev, "Enabling temp3, "
1546 "readings might not make sense\n");
1547 w83627hf_write_value(data,
1548 W83781D_REG_TEMP3_CONFIG, tmp & 0xfe);
1549 }
1550 }
1551 }
1552
1553 /* Start monitoring */
1554 w83627hf_write_value(data, W83781D_REG_CONFIG,
1555 (w83627hf_read_value(data,
1556 W83781D_REG_CONFIG) & 0xf7)
1557 | 0x01);
1558 }
1559
1560 static struct w83627hf_data *w83627hf_update_device(struct device *dev)
1561 {
1562 struct w83627hf_data *data = dev_get_drvdata(dev);
1563 int i;
1564
1565 mutex_lock(&data->update_lock);
1566
1567 if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
1568 || !data->valid) {
1569 for (i = 0; i <= 8; i++) {
1570 /* skip missing sensors */
1571 if (((data->type == w83697hf) && (i == 1)) ||
1572 ((data->type != w83627hf && data->type != w83697hf)
1573 && (i == 5 || i == 6)))
1574 continue;
1575 data->in[i] =
1576 w83627hf_read_value(data, W83781D_REG_IN(i));
1577 data->in_min[i] =
1578 w83627hf_read_value(data,
1579 W83781D_REG_IN_MIN(i));
1580 data->in_max[i] =
1581 w83627hf_read_value(data,
1582 W83781D_REG_IN_MAX(i));
1583 }
1584 for (i = 1; i <= 3; i++) {
1585 data->fan[i - 1] =
1586 w83627hf_read_value(data, W83781D_REG_FAN(i));
1587 data->fan_min[i - 1] =
1588 w83627hf_read_value(data,
1589 W83781D_REG_FAN_MIN(i));
1590 }
1591 for (i = 1; i <= 3; i++) {
1592 u8 tmp = w83627hf_read_value(data,
1593 W836X7HF_REG_PWM(data->type, i));
1594 /* bits 0-3 are reserved in 627THF */
1595 if (data->type == w83627thf)
1596 tmp &= 0xf0;
1597 data->pwm[i - 1] = tmp;
1598 if(i == 2 &&
1599 (data->type == w83627hf || data->type == w83697hf))
1600 break;
1601 }
1602 if (data->type == w83627hf) {
1603 u8 tmp = w83627hf_read_value(data,
1604 W83627HF_REG_PWM_FREQ);
1605 data->pwm_freq[0] = tmp & 0x07;
1606 data->pwm_freq[1] = (tmp >> 4) & 0x07;
1607 } else if (data->type != w83627thf) {
1608 for (i = 1; i <= 3; i++) {
1609 data->pwm_freq[i - 1] =
1610 w83627hf_read_value(data,
1611 W83637HF_REG_PWM_FREQ[i - 1]);
1612 if (i == 2 && (data->type == w83697hf))
1613 break;
1614 }
1615 }
1616
1617 data->temp = w83627hf_read_value(data, W83781D_REG_TEMP(1));
1618 data->temp_max =
1619 w83627hf_read_value(data, W83781D_REG_TEMP_OVER(1));
1620 data->temp_max_hyst =
1621 w83627hf_read_value(data, W83781D_REG_TEMP_HYST(1));
1622 data->temp_add[0] =
1623 w83627hf_read_value(data, W83781D_REG_TEMP(2));
1624 data->temp_max_add[0] =
1625 w83627hf_read_value(data, W83781D_REG_TEMP_OVER(2));
1626 data->temp_max_hyst_add[0] =
1627 w83627hf_read_value(data, W83781D_REG_TEMP_HYST(2));
1628 if (data->type != w83697hf) {
1629 data->temp_add[1] =
1630 w83627hf_read_value(data, W83781D_REG_TEMP(3));
1631 data->temp_max_add[1] =
1632 w83627hf_read_value(data, W83781D_REG_TEMP_OVER(3));
1633 data->temp_max_hyst_add[1] =
1634 w83627hf_read_value(data, W83781D_REG_TEMP_HYST(3));
1635 }
1636
1637 i = w83627hf_read_value(data, W83781D_REG_VID_FANDIV);
1638 data->fan_div[0] = (i >> 4) & 0x03;
1639 data->fan_div[1] = (i >> 6) & 0x03;
1640 if (data->type != w83697hf) {
1641 data->fan_div[2] = (w83627hf_read_value(data,
1642 W83781D_REG_PIN) >> 6) & 0x03;
1643 }
1644 i = w83627hf_read_value(data, W83781D_REG_VBAT);
1645 data->fan_div[0] |= (i >> 3) & 0x04;
1646 data->fan_div[1] |= (i >> 4) & 0x04;
1647 if (data->type != w83697hf)
1648 data->fan_div[2] |= (i >> 5) & 0x04;
1649 data->alarms =
1650 w83627hf_read_value(data, W83781D_REG_ALARM1) |
1651 (w83627hf_read_value(data, W83781D_REG_ALARM2) << 8) |
1652 (w83627hf_read_value(data, W83781D_REG_ALARM3) << 16);
1653 i = w83627hf_read_value(data, W83781D_REG_BEEP_INTS2);
1654 data->beep_enable = i >> 7;
1655 data->beep_mask = ((i & 0x7f) << 8) |
1656 w83627hf_read_value(data, W83781D_REG_BEEP_INTS1) |
1657 w83627hf_read_value(data, W83781D_REG_BEEP_INTS3) << 16;
1658 data->last_updated = jiffies;
1659 data->valid = 1;
1660 }
1661
1662 mutex_unlock(&data->update_lock);
1663
1664 return data;
1665 }
1666
1667 static int __init w83627hf_device_add(unsigned short address,
1668 const struct w83627hf_sio_data *sio_data)
1669 {
1670 struct resource res = {
1671 .start = address + WINB_REGION_OFFSET,
1672 .end = address + WINB_REGION_OFFSET + WINB_REGION_SIZE - 1,
1673 .name = DRVNAME,
1674 .flags = IORESOURCE_IO,
1675 };
1676 int err;
1677
1678 pdev = platform_device_alloc(DRVNAME, address);
1679 if (!pdev) {
1680 err = -ENOMEM;
1681 printk(KERN_ERR DRVNAME ": Device allocation failed\n");
1682 goto exit;
1683 }
1684
1685 err = platform_device_add_resources(pdev, &res, 1);
1686 if (err) {
1687 printk(KERN_ERR DRVNAME ": Device resource addition failed "
1688 "(%d)\n", err);
1689 goto exit_device_put;
1690 }
1691
1692 err = platform_device_add_data(pdev, sio_data,
1693 sizeof(struct w83627hf_sio_data));
1694 if (err) {
1695 printk(KERN_ERR DRVNAME ": Platform data allocation failed\n");
1696 goto exit_device_put;
1697 }
1698
1699 err = platform_device_add(pdev);
1700 if (err) {
1701 printk(KERN_ERR DRVNAME ": Device addition failed (%d)\n",
1702 err);
1703 goto exit_device_put;
1704 }
1705
1706 return 0;
1707
1708 exit_device_put:
1709 platform_device_put(pdev);
1710 exit:
1711 return err;
1712 }
1713
1714 static int __init sensors_w83627hf_init(void)
1715 {
1716 int err;
1717 unsigned short address;
1718 struct w83627hf_sio_data sio_data;
1719
1720 if (w83627hf_find(0x2e, &address, &sio_data)
1721 && w83627hf_find(0x4e, &address, &sio_data))
1722 return -ENODEV;
1723
1724 err = platform_driver_register(&w83627hf_driver);
1725 if (err)
1726 goto exit;
1727
1728 /* Sets global pdev as a side effect */
1729 err = w83627hf_device_add(address, &sio_data);
1730 if (err)
1731 goto exit_driver;
1732
1733 return 0;
1734
1735 exit_driver:
1736 platform_driver_unregister(&w83627hf_driver);
1737 exit:
1738 return err;
1739 }
1740
1741 static void __exit sensors_w83627hf_exit(void)
1742 {
1743 platform_device_unregister(pdev);
1744 platform_driver_unregister(&w83627hf_driver);
1745 }
1746
1747 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>, "
1748 "Philip Edelbrock <phil@netroedge.com>, "
1749 "and Mark Studebaker <mdsxyz123@yahoo.com>");
1750 MODULE_DESCRIPTION("W83627HF driver");
1751 MODULE_LICENSE("GPL");
1752
1753 module_init(sensors_w83627hf_init);
1754 module_exit(sensors_w83627hf_exit);
Linux kernel - Deliverables
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