1 /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <linux/kernel.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/types.h>
17 #include <linux/device.h>
19 #include <linux/err.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/smp.h>
24 #include <linux/sysfs.h>
25 #include <linux/stat.h>
26 #include <linux/clk.h>
27 #include <linux/cpu.h>
28 #include <linux/coresight.h>
29 #include <linux/pm_wakeup.h>
30 #include <linux/amba/bus.h>
31 #include <linux/seq_file.h>
32 #include <linux/uaccess.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/perf_event.h>
35 #include <asm/sections.h>
37 #include "coresight-etm4x.h"
39 static int boot_enable
;
40 module_param_named(boot_enable
, boot_enable
, int, S_IRUGO
);
42 /* The number of ETMv4 currently registered */
43 static int etm4_count
;
44 static struct etmv4_drvdata
*etmdrvdata
[NR_CPUS
];
46 static void etm4_os_unlock(void *info
)
48 struct etmv4_drvdata
*drvdata
= (struct etmv4_drvdata
*)info
;
50 /* Writing any value to ETMOSLAR unlocks the trace registers */
51 writel_relaxed(0x0, drvdata
->base
+ TRCOSLAR
);
55 static bool etm4_arch_supported(u8 arch
)
66 static int etm4_cpu_id(struct coresight_device
*csdev
)
68 struct etmv4_drvdata
*drvdata
= dev_get_drvdata(csdev
->dev
.parent
);
73 static int etm4_trace_id(struct coresight_device
*csdev
)
75 struct etmv4_drvdata
*drvdata
= dev_get_drvdata(csdev
->dev
.parent
);
80 return drvdata
->trcid
;
82 spin_lock_irqsave(&drvdata
->spinlock
, flags
);
84 CS_UNLOCK(drvdata
->base
);
85 trace_id
= readl_relaxed(drvdata
->base
+ TRCTRACEIDR
);
86 trace_id
&= ETM_TRACEID_MASK
;
87 CS_LOCK(drvdata
->base
);
89 spin_unlock_irqrestore(&drvdata
->spinlock
, flags
);
94 static void etm4_enable_hw(void *info
)
97 struct etmv4_drvdata
*drvdata
= info
;
99 CS_UNLOCK(drvdata
->base
);
101 etm4_os_unlock(drvdata
);
103 /* Disable the trace unit before programming trace registers */
104 writel_relaxed(0, drvdata
->base
+ TRCPRGCTLR
);
106 /* wait for TRCSTATR.IDLE to go up */
107 if (coresight_timeout(drvdata
->base
, TRCSTATR
, TRCSTATR_IDLE_BIT
, 1))
108 dev_err(drvdata
->dev
,
109 "timeout observed when probing at offset %#x\n",
112 writel_relaxed(drvdata
->pe_sel
, drvdata
->base
+ TRCPROCSELR
);
113 writel_relaxed(drvdata
->cfg
, drvdata
->base
+ TRCCONFIGR
);
114 /* nothing specific implemented */
115 writel_relaxed(0x0, drvdata
->base
+ TRCAUXCTLR
);
116 writel_relaxed(drvdata
->eventctrl0
, drvdata
->base
+ TRCEVENTCTL0R
);
117 writel_relaxed(drvdata
->eventctrl1
, drvdata
->base
+ TRCEVENTCTL1R
);
118 writel_relaxed(drvdata
->stall_ctrl
, drvdata
->base
+ TRCSTALLCTLR
);
119 writel_relaxed(drvdata
->ts_ctrl
, drvdata
->base
+ TRCTSCTLR
);
120 writel_relaxed(drvdata
->syncfreq
, drvdata
->base
+ TRCSYNCPR
);
121 writel_relaxed(drvdata
->ccctlr
, drvdata
->base
+ TRCCCCTLR
);
122 writel_relaxed(drvdata
->bb_ctrl
, drvdata
->base
+ TRCBBCTLR
);
123 writel_relaxed(drvdata
->trcid
, drvdata
->base
+ TRCTRACEIDR
);
124 writel_relaxed(drvdata
->vinst_ctrl
, drvdata
->base
+ TRCVICTLR
);
125 writel_relaxed(drvdata
->viiectlr
, drvdata
->base
+ TRCVIIECTLR
);
126 writel_relaxed(drvdata
->vissctlr
,
127 drvdata
->base
+ TRCVISSCTLR
);
128 writel_relaxed(drvdata
->vipcssctlr
,
129 drvdata
->base
+ TRCVIPCSSCTLR
);
130 for (i
= 0; i
< drvdata
->nrseqstate
- 1; i
++)
131 writel_relaxed(drvdata
->seq_ctrl
[i
],
132 drvdata
->base
+ TRCSEQEVRn(i
));
133 writel_relaxed(drvdata
->seq_rst
, drvdata
->base
+ TRCSEQRSTEVR
);
134 writel_relaxed(drvdata
->seq_state
, drvdata
->base
+ TRCSEQSTR
);
135 writel_relaxed(drvdata
->ext_inp
, drvdata
->base
+ TRCEXTINSELR
);
136 for (i
= 0; i
< drvdata
->nr_cntr
; i
++) {
137 writel_relaxed(drvdata
->cntrldvr
[i
],
138 drvdata
->base
+ TRCCNTRLDVRn(i
));
139 writel_relaxed(drvdata
->cntr_ctrl
[i
],
140 drvdata
->base
+ TRCCNTCTLRn(i
));
141 writel_relaxed(drvdata
->cntr_val
[i
],
142 drvdata
->base
+ TRCCNTVRn(i
));
145 /* Resource selector pair 0 is always implemented and reserved */
146 for (i
= 2; i
< drvdata
->nr_resource
* 2; i
++)
147 writel_relaxed(drvdata
->res_ctrl
[i
],
148 drvdata
->base
+ TRCRSCTLRn(i
));
150 for (i
= 0; i
< drvdata
->nr_ss_cmp
; i
++) {
151 writel_relaxed(drvdata
->ss_ctrl
[i
],
152 drvdata
->base
+ TRCSSCCRn(i
));
153 writel_relaxed(drvdata
->ss_status
[i
],
154 drvdata
->base
+ TRCSSCSRn(i
));
155 writel_relaxed(drvdata
->ss_pe_cmp
[i
],
156 drvdata
->base
+ TRCSSPCICRn(i
));
158 for (i
= 0; i
< drvdata
->nr_addr_cmp
; i
++) {
159 writeq_relaxed(drvdata
->addr_val
[i
],
160 drvdata
->base
+ TRCACVRn(i
));
161 writeq_relaxed(drvdata
->addr_acc
[i
],
162 drvdata
->base
+ TRCACATRn(i
));
164 for (i
= 0; i
< drvdata
->numcidc
; i
++)
165 writeq_relaxed(drvdata
->ctxid_pid
[i
],
166 drvdata
->base
+ TRCCIDCVRn(i
));
167 writel_relaxed(drvdata
->ctxid_mask0
, drvdata
->base
+ TRCCIDCCTLR0
);
168 writel_relaxed(drvdata
->ctxid_mask1
, drvdata
->base
+ TRCCIDCCTLR1
);
170 for (i
= 0; i
< drvdata
->numvmidc
; i
++)
171 writeq_relaxed(drvdata
->vmid_val
[i
],
172 drvdata
->base
+ TRCVMIDCVRn(i
));
173 writel_relaxed(drvdata
->vmid_mask0
, drvdata
->base
+ TRCVMIDCCTLR0
);
174 writel_relaxed(drvdata
->vmid_mask1
, drvdata
->base
+ TRCVMIDCCTLR1
);
176 /* Enable the trace unit */
177 writel_relaxed(1, drvdata
->base
+ TRCPRGCTLR
);
179 /* wait for TRCSTATR.IDLE to go back down to '0' */
180 if (coresight_timeout(drvdata
->base
, TRCSTATR
, TRCSTATR_IDLE_BIT
, 0))
181 dev_err(drvdata
->dev
,
182 "timeout observed when probing at offset %#x\n",
185 CS_LOCK(drvdata
->base
);
187 dev_dbg(drvdata
->dev
, "cpu: %d enable smp call done\n", drvdata
->cpu
);
190 static int etm4_enable(struct coresight_device
*csdev
,
191 struct perf_event_attr
*attr
, u32 mode
)
193 struct etmv4_drvdata
*drvdata
= dev_get_drvdata(csdev
->dev
.parent
);
196 spin_lock(&drvdata
->spinlock
);
199 * Executing etm4_enable_hw on the cpu whose ETM is being enabled
200 * ensures that register writes occur when cpu is powered.
202 ret
= smp_call_function_single(drvdata
->cpu
,
203 etm4_enable_hw
, drvdata
, 1);
206 drvdata
->enable
= true;
207 drvdata
->sticky_enable
= true;
209 spin_unlock(&drvdata
->spinlock
);
211 dev_info(drvdata
->dev
, "ETM tracing enabled\n");
214 spin_unlock(&drvdata
->spinlock
);
218 static void etm4_disable_hw(void *info
)
221 struct etmv4_drvdata
*drvdata
= info
;
223 CS_UNLOCK(drvdata
->base
);
225 control
= readl_relaxed(drvdata
->base
+ TRCPRGCTLR
);
227 /* EN, bit[0] Trace unit enable bit */
230 /* make sure everything completes before disabling */
233 writel_relaxed(control
, drvdata
->base
+ TRCPRGCTLR
);
235 CS_LOCK(drvdata
->base
);
237 dev_dbg(drvdata
->dev
, "cpu: %d disable smp call done\n", drvdata
->cpu
);
240 static void etm4_disable(struct coresight_device
*csdev
)
242 struct etmv4_drvdata
*drvdata
= dev_get_drvdata(csdev
->dev
.parent
);
245 * Taking hotplug lock here protects from clocks getting disabled
246 * with tracing being left on (crash scenario) if user disable occurs
247 * after cpu online mask indicates the cpu is offline but before the
248 * DYING hotplug callback is serviced by the ETM driver.
251 spin_lock(&drvdata
->spinlock
);
254 * Executing etm4_disable_hw on the cpu whose ETM is being disabled
255 * ensures that register writes occur when cpu is powered.
257 smp_call_function_single(drvdata
->cpu
, etm4_disable_hw
, drvdata
, 1);
258 drvdata
->enable
= false;
260 spin_unlock(&drvdata
->spinlock
);
263 dev_info(drvdata
->dev
, "ETM tracing disabled\n");
266 static const struct coresight_ops_source etm4_source_ops
= {
267 .cpu_id
= etm4_cpu_id
,
268 .trace_id
= etm4_trace_id
,
269 .enable
= etm4_enable
,
270 .disable
= etm4_disable
,
273 static const struct coresight_ops etm4_cs_ops
= {
274 .source_ops
= &etm4_source_ops
,
277 static void etm4_init_arch_data(void *info
)
285 struct etmv4_drvdata
*drvdata
= info
;
287 CS_UNLOCK(drvdata
->base
);
289 /* find all capabilities of the tracing unit */
290 etmidr0
= readl_relaxed(drvdata
->base
+ TRCIDR0
);
292 /* INSTP0, bits[2:1] P0 tracing support field */
293 if (BMVAL(etmidr0
, 1, 1) && BMVAL(etmidr0
, 2, 2))
294 drvdata
->instrp0
= true;
296 drvdata
->instrp0
= false;
298 /* TRCBB, bit[5] Branch broadcast tracing support bit */
299 if (BMVAL(etmidr0
, 5, 5))
300 drvdata
->trcbb
= true;
302 drvdata
->trcbb
= false;
304 /* TRCCOND, bit[6] Conditional instruction tracing support bit */
305 if (BMVAL(etmidr0
, 6, 6))
306 drvdata
->trccond
= true;
308 drvdata
->trccond
= false;
310 /* TRCCCI, bit[7] Cycle counting instruction bit */
311 if (BMVAL(etmidr0
, 7, 7))
312 drvdata
->trccci
= true;
314 drvdata
->trccci
= false;
316 /* RETSTACK, bit[9] Return stack bit */
317 if (BMVAL(etmidr0
, 9, 9))
318 drvdata
->retstack
= true;
320 drvdata
->retstack
= false;
322 /* NUMEVENT, bits[11:10] Number of events field */
323 drvdata
->nr_event
= BMVAL(etmidr0
, 10, 11);
324 /* QSUPP, bits[16:15] Q element support field */
325 drvdata
->q_support
= BMVAL(etmidr0
, 15, 16);
326 /* TSSIZE, bits[28:24] Global timestamp size field */
327 drvdata
->ts_size
= BMVAL(etmidr0
, 24, 28);
329 /* base architecture of trace unit */
330 etmidr1
= readl_relaxed(drvdata
->base
+ TRCIDR1
);
332 * TRCARCHMIN, bits[7:4] architecture the minor version number
333 * TRCARCHMAJ, bits[11:8] architecture major versin number
335 drvdata
->arch
= BMVAL(etmidr1
, 4, 11);
337 /* maximum size of resources */
338 etmidr2
= readl_relaxed(drvdata
->base
+ TRCIDR2
);
339 /* CIDSIZE, bits[9:5] Indicates the Context ID size */
340 drvdata
->ctxid_size
= BMVAL(etmidr2
, 5, 9);
341 /* VMIDSIZE, bits[14:10] Indicates the VMID size */
342 drvdata
->vmid_size
= BMVAL(etmidr2
, 10, 14);
343 /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
344 drvdata
->ccsize
= BMVAL(etmidr2
, 25, 28);
346 etmidr3
= readl_relaxed(drvdata
->base
+ TRCIDR3
);
347 /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
348 drvdata
->ccitmin
= BMVAL(etmidr3
, 0, 11);
349 /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
350 drvdata
->s_ex_level
= BMVAL(etmidr3
, 16, 19);
351 /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
352 drvdata
->ns_ex_level
= BMVAL(etmidr3
, 20, 23);
355 * TRCERR, bit[24] whether a trace unit can trace a
356 * system error exception.
358 if (BMVAL(etmidr3
, 24, 24))
359 drvdata
->trc_error
= true;
361 drvdata
->trc_error
= false;
363 /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
364 if (BMVAL(etmidr3
, 25, 25))
365 drvdata
->syncpr
= true;
367 drvdata
->syncpr
= false;
369 /* STALLCTL, bit[26] is stall control implemented? */
370 if (BMVAL(etmidr3
, 26, 26))
371 drvdata
->stallctl
= true;
373 drvdata
->stallctl
= false;
375 /* SYSSTALL, bit[27] implementation can support stall control? */
376 if (BMVAL(etmidr3
, 27, 27))
377 drvdata
->sysstall
= true;
379 drvdata
->sysstall
= false;
381 /* NUMPROC, bits[30:28] the number of PEs available for tracing */
382 drvdata
->nr_pe
= BMVAL(etmidr3
, 28, 30);
384 /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
385 if (BMVAL(etmidr3
, 31, 31))
386 drvdata
->nooverflow
= true;
388 drvdata
->nooverflow
= false;
390 /* number of resources trace unit supports */
391 etmidr4
= readl_relaxed(drvdata
->base
+ TRCIDR4
);
392 /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
393 drvdata
->nr_addr_cmp
= BMVAL(etmidr4
, 0, 3);
394 /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
395 drvdata
->nr_pe_cmp
= BMVAL(etmidr4
, 12, 15);
397 * NUMRSPAIR, bits[19:16]
398 * The number of resource pairs conveyed by the HW starts at 0, i.e a
399 * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
400 * As such add 1 to the value of NUMRSPAIR for a better representation.
402 drvdata
->nr_resource
= BMVAL(etmidr4
, 16, 19) + 1;
404 * NUMSSCC, bits[23:20] the number of single-shot
405 * comparator control for tracing
407 drvdata
->nr_ss_cmp
= BMVAL(etmidr4
, 20, 23);
408 /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
409 drvdata
->numcidc
= BMVAL(etmidr4
, 24, 27);
410 /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
411 drvdata
->numvmidc
= BMVAL(etmidr4
, 28, 31);
413 etmidr5
= readl_relaxed(drvdata
->base
+ TRCIDR5
);
414 /* NUMEXTIN, bits[8:0] number of external inputs implemented */
415 drvdata
->nr_ext_inp
= BMVAL(etmidr5
, 0, 8);
416 /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
417 drvdata
->trcid_size
= BMVAL(etmidr5
, 16, 21);
418 /* ATBTRIG, bit[22] implementation can support ATB triggers? */
419 if (BMVAL(etmidr5
, 22, 22))
420 drvdata
->atbtrig
= true;
422 drvdata
->atbtrig
= false;
424 * LPOVERRIDE, bit[23] implementation supports
425 * low-power state override
427 if (BMVAL(etmidr5
, 23, 23))
428 drvdata
->lpoverride
= true;
430 drvdata
->lpoverride
= false;
431 /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
432 drvdata
->nrseqstate
= BMVAL(etmidr5
, 25, 27);
433 /* NUMCNTR, bits[30:28] number of counters available for tracing */
434 drvdata
->nr_cntr
= BMVAL(etmidr5
, 28, 30);
435 CS_LOCK(drvdata
->base
);
438 static void etm4_init_default_data(struct etmv4_drvdata
*drvdata
)
442 drvdata
->pe_sel
= 0x0;
443 drvdata
->cfg
= (ETMv4_MODE_CTXID
| ETM_MODE_VMID
|
444 ETMv4_MODE_TIMESTAMP
| ETM_MODE_RETURNSTACK
);
446 /* disable all events tracing */
447 drvdata
->eventctrl0
= 0x0;
448 drvdata
->eventctrl1
= 0x0;
450 /* disable stalling */
451 drvdata
->stall_ctrl
= 0x0;
453 /* disable timestamp event */
454 drvdata
->ts_ctrl
= 0x0;
456 /* enable trace synchronization every 4096 bytes for trace */
457 if (drvdata
->syncpr
== false)
458 drvdata
->syncfreq
= 0xC;
461 * enable viewInst to trace everything with start-stop logic in
464 drvdata
->vinst_ctrl
|= BIT(0);
465 /* set initial state of start-stop logic */
466 if (drvdata
->nr_addr_cmp
)
467 drvdata
->vinst_ctrl
|= BIT(9);
469 /* no address range filtering for ViewInst */
470 drvdata
->viiectlr
= 0x0;
471 /* no start-stop filtering for ViewInst */
472 drvdata
->vissctlr
= 0x0;
474 /* disable seq events */
475 for (i
= 0; i
< drvdata
->nrseqstate
-1; i
++)
476 drvdata
->seq_ctrl
[i
] = 0x0;
477 drvdata
->seq_rst
= 0x0;
478 drvdata
->seq_state
= 0x0;
480 /* disable external input events */
481 drvdata
->ext_inp
= 0x0;
483 for (i
= 0; i
< drvdata
->nr_cntr
; i
++) {
484 drvdata
->cntrldvr
[i
] = 0x0;
485 drvdata
->cntr_ctrl
[i
] = 0x0;
486 drvdata
->cntr_val
[i
] = 0x0;
489 /* Resource selector pair 0 is always implemented and reserved */
490 drvdata
->res_idx
= 0x2;
491 for (i
= 2; i
< drvdata
->nr_resource
* 2; i
++)
492 drvdata
->res_ctrl
[i
] = 0x0;
494 for (i
= 0; i
< drvdata
->nr_ss_cmp
; i
++) {
495 drvdata
->ss_ctrl
[i
] = 0x0;
496 drvdata
->ss_pe_cmp
[i
] = 0x0;
499 if (drvdata
->nr_addr_cmp
>= 1) {
500 drvdata
->addr_val
[0] = (unsigned long)_stext
;
501 drvdata
->addr_val
[1] = (unsigned long)_etext
;
502 drvdata
->addr_type
[0] = ETM_ADDR_TYPE_RANGE
;
503 drvdata
->addr_type
[1] = ETM_ADDR_TYPE_RANGE
;
506 for (i
= 0; i
< drvdata
->numcidc
; i
++) {
507 drvdata
->ctxid_pid
[i
] = 0x0;
508 drvdata
->ctxid_vpid
[i
] = 0x0;
511 drvdata
->ctxid_mask0
= 0x0;
512 drvdata
->ctxid_mask1
= 0x0;
514 for (i
= 0; i
< drvdata
->numvmidc
; i
++)
515 drvdata
->vmid_val
[i
] = 0x0;
516 drvdata
->vmid_mask0
= 0x0;
517 drvdata
->vmid_mask1
= 0x0;
520 * A trace ID value of 0 is invalid, so let's start at some
521 * random value that fits in 7 bits. ETMv3.x has 0x10 so let's
524 drvdata
->trcid
= 0x20 + drvdata
->cpu
;
527 static int etm4_cpu_callback(struct notifier_block
*nfb
, unsigned long action
,
530 unsigned int cpu
= (unsigned long)hcpu
;
532 if (!etmdrvdata
[cpu
])
535 switch (action
& (~CPU_TASKS_FROZEN
)) {
537 spin_lock(&etmdrvdata
[cpu
]->spinlock
);
538 if (!etmdrvdata
[cpu
]->os_unlock
) {
539 etm4_os_unlock(etmdrvdata
[cpu
]);
540 etmdrvdata
[cpu
]->os_unlock
= true;
543 if (etmdrvdata
[cpu
]->enable
)
544 etm4_enable_hw(etmdrvdata
[cpu
]);
545 spin_unlock(&etmdrvdata
[cpu
]->spinlock
);
549 if (etmdrvdata
[cpu
]->boot_enable
&&
550 !etmdrvdata
[cpu
]->sticky_enable
)
551 coresight_enable(etmdrvdata
[cpu
]->csdev
);
555 spin_lock(&etmdrvdata
[cpu
]->spinlock
);
556 if (etmdrvdata
[cpu
]->enable
)
557 etm4_disable_hw(etmdrvdata
[cpu
]);
558 spin_unlock(&etmdrvdata
[cpu
]->spinlock
);
565 static struct notifier_block etm4_cpu_notifier
= {
566 .notifier_call
= etm4_cpu_callback
,
569 static int etm4_probe(struct amba_device
*adev
, const struct amba_id
*id
)
573 struct device
*dev
= &adev
->dev
;
574 struct coresight_platform_data
*pdata
= NULL
;
575 struct etmv4_drvdata
*drvdata
;
576 struct resource
*res
= &adev
->res
;
577 struct coresight_desc
*desc
;
578 struct device_node
*np
= adev
->dev
.of_node
;
580 desc
= devm_kzalloc(dev
, sizeof(*desc
), GFP_KERNEL
);
584 drvdata
= devm_kzalloc(dev
, sizeof(*drvdata
), GFP_KERNEL
);
589 pdata
= of_get_coresight_platform_data(dev
, np
);
591 return PTR_ERR(pdata
);
592 adev
->dev
.platform_data
= pdata
;
595 drvdata
->dev
= &adev
->dev
;
596 dev_set_drvdata(dev
, drvdata
);
598 /* Validity for the resource is already checked by the AMBA core */
599 base
= devm_ioremap_resource(dev
, res
);
601 return PTR_ERR(base
);
603 drvdata
->base
= base
;
605 spin_lock_init(&drvdata
->spinlock
);
607 drvdata
->cpu
= pdata
? pdata
->cpu
: 0;
610 etmdrvdata
[drvdata
->cpu
] = drvdata
;
612 if (!smp_call_function_single(drvdata
->cpu
, etm4_os_unlock
, drvdata
, 1))
613 drvdata
->os_unlock
= true;
615 if (smp_call_function_single(drvdata
->cpu
,
616 etm4_init_arch_data
, drvdata
, 1))
617 dev_err(dev
, "ETM arch init failed\n");
620 register_hotcpu_notifier(&etm4_cpu_notifier
);
624 if (etm4_arch_supported(drvdata
->arch
) == false) {
626 goto err_arch_supported
;
628 etm4_init_default_data(drvdata
);
630 pm_runtime_put(&adev
->dev
);
632 desc
->type
= CORESIGHT_DEV_TYPE_SOURCE
;
633 desc
->subtype
.source_subtype
= CORESIGHT_DEV_SUBTYPE_SOURCE_PROC
;
634 desc
->ops
= &etm4_cs_ops
;
637 desc
->groups
= coresight_etmv4_groups
;
638 drvdata
->csdev
= coresight_register(desc
);
639 if (IS_ERR(drvdata
->csdev
)) {
640 ret
= PTR_ERR(drvdata
->csdev
);
641 goto err_coresight_register
;
644 dev_info(dev
, "%s initialized\n", (char *)id
->data
);
647 coresight_enable(drvdata
->csdev
);
648 drvdata
->boot_enable
= true;
654 pm_runtime_put(&adev
->dev
);
655 err_coresight_register
:
656 if (--etm4_count
== 0)
657 unregister_hotcpu_notifier(&etm4_cpu_notifier
);
661 static struct amba_id etm4_ids
[] = {
662 { /* ETM 4.0 - Qualcomm */
667 { /* ETM 4.0 - Juno board */
675 static struct amba_driver etm4x_driver
= {
677 .name
= "coresight-etm4x",
678 .suppress_bind_attrs
= true,
681 .id_table
= etm4_ids
,
683 builtin_amba_driver(etm4x_driver
);