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[deliverable/linux.git] / drivers / hwtracing / coresight / coresight-etm4x.h
1 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13 #ifndef _CORESIGHT_CORESIGHT_ETM_H
14 #define _CORESIGHT_CORESIGHT_ETM_H
15
16 #include <linux/spinlock.h>
17 #include "coresight-priv.h"
18
19 /*
20 * Device registers:
21 * 0x000 - 0x2FC: Trace registers
22 * 0x300 - 0x314: Management registers
23 * 0x318 - 0xEFC: Trace registers
24 * 0xF00: Management registers
25 * 0xFA0 - 0xFA4: Trace registers
26 * 0xFA8 - 0xFFC: Management registers
27 */
28 /* Trace registers (0x000-0x2FC) */
29 /* Main control and configuration registers */
30 #define TRCPRGCTLR 0x004
31 #define TRCPROCSELR 0x008
32 #define TRCSTATR 0x00C
33 #define TRCCONFIGR 0x010
34 #define TRCAUXCTLR 0x018
35 #define TRCEVENTCTL0R 0x020
36 #define TRCEVENTCTL1R 0x024
37 #define TRCSTALLCTLR 0x02C
38 #define TRCTSCTLR 0x030
39 #define TRCSYNCPR 0x034
40 #define TRCCCCTLR 0x038
41 #define TRCBBCTLR 0x03C
42 #define TRCTRACEIDR 0x040
43 #define TRCQCTLR 0x044
44 /* Filtering control registers */
45 #define TRCVICTLR 0x080
46 #define TRCVIIECTLR 0x084
47 #define TRCVISSCTLR 0x088
48 #define TRCVIPCSSCTLR 0x08C
49 #define TRCVDCTLR 0x0A0
50 #define TRCVDSACCTLR 0x0A4
51 #define TRCVDARCCTLR 0x0A8
52 /* Derived resources registers */
53 #define TRCSEQEVRn(n) (0x100 + (n * 4))
54 #define TRCSEQRSTEVR 0x118
55 #define TRCSEQSTR 0x11C
56 #define TRCEXTINSELR 0x120
57 #define TRCCNTRLDVRn(n) (0x140 + (n * 4))
58 #define TRCCNTCTLRn(n) (0x150 + (n * 4))
59 #define TRCCNTVRn(n) (0x160 + (n * 4))
60 /* ID registers */
61 #define TRCIDR8 0x180
62 #define TRCIDR9 0x184
63 #define TRCIDR10 0x188
64 #define TRCIDR11 0x18C
65 #define TRCIDR12 0x190
66 #define TRCIDR13 0x194
67 #define TRCIMSPEC0 0x1C0
68 #define TRCIMSPECn(n) (0x1C0 + (n * 4))
69 #define TRCIDR0 0x1E0
70 #define TRCIDR1 0x1E4
71 #define TRCIDR2 0x1E8
72 #define TRCIDR3 0x1EC
73 #define TRCIDR4 0x1F0
74 #define TRCIDR5 0x1F4
75 #define TRCIDR6 0x1F8
76 #define TRCIDR7 0x1FC
77 /* Resource selection registers */
78 #define TRCRSCTLRn(n) (0x200 + (n * 4))
79 /* Single-shot comparator registers */
80 #define TRCSSCCRn(n) (0x280 + (n * 4))
81 #define TRCSSCSRn(n) (0x2A0 + (n * 4))
82 #define TRCSSPCICRn(n) (0x2C0 + (n * 4))
83 /* Management registers (0x300-0x314) */
84 #define TRCOSLAR 0x300
85 #define TRCOSLSR 0x304
86 #define TRCPDCR 0x310
87 #define TRCPDSR 0x314
88 /* Trace registers (0x318-0xEFC) */
89 /* Comparator registers */
90 #define TRCACVRn(n) (0x400 + (n * 8))
91 #define TRCACATRn(n) (0x480 + (n * 8))
92 #define TRCDVCVRn(n) (0x500 + (n * 16))
93 #define TRCDVCMRn(n) (0x580 + (n * 16))
94 #define TRCCIDCVRn(n) (0x600 + (n * 8))
95 #define TRCVMIDCVRn(n) (0x640 + (n * 8))
96 #define TRCCIDCCTLR0 0x680
97 #define TRCCIDCCTLR1 0x684
98 #define TRCVMIDCCTLR0 0x688
99 #define TRCVMIDCCTLR1 0x68C
100 /* Management register (0xF00) */
101 /* Integration control registers */
102 #define TRCITCTRL 0xF00
103 /* Trace registers (0xFA0-0xFA4) */
104 /* Claim tag registers */
105 #define TRCCLAIMSET 0xFA0
106 #define TRCCLAIMCLR 0xFA4
107 /* Management registers (0xFA8-0xFFC) */
108 #define TRCDEVAFF0 0xFA8
109 #define TRCDEVAFF1 0xFAC
110 #define TRCLAR 0xFB0
111 #define TRCLSR 0xFB4
112 #define TRCAUTHSTATUS 0xFB8
113 #define TRCDEVARCH 0xFBC
114 #define TRCDEVID 0xFC8
115 #define TRCDEVTYPE 0xFCC
116 #define TRCPIDR4 0xFD0
117 #define TRCPIDR5 0xFD4
118 #define TRCPIDR6 0xFD8
119 #define TRCPIDR7 0xFDC
120 #define TRCPIDR0 0xFE0
121 #define TRCPIDR1 0xFE4
122 #define TRCPIDR2 0xFE8
123 #define TRCPIDR3 0xFEC
124 #define TRCCIDR0 0xFF0
125 #define TRCCIDR1 0xFF4
126 #define TRCCIDR2 0xFF8
127 #define TRCCIDR3 0xFFC
128
129 /* ETMv4 resources */
130 #define ETM_MAX_NR_PE 8
131 #define ETMv4_MAX_CNTR 4
132 #define ETM_MAX_SEQ_STATES 4
133 #define ETM_MAX_EXT_INP_SEL 4
134 #define ETM_MAX_EXT_INP 256
135 #define ETM_MAX_EXT_OUT 4
136 #define ETM_MAX_SINGLE_ADDR_CMP 16
137 #define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2)
138 #define ETM_MAX_DATA_VAL_CMP 8
139 #define ETMv4_MAX_CTXID_CMP 8
140 #define ETM_MAX_VMID_CMP 8
141 #define ETM_MAX_PE_CMP 8
142 #define ETM_MAX_RES_SEL 16
143 #define ETM_MAX_SS_CMP 8
144
145 #define ETM_ARCH_V4 0x40
146 #define ETMv4_SYNC_MASK 0x1F
147 #define ETM_CYC_THRESHOLD_MASK 0xFFF
148 #define ETMv4_EVENT_MASK 0xFF
149 #define ETM_CNTR_MAX_VAL 0xFFFF
150 #define ETM_TRACEID_MASK 0x3f
151
152 /* ETMv4 programming modes */
153 #define ETM_MODE_EXCLUDE BIT(0)
154 #define ETM_MODE_LOAD BIT(1)
155 #define ETM_MODE_STORE BIT(2)
156 #define ETM_MODE_LOAD_STORE BIT(3)
157 #define ETM_MODE_BB BIT(4)
158 #define ETMv4_MODE_CYCACC BIT(5)
159 #define ETMv4_MODE_CTXID BIT(6)
160 #define ETM_MODE_VMID BIT(7)
161 #define ETM_MODE_COND(val) BMVAL(val, 8, 10)
162 #define ETMv4_MODE_TIMESTAMP BIT(11)
163 #define ETM_MODE_RETURNSTACK BIT(12)
164 #define ETM_MODE_QELEM(val) BMVAL(val, 13, 14)
165 #define ETM_MODE_DATA_TRACE_ADDR BIT(15)
166 #define ETM_MODE_DATA_TRACE_VAL BIT(16)
167 #define ETM_MODE_ISTALL BIT(17)
168 #define ETM_MODE_DSTALL BIT(18)
169 #define ETM_MODE_ATB_TRIGGER BIT(19)
170 #define ETM_MODE_LPOVERRIDE BIT(20)
171 #define ETM_MODE_ISTALL_EN BIT(21)
172 #define ETM_MODE_DSTALL_EN BIT(22)
173 #define ETM_MODE_INSTPRIO BIT(23)
174 #define ETM_MODE_NOOVERFLOW BIT(24)
175 #define ETM_MODE_TRACE_RESET BIT(25)
176 #define ETM_MODE_TRACE_ERR BIT(26)
177 #define ETM_MODE_VIEWINST_STARTSTOP BIT(27)
178 #define ETMv4_MODE_ALL 0xFFFFFFF
179
180 #define TRCSTATR_IDLE_BIT 0
181 #define ETM_DEFAULT_ADDR_COMP 0
182
183 /* secure state access levels */
184 #define ETM_EXLEVEL_S_APP BIT(8)
185 #define ETM_EXLEVEL_S_OS BIT(9)
186 #define ETM_EXLEVEL_S_NA BIT(10)
187 #define ETM_EXLEVEL_S_HYP BIT(11)
188 /* non-secure state access levels */
189 #define ETM_EXLEVEL_NS_APP BIT(12)
190 #define ETM_EXLEVEL_NS_OS BIT(13)
191 #define ETM_EXLEVEL_NS_HYP BIT(14)
192 #define ETM_EXLEVEL_NS_NA BIT(15)
193
194 /**
195 * struct etmv4_config - configuration information related to an ETMv4
196 * @mode: Controls various modes supported by this ETM.
197 * @pe_sel: Controls which PE to trace.
198 * @cfg: Controls the tracing options.
199 * @eventctrl0: Controls the tracing of arbitrary events.
200 * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects.
201 * @stallctl: If functionality that prevents trace unit buffer overflows
202 * is available.
203 * @ts_ctrl: Controls the insertion of global timestamps in the
204 * trace streams.
205 * @syncfreq: Controls how often trace synchronization requests occur.
206 * the TRCCCCTLR register.
207 * @ccctlr: Sets the threshold value for cycle counting.
208 * @vinst_ctrl: Controls instruction trace filtering.
209 * @viiectlr: Set or read, the address range comparators.
210 * @vissctlr: Set, or read, the single address comparators that control the
211 * ViewInst start-stop logic.
212 * @vipcssctlr: Set, or read, which PE comparator inputs can control the
213 * ViewInst start-stop logic.
214 * @seq_idx: Sequencor index selector.
215 * @seq_ctrl: Control for the sequencer state transition control register.
216 * @seq_rst: Moves the sequencer to state 0 when a programmed event occurs.
217 * @seq_state: Set, or read the sequencer state.
218 * @cntr_idx: Counter index seletor.
219 * @cntrldvr: Sets or returns the reload count value for a counter.
220 * @cntr_ctrl: Controls the operation of a counter.
221 * @cntr_val: Sets or returns the value for a counter.
222 * @res_idx: Resource index selector.
223 * @res_ctrl: Controls the selection of the resources in the trace unit.
224 * @ss_ctrl: Controls the corresponding single-shot comparator resource.
225 * @ss_status: The status of the corresponding single-shot comparator.
226 * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control.
227 * @addr_idx: Address comparator index selector.
228 * @addr_val: Value for address comparator.
229 * @addr_acc: Address comparator access type.
230 * @addr_type: Current status of the comparator register.
231 * @ctxid_idx: Context ID index selector.
232 * @ctxid_pid: Value of the context ID comparator.
233 * @ctxid_vpid: Virtual PID seen by users if PID namespace is enabled, otherwise
234 * the same value of ctxid_pid.
235 * @ctxid_mask0:Context ID comparator mask for comparator 0-3.
236 * @ctxid_mask1:Context ID comparator mask for comparator 4-7.
237 * @vmid_idx: VM ID index selector.
238 * @vmid_val: Value of the VM ID comparator.
239 * @vmid_mask0: VM ID comparator mask for comparator 0-3.
240 * @vmid_mask1: VM ID comparator mask for comparator 4-7.
241 * @ext_inp: External input selection.
242 */
243 struct etmv4_config {
244 u32 mode;
245 u32 pe_sel;
246 u32 cfg;
247 u32 eventctrl0;
248 u32 eventctrl1;
249 u32 stall_ctrl;
250 u32 ts_ctrl;
251 u32 syncfreq;
252 u32 ccctlr;
253 u32 bb_ctrl;
254 u32 vinst_ctrl;
255 u32 viiectlr;
256 u32 vissctlr;
257 u32 vipcssctlr;
258 u8 seq_idx;
259 u32 seq_ctrl[ETM_MAX_SEQ_STATES];
260 u32 seq_rst;
261 u32 seq_state;
262 u8 cntr_idx;
263 u32 cntrldvr[ETMv4_MAX_CNTR];
264 u32 cntr_ctrl[ETMv4_MAX_CNTR];
265 u32 cntr_val[ETMv4_MAX_CNTR];
266 u8 res_idx;
267 u32 res_ctrl[ETM_MAX_RES_SEL];
268 u32 ss_ctrl[ETM_MAX_SS_CMP];
269 u32 ss_status[ETM_MAX_SS_CMP];
270 u32 ss_pe_cmp[ETM_MAX_SS_CMP];
271 u8 addr_idx;
272 u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];
273 u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP];
274 u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP];
275 u8 ctxid_idx;
276 u64 ctxid_pid[ETMv4_MAX_CTXID_CMP];
277 u64 ctxid_vpid[ETMv4_MAX_CTXID_CMP];
278 u32 ctxid_mask0;
279 u32 ctxid_mask1;
280 u8 vmid_idx;
281 u64 vmid_val[ETM_MAX_VMID_CMP];
282 u32 vmid_mask0;
283 u32 vmid_mask1;
284 u32 ext_inp;
285 };
286
287 /**
288 * struct etm4_drvdata - specifics associated to an ETM component
289 * @base: Memory mapped base address for this component.
290 * @dev: The device entity associated to this component.
291 * @csdev: Component vitals needed by the framework.
292 * @spinlock: Only one at a time pls.
293 * @cpu: The cpu this component is affined to.
294 * @arch: ETM version number.
295 * @nr_pe: The number of processing entity available for tracing.
296 * @nr_pe_cmp: The number of processing entity comparator inputs that are
297 * available for tracing.
298 * @nr_addr_cmp:Number of pairs of address comparators available
299 * as found in ETMIDR4 0-3.
300 * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30.
301 * @nr_ext_inp: Number of external input.
302 * @numcidc: Number of contextID comparators.
303 * @numvmidc: Number of VMID comparators.
304 * @nrseqstate: The number of sequencer states that are implemented.
305 * @nr_event: Indicates how many events the trace unit support.
306 * @nr_resource:The number of resource selection pairs available for tracing.
307 * @nr_ss_cmp: Number of single-shot comparator controls that are available.
308 * @trcid: value of the current ID for this component.
309 * @trcid_size: Indicates the trace ID width.
310 * @ts_size: Global timestamp size field.
311 * @ctxid_size: Size of the context ID field to consider.
312 * @vmid_size: Size of the VM ID comparator to consider.
313 * @ccsize: Indicates the size of the cycle counter in bits.
314 * @ccitmin: minimum value that can be programmed in
315 * @s_ex_level: In secure state, indicates whether instruction tracing is
316 * supported for the corresponding Exception level.
317 * @ns_ex_level:In non-secure state, indicates whether instruction tracing is
318 * supported for the corresponding Exception level.
319 * @enable: Is this ETM currently tracing.
320 * @sticky_enable: true if ETM base configuration has been done.
321 * @boot_enable:True if we should start tracing at boot time.
322 * @os_unlock: True if access to management registers is allowed.
323 * @instrp0: Tracing of load and store instructions
324 * as P0 elements is supported.
325 * @trcbb: Indicates if the trace unit supports branch broadcast tracing.
326 * @trccond: If the trace unit supports conditional
327 * instruction tracing.
328 * @retstack: Indicates if the implementation supports a return stack.
329 * @trccci: Indicates if the trace unit supports cycle counting
330 * for instruction.
331 * @q_support: Q element support characteristics.
332 * @trc_error: Whether a trace unit can trace a system
333 * error exception.
334 * @syncpr: Indicates if an implementation has a fixed
335 * synchronization period.
336 * @stall_ctrl: Enables trace unit functionality that prevents trace
337 * unit buffer overflows.
338 * @sysstall: Does the system support stall control of the PE?
339 * @nooverflow: Indicate if overflow prevention is supported.
340 * @atbtrig: If the implementation can support ATB triggers
341 * @lpoverride: If the implementation can support low-power state over.
342 * @config: structure holding configuration parameters.
343 */
344 struct etmv4_drvdata {
345 void __iomem *base;
346 struct device *dev;
347 struct coresight_device *csdev;
348 spinlock_t spinlock;
349 int cpu;
350 u8 arch;
351 u8 nr_pe;
352 u8 nr_pe_cmp;
353 u8 nr_addr_cmp;
354 u8 nr_cntr;
355 u8 nr_ext_inp;
356 u8 numcidc;
357 u8 numvmidc;
358 u8 nrseqstate;
359 u8 nr_event;
360 u8 nr_resource;
361 u8 nr_ss_cmp;
362 u8 trcid;
363 u8 trcid_size;
364 u8 ts_size;
365 u8 ctxid_size;
366 u8 vmid_size;
367 u8 ccsize;
368 u8 ccitmin;
369 u8 s_ex_level;
370 u8 ns_ex_level;
371 bool enable;
372 bool sticky_enable;
373 bool boot_enable;
374 bool os_unlock;
375 bool instrp0;
376 bool trcbb;
377 bool trccond;
378 bool retstack;
379 bool trccci;
380 bool q_support;
381 bool trc_error;
382 bool syncpr;
383 bool stallctl;
384 bool sysstall;
385 bool nooverflow;
386 bool atbtrig;
387 bool lpoverride;
388 struct etmv4_config config;
389 };
390
391 /* Address comparator access types */
392 enum etm_addr_acctype {
393 ETM_INSTR_ADDR,
394 ETM_DATA_LOAD_ADDR,
395 ETM_DATA_STORE_ADDR,
396 ETM_DATA_LOAD_STORE_ADDR,
397 };
398
399 /* Address comparator context types */
400 enum etm_addr_ctxtype {
401 ETM_CTX_NONE,
402 ETM_CTX_CTXID,
403 ETM_CTX_VMID,
404 ETM_CTX_CTXID_VMID,
405 };
406
407 enum etm_addr_type {
408 ETM_ADDR_TYPE_NONE,
409 ETM_ADDR_TYPE_SINGLE,
410 ETM_ADDR_TYPE_RANGE,
411 ETM_ADDR_TYPE_START,
412 ETM_ADDR_TYPE_STOP,
413 };
414
415 extern const struct attribute_group *coresight_etmv4_groups[];
416 #endif
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