projects / deliverable / linux.git / blob
? search:


2c9d9b1c8e6441d6b7ab988f72765c982ee0deaa
[deliverable/linux.git] / drivers / i2c / busses / i2c-bcm-kona.c
1 /*
2 * Copyright (C) 2013 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/device.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/sched.h>
18 #include <linux/i2c.h>
19 #include <linux/interrupt.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/slab.h>
24
25 /* Hardware register offsets and field defintions */
26 #define CS_OFFSET 0x00000020
27 #define CS_ACK_SHIFT 3
28 #define CS_ACK_MASK 0x00000008
29 #define CS_ACK_CMD_GEN_START 0x00000000
30 #define CS_ACK_CMD_GEN_RESTART 0x00000001
31 #define CS_CMD_SHIFT 1
32 #define CS_CMD_CMD_NO_ACTION 0x00000000
33 #define CS_CMD_CMD_START_RESTART 0x00000001
34 #define CS_CMD_CMD_STOP 0x00000002
35 #define CS_EN_SHIFT 0
36 #define CS_EN_CMD_ENABLE_BSC 0x00000001
37
38 #define TIM_OFFSET 0x00000024
39 #define TIM_PRESCALE_SHIFT 6
40 #define TIM_P_SHIFT 3
41 #define TIM_NO_DIV_SHIFT 2
42 #define TIM_DIV_SHIFT 0
43
44 #define DAT_OFFSET 0x00000028
45
46 #define TOUT_OFFSET 0x0000002c
47
48 #define TXFCR_OFFSET 0x0000003c
49 #define TXFCR_FIFO_FLUSH_MASK 0x00000080
50 #define TXFCR_FIFO_EN_MASK 0x00000040
51
52 #define IER_OFFSET 0x00000044
53 #define IER_READ_COMPLETE_INT_MASK 0x00000010
54 #define IER_I2C_INT_EN_MASK 0x00000008
55 #define IER_FIFO_INT_EN_MASK 0x00000002
56 #define IER_NOACK_EN_MASK 0x00000001
57
58 #define ISR_OFFSET 0x00000048
59 #define ISR_RESERVED_MASK 0xffffff60
60 #define ISR_CMDBUSY_MASK 0x00000080
61 #define ISR_READ_COMPLETE_MASK 0x00000010
62 #define ISR_SES_DONE_MASK 0x00000008
63 #define ISR_ERR_MASK 0x00000004
64 #define ISR_TXFIFOEMPTY_MASK 0x00000002
65 #define ISR_NOACK_MASK 0x00000001
66
67 #define CLKEN_OFFSET 0x0000004C
68 #define CLKEN_AUTOSENSE_OFF_MASK 0x00000080
69 #define CLKEN_M_SHIFT 4
70 #define CLKEN_N_SHIFT 1
71 #define CLKEN_CLKEN_MASK 0x00000001
72
73 #define FIFO_STATUS_OFFSET 0x00000054
74 #define FIFO_STATUS_RXFIFO_EMPTY_MASK 0x00000004
75 #define FIFO_STATUS_TXFIFO_EMPTY_MASK 0x00000010
76
77 #define HSTIM_OFFSET 0x00000058
78 #define HSTIM_HS_MODE_MASK 0x00008000
79 #define HSTIM_HS_HOLD_SHIFT 10
80 #define HSTIM_HS_HIGH_PHASE_SHIFT 5
81 #define HSTIM_HS_SETUP_SHIFT 0
82
83 #define PADCTL_OFFSET 0x0000005c
84 #define PADCTL_PAD_OUT_EN_MASK 0x00000004
85
86 #define RXFCR_OFFSET 0x00000068
87 #define RXFCR_NACK_EN_SHIFT 7
88 #define RXFCR_READ_COUNT_SHIFT 0
89 #define RXFIFORDOUT_OFFSET 0x0000006c
90
91 /* Locally used constants */
92 #define MAX_RX_FIFO_SIZE 64U /* bytes */
93 #define MAX_TX_FIFO_SIZE 64U /* bytes */
94
95 #define STD_EXT_CLK_FREQ 13000000UL
96 #define HS_EXT_CLK_FREQ 104000000UL
97
98 #define MASTERCODE 0x08 /* Mastercodes are 0000_1xxxb */
99
100 #define I2C_TIMEOUT 100 /* msecs */
101
102 /* Operations that can be commanded to the controller */
103 enum bcm_kona_cmd_t {
104 BCM_CMD_NOACTION = 0,
105 BCM_CMD_START,
106 BCM_CMD_RESTART,
107 BCM_CMD_STOP,
108 };
109
110 enum bus_speed_index {
111 BCM_SPD_100K = 0,
112 BCM_SPD_400K,
113 BCM_SPD_1MHZ,
114 };
115
116 enum hs_bus_speed_index {
117 BCM_SPD_3P4MHZ = 0,
118 };
119
120 /* Internal divider settings for standard mode, fast mode and fast mode plus */
121 struct bus_speed_cfg {
122 uint8_t time_m; /* Number of cycles for setup time */
123 uint8_t time_n; /* Number of cycles for hold time */
124 uint8_t prescale; /* Prescale divider */
125 uint8_t time_p; /* Timing coefficient */
126 uint8_t no_div; /* Disable clock divider */
127 uint8_t time_div; /* Post-prescale divider */
128 };
129
130 /* Internal divider settings for high-speed mode */
131 struct hs_bus_speed_cfg {
132 uint8_t hs_hold; /* Number of clock cycles SCL stays low until
133 the end of bit period */
134 uint8_t hs_high_phase; /* Number of clock cycles SCL stays high
135 before it falls */
136 uint8_t hs_setup; /* Number of clock cycles SCL stays low
137 before it rises */
138 uint8_t prescale; /* Prescale divider */
139 uint8_t time_p; /* Timing coefficient */
140 uint8_t no_div; /* Disable clock divider */
141 uint8_t time_div; /* Post-prescale divider */
142 };
143
144 static const struct bus_speed_cfg std_cfg_table[] = {
145 [BCM_SPD_100K] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02},
146 [BCM_SPD_400K] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02},
147 [BCM_SPD_1MHZ] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03},
148 };
149
150 static const struct hs_bus_speed_cfg hs_cfg_table[] = {
151 [BCM_SPD_3P4MHZ] = {0x01, 0x08, 0x14, 0x00, 0x06, 0x01, 0x00},
152 };
153
154 struct bcm_kona_i2c_dev {
155 struct device *device;
156
157 void __iomem *base;
158 int irq;
159 struct clk *external_clk;
160
161 struct i2c_adapter adapter;
162
163 struct completion done;
164
165 const struct bus_speed_cfg *std_cfg;
166 const struct hs_bus_speed_cfg *hs_cfg;
167 };
168
169 static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev,
170 enum bcm_kona_cmd_t cmd)
171 {
172 dev_dbg(dev->device, "%s, %d\n", __func__, cmd);
173
174 switch (cmd) {
175 case BCM_CMD_NOACTION:
176 writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) |
177 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
178 dev->base + CS_OFFSET);
179 break;
180
181 case BCM_CMD_START:
182 writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) |
183 (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
184 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
185 dev->base + CS_OFFSET);
186 break;
187
188 case BCM_CMD_RESTART:
189 writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) |
190 (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
191 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
192 dev->base + CS_OFFSET);
193 break;
194
195 case BCM_CMD_STOP:
196 writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) |
197 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
198 dev->base + CS_OFFSET);
199 break;
200
201 default:
202 dev_err(dev->device, "Unknown command %d\n", cmd);
203 }
204 }
205
206 static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev)
207 {
208 writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK,
209 dev->base + CLKEN_OFFSET);
210 }
211
212 static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev)
213 {
214 writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK,
215 dev->base + CLKEN_OFFSET);
216 }
217
218 static irqreturn_t bcm_kona_i2c_isr(int irq, void *devid)
219 {
220 struct bcm_kona_i2c_dev *dev = devid;
221 uint32_t status = readl(dev->base + ISR_OFFSET);
222
223 if ((status & ~ISR_RESERVED_MASK) == 0)
224 return IRQ_NONE;
225
226 /* Must flush the TX FIFO when NAK detected */
227 if (status & ISR_NOACK_MASK)
228 writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
229 dev->base + TXFCR_OFFSET);
230
231 writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET);
232 complete_all(&dev->done);
233
234 return IRQ_HANDLED;
235 }
236
237 /* Wait for ISR_CMDBUSY_MASK to go low before writing to CS, DAT, or RCD */
238 static int bcm_kona_i2c_wait_if_busy(struct bcm_kona_i2c_dev *dev)
239 {
240 unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT);
241
242 while (readl(dev->base + ISR_OFFSET) & ISR_CMDBUSY_MASK)
243 if (time_after(jiffies, timeout)) {
244 dev_err(dev->device, "CMDBUSY timeout\n");
245 return -ETIMEDOUT;
246 }
247
248 return 0;
249 }
250
251 /* Send command to I2C bus */
252 static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev,
253 enum bcm_kona_cmd_t cmd)
254 {
255 int rc;
256 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT);
257
258 /* Make sure the hardware is ready */
259 rc = bcm_kona_i2c_wait_if_busy(dev);
260 if (rc < 0)
261 return rc;
262
263 /* Unmask the session done interrupt */
264 writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET);
265
266 /* Mark as incomplete before sending the command */
267 reinit_completion(&dev->done);
268
269 /* Send the command */
270 bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd);
271
272 /* Wait for transaction to finish or timeout */
273 time_left = wait_for_completion_timeout(&dev->done, time_left);
274
275 /* Mask all interrupts */
276 writel(0, dev->base + IER_OFFSET);
277
278 if (!time_left) {
279 dev_err(dev->device, "controller timed out\n");
280 rc = -ETIMEDOUT;
281 }
282
283 /* Clear command */
284 bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
285
286 return rc;
287 }
288
289 /* Read a single RX FIFO worth of data from the i2c bus */
290 static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev,
291 uint8_t *buf, unsigned int len,
292 unsigned int last_byte_nak)
293 {
294 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT);
295
296 /* Mark as incomplete before starting the RX FIFO */
297 reinit_completion(&dev->done);
298
299 /* Unmask the read complete interrupt */
300 writel(IER_READ_COMPLETE_INT_MASK, dev->base + IER_OFFSET);
301
302 /* Start the RX FIFO */
303 writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) |
304 (len << RXFCR_READ_COUNT_SHIFT),
305 dev->base + RXFCR_OFFSET);
306
307 /* Wait for FIFO read to complete */
308 time_left = wait_for_completion_timeout(&dev->done, time_left);
309
310 /* Mask all interrupts */
311 writel(0, dev->base + IER_OFFSET);
312
313 if (!time_left) {
314 dev_err(dev->device, "RX FIFO time out\n");
315 return -EREMOTEIO;
316 }
317
318 /* Read data from FIFO */
319 for (; len > 0; len--, buf++)
320 *buf = readl(dev->base + RXFIFORDOUT_OFFSET);
321
322 return 0;
323 }
324
325 /* Read any amount of data using the RX FIFO from the i2c bus */
326 static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev,
327 struct i2c_msg *msg)
328 {
329 unsigned int bytes_to_read = MAX_RX_FIFO_SIZE;
330 unsigned int last_byte_nak = 0;
331 unsigned int bytes_read = 0;
332 int rc;
333
334 uint8_t *tmp_buf = msg->buf;
335
336 while (bytes_read < msg->len) {
337 if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) {
338 last_byte_nak = 1; /* NAK last byte of transfer */
339 bytes_to_read = msg->len - bytes_read;
340 }
341
342 rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read,
343 last_byte_nak);
344 if (rc < 0)
345 return -EREMOTEIO;
346
347 bytes_read += bytes_to_read;
348 tmp_buf += bytes_to_read;
349 }
350
351 return 0;
352 }
353
354 /* Write a single byte of data to the i2c bus */
355 static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data,
356 unsigned int nak_expected)
357 {
358 int rc;
359 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT);
360 unsigned int nak_received;
361
362 /* Make sure the hardware is ready */
363 rc = bcm_kona_i2c_wait_if_busy(dev);
364 if (rc < 0)
365 return rc;
366
367 /* Clear pending session done interrupt */
368 writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET);
369
370 /* Unmask the session done interrupt */
371 writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET);
372
373 /* Mark as incomplete before sending the data */
374 reinit_completion(&dev->done);
375
376 /* Send one byte of data */
377 writel(data, dev->base + DAT_OFFSET);
378
379 /* Wait for byte to be written */
380 time_left = wait_for_completion_timeout(&dev->done, time_left);
381
382 /* Mask all interrupts */
383 writel(0, dev->base + IER_OFFSET);
384
385 if (!time_left) {
386 dev_dbg(dev->device, "controller timed out\n");
387 return -ETIMEDOUT;
388 }
389
390 nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0;
391
392 if (nak_received ^ nak_expected) {
393 dev_dbg(dev->device, "unexpected NAK/ACK\n");
394 return -EREMOTEIO;
395 }
396
397 return 0;
398 }
399
400 /* Write a single TX FIFO worth of data to the i2c bus */
401 static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev,
402 uint8_t *buf, unsigned int len)
403 {
404 int k;
405 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT);
406 unsigned int fifo_status;
407
408 /* Mark as incomplete before sending data to the TX FIFO */
409 reinit_completion(&dev->done);
410
411 /* Unmask the fifo empty and nak interrupt */
412 writel(IER_FIFO_INT_EN_MASK | IER_NOACK_EN_MASK,
413 dev->base + IER_OFFSET);
414
415 /* Disable IRQ to load a FIFO worth of data without interruption */
416 disable_irq(dev->irq);
417
418 /* Write data into FIFO */
419 for (k = 0; k < len; k++)
420 writel(buf[k], (dev->base + DAT_OFFSET));
421
422 /* Enable IRQ now that data has been loaded */
423 enable_irq(dev->irq);
424
425 /* Wait for FIFO to empty */
426 do {
427 time_left = wait_for_completion_timeout(&dev->done, time_left);
428 fifo_status = readl(dev->base + FIFO_STATUS_OFFSET);
429 } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK));
430
431 /* Mask all interrupts */
432 writel(0, dev->base + IER_OFFSET);
433
434 /* Check if there was a NAK */
435 if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) {
436 dev_err(dev->device, "unexpected NAK\n");
437 return -EREMOTEIO;
438 }
439
440 /* Check if a timeout occured */
441 if (!time_left) {
442 dev_err(dev->device, "completion timed out\n");
443 return -EREMOTEIO;
444 }
445
446 return 0;
447 }
448
449
450 /* Write any amount of data using TX FIFO to the i2c bus */
451 static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev,
452 struct i2c_msg *msg)
453 {
454 unsigned int bytes_to_write = MAX_TX_FIFO_SIZE;
455 unsigned int bytes_written = 0;
456 int rc;
457
458 uint8_t *tmp_buf = msg->buf;
459
460 while (bytes_written < msg->len) {
461 if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE)
462 bytes_to_write = msg->len - bytes_written;
463
464 rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf,
465 bytes_to_write);
466 if (rc < 0)
467 return -EREMOTEIO;
468
469 bytes_written += bytes_to_write;
470 tmp_buf += bytes_to_write;
471 }
472
473 return 0;
474 }
475
476 /* Send i2c address */
477 static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev,
478 struct i2c_msg *msg)
479 {
480 unsigned char addr;
481
482 if (msg->flags & I2C_M_TEN) {
483 /* First byte is 11110XX0 where XX is upper 2 bits */
484 addr = 0xF0 | ((msg->addr & 0x300) >> 7);
485 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
486 return -EREMOTEIO;
487
488 /* Second byte is the remaining 8 bits */
489 addr = msg->addr & 0xFF;
490 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
491 return -EREMOTEIO;
492
493 if (msg->flags & I2C_M_RD) {
494 /* For read, send restart command */
495 if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0)
496 return -EREMOTEIO;
497
498 /* Then re-send the first byte with the read bit set */
499 addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01;
500 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
501 return -EREMOTEIO;
502 }
503 } else {
504 addr = msg->addr << 1;
505
506 if (msg->flags & I2C_M_RD)
507 addr |= 1;
508
509 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
510 return -EREMOTEIO;
511 }
512
513 return 0;
514 }
515
516 static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev)
517 {
518 writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK,
519 dev->base + CLKEN_OFFSET);
520 }
521
522 static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev)
523 {
524 writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK,
525 dev->base + HSTIM_OFFSET);
526
527 writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) |
528 (dev->std_cfg->time_p << TIM_P_SHIFT) |
529 (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) |
530 (dev->std_cfg->time_div << TIM_DIV_SHIFT),
531 dev->base + TIM_OFFSET);
532
533 writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) |
534 (dev->std_cfg->time_n << CLKEN_N_SHIFT) |
535 CLKEN_CLKEN_MASK,
536 dev->base + CLKEN_OFFSET);
537 }
538
539 static void bcm_kona_i2c_config_timing_hs(struct bcm_kona_i2c_dev *dev)
540 {
541 writel((dev->hs_cfg->prescale << TIM_PRESCALE_SHIFT) |
542 (dev->hs_cfg->time_p << TIM_P_SHIFT) |
543 (dev->hs_cfg->no_div << TIM_NO_DIV_SHIFT) |
544 (dev->hs_cfg->time_div << TIM_DIV_SHIFT),
545 dev->base + TIM_OFFSET);
546
547 writel((dev->hs_cfg->hs_hold << HSTIM_HS_HOLD_SHIFT) |
548 (dev->hs_cfg->hs_high_phase << HSTIM_HS_HIGH_PHASE_SHIFT) |
549 (dev->hs_cfg->hs_setup << HSTIM_HS_SETUP_SHIFT),
550 dev->base + HSTIM_OFFSET);
551
552 writel(readl(dev->base + HSTIM_OFFSET) | HSTIM_HS_MODE_MASK,
553 dev->base + HSTIM_OFFSET);
554 }
555
556 static int bcm_kona_i2c_switch_to_hs(struct bcm_kona_i2c_dev *dev)
557 {
558 int rc;
559
560 /* Send mastercode at standard speed */
561 rc = bcm_kona_i2c_write_byte(dev, MASTERCODE, 1);
562 if (rc < 0) {
563 pr_err("High speed handshake failed\n");
564 return rc;
565 }
566
567 /* Configure external clock to higher frequency */
568 rc = clk_set_rate(dev->external_clk, HS_EXT_CLK_FREQ);
569 if (rc) {
570 dev_err(dev->device, "%s: clk_set_rate returned %d\n",
571 __func__, rc);
572 return rc;
573 }
574
575 /* Reconfigure internal dividers */
576 bcm_kona_i2c_config_timing_hs(dev);
577
578 /* Send a restart command */
579 rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
580 if (rc < 0)
581 dev_err(dev->device, "High speed restart command failed\n");
582
583 return rc;
584 }
585
586 static int bcm_kona_i2c_switch_to_std(struct bcm_kona_i2c_dev *dev)
587 {
588 int rc;
589
590 /* Reconfigure internal dividers */
591 bcm_kona_i2c_config_timing(dev);
592
593 /* Configure external clock to lower frequency */
594 rc = clk_set_rate(dev->external_clk, STD_EXT_CLK_FREQ);
595 if (rc) {
596 dev_err(dev->device, "%s: clk_set_rate returned %d\n",
597 __func__, rc);
598 }
599
600 return rc;
601 }
602
603 /* Master transfer function */
604 static int bcm_kona_i2c_xfer(struct i2c_adapter *adapter,
605 struct i2c_msg msgs[], int num)
606 {
607 struct bcm_kona_i2c_dev *dev = i2c_get_adapdata(adapter);
608 struct i2c_msg *pmsg;
609 int rc = 0;
610 int i;
611
612 rc = clk_prepare_enable(dev->external_clk);
613 if (rc) {
614 dev_err(dev->device, "%s: peri clock enable failed. err %d\n",
615 __func__, rc);
616 return rc;
617 }
618
619 /* Enable pad output */
620 writel(0, dev->base + PADCTL_OFFSET);
621
622 /* Enable internal clocks */
623 bcm_kona_i2c_enable_clock(dev);
624
625 /* Send start command */
626 rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START);
627 if (rc < 0) {
628 dev_err(dev->device, "Start command failed rc = %d\n", rc);
629 goto xfer_disable_pad;
630 }
631
632 /* Switch to high speed if applicable */
633 if (dev->hs_cfg) {
634 rc = bcm_kona_i2c_switch_to_hs(dev);
635 if (rc < 0)
636 goto xfer_send_stop;
637 }
638
639 /* Loop through all messages */
640 for (i = 0; i < num; i++) {
641 pmsg = &msgs[i];
642
643 /* Send restart for subsequent messages */
644 if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) {
645 rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
646 if (rc < 0) {
647 dev_err(dev->device,
648 "restart cmd failed rc = %d\n", rc);
649 goto xfer_send_stop;
650 }
651 }
652
653 /* Send slave address */
654 if (!(pmsg->flags & I2C_M_NOSTART)) {
655 rc = bcm_kona_i2c_do_addr(dev, pmsg);
656 if (rc < 0) {
657 dev_err(dev->device,
658 "NAK from addr %2.2x msg#%d rc = %d\n",
659 pmsg->addr, i, rc);
660 goto xfer_send_stop;
661 }
662 }
663
664 /* Perform data transfer */
665 if (pmsg->flags & I2C_M_RD) {
666 rc = bcm_kona_i2c_read_fifo(dev, pmsg);
667 if (rc < 0) {
668 dev_err(dev->device, "read failure\n");
669 goto xfer_send_stop;
670 }
671 } else {
672 rc = bcm_kona_i2c_write_fifo(dev, pmsg);
673 if (rc < 0) {
674 dev_err(dev->device, "write failure");
675 goto xfer_send_stop;
676 }
677 }
678 }
679
680 rc = num;
681
682 xfer_send_stop:
683 /* Send a STOP command */
684 bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP);
685
686 /* Return from high speed if applicable */
687 if (dev->hs_cfg) {
688 int hs_rc = bcm_kona_i2c_switch_to_std(dev);
689
690 if (hs_rc)
691 rc = hs_rc;
692 }
693
694 xfer_disable_pad:
695 /* Disable pad output */
696 writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
697
698 /* Stop internal clock */
699 bcm_kona_i2c_disable_clock(dev);
700
701 clk_disable_unprepare(dev->external_clk);
702
703 return rc;
704 }
705
706 static uint32_t bcm_kona_i2c_functionality(struct i2c_adapter *adap)
707 {
708 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
709 I2C_FUNC_NOSTART;
710 }
711
712 static const struct i2c_algorithm bcm_algo = {
713 .master_xfer = bcm_kona_i2c_xfer,
714 .functionality = bcm_kona_i2c_functionality,
715 };
716
717 static int bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev)
718 {
719 unsigned int bus_speed;
720 int ret = of_property_read_u32(dev->device->of_node, "clock-frequency",
721 &bus_speed);
722 if (ret < 0) {
723 dev_err(dev->device, "missing clock-frequency property\n");
724 return -ENODEV;
725 }
726
727 switch (bus_speed) {
728 case 100000:
729 dev->std_cfg = &std_cfg_table[BCM_SPD_100K];
730 break;
731 case 400000:
732 dev->std_cfg = &std_cfg_table[BCM_SPD_400K];
733 break;
734 case 1000000:
735 dev->std_cfg = &std_cfg_table[BCM_SPD_1MHZ];
736 break;
737 case 3400000:
738 /* Send mastercode at 100k */
739 dev->std_cfg = &std_cfg_table[BCM_SPD_100K];
740 dev->hs_cfg = &hs_cfg_table[BCM_SPD_3P4MHZ];
741 break;
742 default:
743 pr_err("%d hz bus speed not supported\n", bus_speed);
744 pr_err("Valid speeds are 100khz, 400khz, 1mhz, and 3.4mhz\n");
745 return -EINVAL;
746 }
747
748 return 0;
749 }
750
751 static int bcm_kona_i2c_probe(struct platform_device *pdev)
752 {
753 int rc = 0;
754 struct bcm_kona_i2c_dev *dev;
755 struct i2c_adapter *adap;
756 struct resource *iomem;
757
758 /* Allocate memory for private data structure */
759 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
760 if (!dev)
761 return -ENOMEM;
762
763 platform_set_drvdata(pdev, dev);
764 dev->device = &pdev->dev;
765 init_completion(&dev->done);
766
767 /* Map hardware registers */
768 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
769 dev->base = devm_ioremap_resource(dev->device, iomem);
770 if (IS_ERR(dev->base))
771 return -ENOMEM;
772
773 /* Get and enable external clock */
774 dev->external_clk = devm_clk_get(dev->device, NULL);
775 if (IS_ERR(dev->external_clk)) {
776 dev_err(dev->device, "couldn't get clock\n");
777 return -ENODEV;
778 }
779
780 rc = clk_set_rate(dev->external_clk, STD_EXT_CLK_FREQ);
781 if (rc) {
782 dev_err(dev->device, "%s: clk_set_rate returned %d\n",
783 __func__, rc);
784 return rc;
785 }
786
787 rc = clk_prepare_enable(dev->external_clk);
788 if (rc) {
789 dev_err(dev->device, "couldn't enable clock\n");
790 return rc;
791 }
792
793 /* Parse bus speed */
794 rc = bcm_kona_i2c_assign_bus_speed(dev);
795 if (rc)
796 goto probe_disable_clk;
797
798 /* Enable internal clocks */
799 bcm_kona_i2c_enable_clock(dev);
800
801 /* Configure internal dividers */
802 bcm_kona_i2c_config_timing(dev);
803
804 /* Disable timeout */
805 writel(0, dev->base + TOUT_OFFSET);
806
807 /* Enable autosense */
808 bcm_kona_i2c_enable_autosense(dev);
809
810 /* Enable TX FIFO */
811 writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
812 dev->base + TXFCR_OFFSET);
813
814 /* Mask all interrupts */
815 writel(0, dev->base + IER_OFFSET);
816
817 /* Clear all pending interrupts */
818 writel(ISR_CMDBUSY_MASK |
819 ISR_READ_COMPLETE_MASK |
820 ISR_SES_DONE_MASK |
821 ISR_ERR_MASK |
822 ISR_TXFIFOEMPTY_MASK |
823 ISR_NOACK_MASK,
824 dev->base + ISR_OFFSET);
825
826 /* Get the interrupt number */
827 dev->irq = platform_get_irq(pdev, 0);
828 if (dev->irq < 0) {
829 dev_err(dev->device, "no irq resource\n");
830 rc = -ENODEV;
831 goto probe_disable_clk;
832 }
833
834 /* register the ISR handler */
835 rc = devm_request_irq(&pdev->dev, dev->irq, bcm_kona_i2c_isr,
836 IRQF_SHARED, pdev->name, dev);
837 if (rc) {
838 dev_err(dev->device, "failed to request irq %i\n", dev->irq);
839 goto probe_disable_clk;
840 }
841
842 /* Enable the controller but leave it idle */
843 bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
844
845 /* Disable pad output */
846 writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
847
848 /* Disable internal clock */
849 bcm_kona_i2c_disable_clock(dev);
850
851 /* Disable external clock */
852 clk_disable_unprepare(dev->external_clk);
853
854 /* Add the i2c adapter */
855 adap = &dev->adapter;
856 i2c_set_adapdata(adap, dev);
857 adap->owner = THIS_MODULE;
858 strlcpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name));
859 adap->algo = &bcm_algo;
860 adap->dev.parent = &pdev->dev;
861 adap->dev.of_node = pdev->dev.of_node;
862
863 rc = i2c_add_adapter(adap);
864 if (rc) {
865 dev_err(dev->device, "failed to add adapter\n");
866 return rc;
867 }
868
869 dev_info(dev->device, "device registered successfully\n");
870
871 return 0;
872
873 probe_disable_clk:
874 bcm_kona_i2c_disable_clock(dev);
875 clk_disable_unprepare(dev->external_clk);
876
877 return rc;
878 }
879
880 static int bcm_kona_i2c_remove(struct platform_device *pdev)
881 {
882 struct bcm_kona_i2c_dev *dev = platform_get_drvdata(pdev);
883
884 i2c_del_adapter(&dev->adapter);
885
886 return 0;
887 }
888
889 static const struct of_device_id bcm_kona_i2c_of_match[] = {
890 {.compatible = "brcm,kona-i2c",},
891 {},
892 };
893 MODULE_DEVICE_TABLE(of, bcm_kona_i2c_of_match);
894
895 static struct platform_driver bcm_kona_i2c_driver = {
896 .driver = {
897 .name = "bcm-kona-i2c",
898 .of_match_table = bcm_kona_i2c_of_match,
899 },
900 .probe = bcm_kona_i2c_probe,
901 .remove = bcm_kona_i2c_remove,
902 };
903 module_platform_driver(bcm_kona_i2c_driver);
904
905 MODULE_AUTHOR("Tim Kryger <tkryger@broadcom.com>");
906 MODULE_DESCRIPTION("Broadcom Kona I2C Driver");
907 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
This page took 0.053194 seconds and 4 git commands to generate.