2 * TI DAVINCI I2C adapter driver.
4 * Copyright (C) 2006 Texas Instruments.
5 * Copyright (C) 2007 MontaVista Software Inc.
7 * Updated by Vinod & Sudhakar Feb 2005
9 * ----------------------------------------------------------------------------
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * ----------------------------------------------------------------------------
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/delay.h>
30 #include <linux/i2c.h>
31 #include <linux/clk.h>
32 #include <linux/errno.h>
33 #include <linux/sched.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/platform_device.h>
38 #include <linux/slab.h>
39 #include <linux/cpufreq.h>
41 #include <mach/hardware.h>
44 /* ----- global defines ----------------------------------------------- */
46 #define DAVINCI_I2C_TIMEOUT (1*HZ)
47 #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \
48 DAVINCI_I2C_IMR_SCD | \
49 DAVINCI_I2C_IMR_ARDY | \
50 DAVINCI_I2C_IMR_NACK | \
53 #define DAVINCI_I2C_OAR_REG 0x00
54 #define DAVINCI_I2C_IMR_REG 0x04
55 #define DAVINCI_I2C_STR_REG 0x08
56 #define DAVINCI_I2C_CLKL_REG 0x0c
57 #define DAVINCI_I2C_CLKH_REG 0x10
58 #define DAVINCI_I2C_CNT_REG 0x14
59 #define DAVINCI_I2C_DRR_REG 0x18
60 #define DAVINCI_I2C_SAR_REG 0x1c
61 #define DAVINCI_I2C_DXR_REG 0x20
62 #define DAVINCI_I2C_MDR_REG 0x24
63 #define DAVINCI_I2C_IVR_REG 0x28
64 #define DAVINCI_I2C_EMDR_REG 0x2c
65 #define DAVINCI_I2C_PSC_REG 0x30
67 #define DAVINCI_I2C_IVR_AAS 0x07
68 #define DAVINCI_I2C_IVR_SCD 0x06
69 #define DAVINCI_I2C_IVR_XRDY 0x05
70 #define DAVINCI_I2C_IVR_RDR 0x04
71 #define DAVINCI_I2C_IVR_ARDY 0x03
72 #define DAVINCI_I2C_IVR_NACK 0x02
73 #define DAVINCI_I2C_IVR_AL 0x01
75 #define DAVINCI_I2C_STR_BB BIT(12)
76 #define DAVINCI_I2C_STR_RSFULL BIT(11)
77 #define DAVINCI_I2C_STR_SCD BIT(5)
78 #define DAVINCI_I2C_STR_ARDY BIT(2)
79 #define DAVINCI_I2C_STR_NACK BIT(1)
80 #define DAVINCI_I2C_STR_AL BIT(0)
82 #define DAVINCI_I2C_MDR_NACK BIT(15)
83 #define DAVINCI_I2C_MDR_STT BIT(13)
84 #define DAVINCI_I2C_MDR_STP BIT(11)
85 #define DAVINCI_I2C_MDR_MST BIT(10)
86 #define DAVINCI_I2C_MDR_TRX BIT(9)
87 #define DAVINCI_I2C_MDR_XA BIT(8)
88 #define DAVINCI_I2C_MDR_RM BIT(7)
89 #define DAVINCI_I2C_MDR_IRS BIT(5)
91 #define DAVINCI_I2C_IMR_AAS BIT(6)
92 #define DAVINCI_I2C_IMR_SCD BIT(5)
93 #define DAVINCI_I2C_IMR_XRDY BIT(4)
94 #define DAVINCI_I2C_IMR_RRDY BIT(3)
95 #define DAVINCI_I2C_IMR_ARDY BIT(2)
96 #define DAVINCI_I2C_IMR_NACK BIT(1)
97 #define DAVINCI_I2C_IMR_AL BIT(0)
99 struct davinci_i2c_dev
{
102 struct completion cmd_complete
;
110 struct i2c_adapter adapter
;
111 #ifdef CONFIG_CPU_FREQ
112 struct completion xfr_complete
;
113 struct notifier_block freq_transition
;
117 /* default platform data to use if not supplied in the platform_device */
118 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default
= {
123 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev
*i2c_dev
,
126 __raw_writew(val
, i2c_dev
->base
+ reg
);
129 static inline u16
davinci_i2c_read_reg(struct davinci_i2c_dev
*i2c_dev
, int reg
)
131 return __raw_readw(i2c_dev
->base
+ reg
);
134 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev
*i2c_dev
,
139 w
= davinci_i2c_read_reg(i2c_dev
, DAVINCI_I2C_MDR_REG
);
140 if (!val
) /* put I2C into reset */
141 w
&= ~DAVINCI_I2C_MDR_IRS
;
142 else /* take I2C out of reset */
143 w
|= DAVINCI_I2C_MDR_IRS
;
145 davinci_i2c_write_reg(i2c_dev
, DAVINCI_I2C_MDR_REG
, w
);
148 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev
*dev
)
150 struct davinci_i2c_platform_data
*pdata
= dev
->dev
->platform_data
;
156 u32 input_clock
= clk_get_rate(dev
->clk
);
158 /* NOTE: I2C Clock divider programming info
159 * As per I2C specs the following formulas provide prescaler
160 * and low/high divider values
161 * input clk --> PSC Div -----------> ICCL/H Div --> output clock
164 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
167 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
169 * where if PSC == 0, d = 7,
174 /* get minimum of 7 MHz clock, but max of 12 MHz */
175 psc
= (input_clock
/ 7000000) - 1;
176 if ((input_clock
/ (psc
+ 1)) > 12000000)
177 psc
++; /* better to run under spec than over */
178 d
= (psc
>= 2) ? 5 : 7 - psc
;
180 clk
= ((input_clock
/ (psc
+ 1)) / (pdata
->bus_freq
* 1000)) - (d
<< 1);
184 davinci_i2c_write_reg(dev
, DAVINCI_I2C_PSC_REG
, psc
);
185 davinci_i2c_write_reg(dev
, DAVINCI_I2C_CLKH_REG
, clkh
);
186 davinci_i2c_write_reg(dev
, DAVINCI_I2C_CLKL_REG
, clkl
);
188 dev_dbg(dev
->dev
, "input_clock = %d, CLK = %d\n", input_clock
, clk
);
192 * This function configures I2C and brings I2C out of reset.
193 * This function is called during I2C init function. This function
194 * also gets called if I2C encounters any errors.
196 static int i2c_davinci_init(struct davinci_i2c_dev
*dev
)
198 struct davinci_i2c_platform_data
*pdata
= dev
->dev
->platform_data
;
201 pdata
= &davinci_i2c_platform_data_default
;
203 /* put I2C into reset */
204 davinci_i2c_reset_ctrl(dev
, 0);
206 /* compute clock dividers */
207 i2c_davinci_calc_clk_dividers(dev
);
209 /* Respond at reserved "SMBus Host" slave address" (and zero);
210 * we seem to have no option to not respond...
212 davinci_i2c_write_reg(dev
, DAVINCI_I2C_OAR_REG
, 0x08);
214 dev_dbg(dev
->dev
, "PSC = %d\n",
215 davinci_i2c_read_reg(dev
, DAVINCI_I2C_PSC_REG
));
216 dev_dbg(dev
->dev
, "CLKL = %d\n",
217 davinci_i2c_read_reg(dev
, DAVINCI_I2C_CLKL_REG
));
218 dev_dbg(dev
->dev
, "CLKH = %d\n",
219 davinci_i2c_read_reg(dev
, DAVINCI_I2C_CLKH_REG
));
220 dev_dbg(dev
->dev
, "bus_freq = %dkHz, bus_delay = %d\n",
221 pdata
->bus_freq
, pdata
->bus_delay
);
223 /* Take the I2C module out of reset: */
224 davinci_i2c_reset_ctrl(dev
, 1);
226 /* Enable interrupts */
227 davinci_i2c_write_reg(dev
, DAVINCI_I2C_IMR_REG
, I2C_DAVINCI_INTR_ALL
);
233 * Waiting for bus not busy
235 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev
*dev
,
238 unsigned long timeout
;
240 timeout
= jiffies
+ dev
->adapter
.timeout
;
241 while (davinci_i2c_read_reg(dev
, DAVINCI_I2C_STR_REG
)
242 & DAVINCI_I2C_STR_BB
) {
243 if (time_after(jiffies
, timeout
)) {
245 "timeout waiting for bus ready\n");
256 * Low level master read/write transaction. This function is called
257 * from i2c_davinci_xfer.
260 i2c_davinci_xfer_msg(struct i2c_adapter
*adap
, struct i2c_msg
*msg
, int stop
)
262 struct davinci_i2c_dev
*dev
= i2c_get_adapdata(adap
);
263 struct davinci_i2c_platform_data
*pdata
= dev
->dev
->platform_data
;
269 pdata
= &davinci_i2c_platform_data_default
;
270 /* Introduce a delay, required for some boards (e.g Davinci EVM) */
271 if (pdata
->bus_delay
)
272 udelay(pdata
->bus_delay
);
274 /* set the slave address */
275 davinci_i2c_write_reg(dev
, DAVINCI_I2C_SAR_REG
, msg
->addr
);
278 dev
->buf_len
= msg
->len
;
281 davinci_i2c_write_reg(dev
, DAVINCI_I2C_CNT_REG
, dev
->buf_len
);
283 INIT_COMPLETION(dev
->cmd_complete
);
286 /* Take I2C out of reset, configure it as master and set the
288 flag
= DAVINCI_I2C_MDR_IRS
| DAVINCI_I2C_MDR_MST
| DAVINCI_I2C_MDR_STT
;
290 /* if the slave address is ten bit address, enable XA bit */
291 if (msg
->flags
& I2C_M_TEN
)
292 flag
|= DAVINCI_I2C_MDR_XA
;
293 if (!(msg
->flags
& I2C_M_RD
))
294 flag
|= DAVINCI_I2C_MDR_TRX
;
296 flag
|= DAVINCI_I2C_MDR_STP
;
298 flag
|= DAVINCI_I2C_MDR_RM
;
299 flag
&= ~DAVINCI_I2C_MDR_STP
;
302 /* Enable receive or transmit interrupts */
303 w
= davinci_i2c_read_reg(dev
, DAVINCI_I2C_IMR_REG
);
304 if (msg
->flags
& I2C_M_RD
)
305 w
|= DAVINCI_I2C_IMR_RRDY
;
307 w
|= DAVINCI_I2C_IMR_XRDY
;
308 davinci_i2c_write_reg(dev
, DAVINCI_I2C_IMR_REG
, w
);
312 /* write the data into mode register */
313 davinci_i2c_write_reg(dev
, DAVINCI_I2C_MDR_REG
, flag
);
316 * First byte should be set here, not after interrupt,
317 * because transmit-data-ready interrupt can come before
318 * NACK-interrupt during sending of previous message and
319 * ICDXR may have wrong data
321 if ((!(msg
->flags
& I2C_M_RD
)) && dev
->buf_len
) {
322 davinci_i2c_write_reg(dev
, DAVINCI_I2C_DXR_REG
, *dev
->buf
++);
326 r
= wait_for_completion_interruptible_timeout(&dev
->cmd_complete
,
327 dev
->adapter
.timeout
);
329 dev_err(dev
->dev
, "controller timed out\n");
330 i2c_davinci_init(dev
);
335 /* This should be 0 if all bytes were transferred
336 * or dev->cmd_err denotes an error.
337 * A signal may have aborted the transfer.
340 dev_err(dev
->dev
, "abnormal termination buf_len=%i\n",
352 if (likely(!dev
->cmd_err
))
355 /* We have an error */
356 if (dev
->cmd_err
& DAVINCI_I2C_STR_AL
) {
357 i2c_davinci_init(dev
);
361 if (dev
->cmd_err
& DAVINCI_I2C_STR_NACK
) {
362 if (msg
->flags
& I2C_M_IGNORE_NAK
)
365 w
= davinci_i2c_read_reg(dev
, DAVINCI_I2C_MDR_REG
);
366 w
|= DAVINCI_I2C_MDR_STP
;
367 davinci_i2c_write_reg(dev
, DAVINCI_I2C_MDR_REG
, w
);
375 * Prepare controller for a transaction and call i2c_davinci_xfer_msg
378 i2c_davinci_xfer(struct i2c_adapter
*adap
, struct i2c_msg msgs
[], int num
)
380 struct davinci_i2c_dev
*dev
= i2c_get_adapdata(adap
);
384 dev_dbg(dev
->dev
, "%s: msgs: %d\n", __func__
, num
);
386 ret
= i2c_davinci_wait_bus_not_busy(dev
, 1);
388 dev_warn(dev
->dev
, "timeout waiting for bus ready\n");
392 for (i
= 0; i
< num
; i
++) {
393 ret
= i2c_davinci_xfer_msg(adap
, &msgs
[i
], (i
== (num
- 1)));
394 dev_dbg(dev
->dev
, "%s [%d/%d] ret: %d\n", __func__
, i
+ 1, num
,
400 #ifdef CONFIG_CPU_FREQ
401 complete(&dev
->xfr_complete
);
407 static u32
i2c_davinci_func(struct i2c_adapter
*adap
)
409 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
412 static void terminate_read(struct davinci_i2c_dev
*dev
)
414 u16 w
= davinci_i2c_read_reg(dev
, DAVINCI_I2C_MDR_REG
);
415 w
|= DAVINCI_I2C_MDR_NACK
;
416 davinci_i2c_write_reg(dev
, DAVINCI_I2C_MDR_REG
, w
);
418 /* Throw away data */
419 davinci_i2c_read_reg(dev
, DAVINCI_I2C_DRR_REG
);
421 dev_err(dev
->dev
, "RDR IRQ while no data requested\n");
423 static void terminate_write(struct davinci_i2c_dev
*dev
)
425 u16 w
= davinci_i2c_read_reg(dev
, DAVINCI_I2C_MDR_REG
);
426 w
|= DAVINCI_I2C_MDR_RM
| DAVINCI_I2C_MDR_STP
;
427 davinci_i2c_write_reg(dev
, DAVINCI_I2C_MDR_REG
, w
);
430 dev_dbg(dev
->dev
, "TDR IRQ while no data to send\n");
434 * Interrupt service routine. This gets called whenever an I2C interrupt
437 static irqreturn_t
i2c_davinci_isr(int this_irq
, void *dev_id
)
439 struct davinci_i2c_dev
*dev
= dev_id
;
444 while ((stat
= davinci_i2c_read_reg(dev
, DAVINCI_I2C_IVR_REG
))) {
445 dev_dbg(dev
->dev
, "%s: stat=0x%x\n", __func__
, stat
);
446 if (count
++ == 100) {
447 dev_warn(dev
->dev
, "Too much work in one IRQ\n");
452 case DAVINCI_I2C_IVR_AL
:
453 /* Arbitration lost, must retry */
454 dev
->cmd_err
|= DAVINCI_I2C_STR_AL
;
456 complete(&dev
->cmd_complete
);
459 case DAVINCI_I2C_IVR_NACK
:
460 dev
->cmd_err
|= DAVINCI_I2C_STR_NACK
;
462 complete(&dev
->cmd_complete
);
465 case DAVINCI_I2C_IVR_ARDY
:
466 davinci_i2c_write_reg(dev
,
467 DAVINCI_I2C_STR_REG
, DAVINCI_I2C_STR_ARDY
);
468 if (((dev
->buf_len
== 0) && (dev
->stop
!= 0)) ||
469 (dev
->cmd_err
& DAVINCI_I2C_STR_NACK
)) {
470 w
= davinci_i2c_read_reg(dev
,
471 DAVINCI_I2C_MDR_REG
);
472 w
|= DAVINCI_I2C_MDR_STP
;
473 davinci_i2c_write_reg(dev
,
474 DAVINCI_I2C_MDR_REG
, w
);
476 complete(&dev
->cmd_complete
);
479 case DAVINCI_I2C_IVR_RDR
:
482 davinci_i2c_read_reg(dev
,
483 DAVINCI_I2C_DRR_REG
);
488 davinci_i2c_write_reg(dev
,
490 DAVINCI_I2C_IMR_RRDY
);
492 /* signal can terminate transfer */
497 case DAVINCI_I2C_IVR_XRDY
:
499 davinci_i2c_write_reg(dev
, DAVINCI_I2C_DXR_REG
,
505 w
= davinci_i2c_read_reg(dev
,
506 DAVINCI_I2C_IMR_REG
);
507 w
&= ~DAVINCI_I2C_IMR_XRDY
;
508 davinci_i2c_write_reg(dev
,
512 /* signal can terminate transfer */
513 terminate_write(dev
);
517 case DAVINCI_I2C_IVR_SCD
:
518 davinci_i2c_write_reg(dev
,
519 DAVINCI_I2C_STR_REG
, DAVINCI_I2C_STR_SCD
);
520 complete(&dev
->cmd_complete
);
523 case DAVINCI_I2C_IVR_AAS
:
524 dev_dbg(dev
->dev
, "Address as slave interrupt\n");
528 dev_warn(dev
->dev
, "Unrecognized irq stat %d\n", stat
);
533 return count
? IRQ_HANDLED
: IRQ_NONE
;
536 #ifdef CONFIG_CPU_FREQ
537 static int i2c_davinci_cpufreq_transition(struct notifier_block
*nb
,
538 unsigned long val
, void *data
)
540 struct davinci_i2c_dev
*dev
;
542 dev
= container_of(nb
, struct davinci_i2c_dev
, freq_transition
);
543 if (val
== CPUFREQ_PRECHANGE
) {
544 wait_for_completion(&dev
->xfr_complete
);
545 davinci_i2c_reset_ctrl(dev
, 0);
546 } else if (val
== CPUFREQ_POSTCHANGE
) {
547 i2c_davinci_calc_clk_dividers(dev
);
548 davinci_i2c_reset_ctrl(dev
, 1);
554 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev
*dev
)
556 dev
->freq_transition
.notifier_call
= i2c_davinci_cpufreq_transition
;
558 return cpufreq_register_notifier(&dev
->freq_transition
,
559 CPUFREQ_TRANSITION_NOTIFIER
);
562 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev
*dev
)
564 cpufreq_unregister_notifier(&dev
->freq_transition
,
565 CPUFREQ_TRANSITION_NOTIFIER
);
568 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev
*dev
)
573 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev
*dev
)
578 static struct i2c_algorithm i2c_davinci_algo
= {
579 .master_xfer
= i2c_davinci_xfer
,
580 .functionality
= i2c_davinci_func
,
583 static int davinci_i2c_probe(struct platform_device
*pdev
)
585 struct davinci_i2c_dev
*dev
;
586 struct i2c_adapter
*adap
;
587 struct resource
*mem
, *irq
, *ioarea
;
590 /* NOTE: driver uses the static register mapping */
591 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
593 dev_err(&pdev
->dev
, "no mem resource?\n");
597 irq
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
599 dev_err(&pdev
->dev
, "no irq resource?\n");
603 ioarea
= request_mem_region(mem
->start
, resource_size(mem
),
606 dev_err(&pdev
->dev
, "I2C region already claimed\n");
610 dev
= kzalloc(sizeof(struct davinci_i2c_dev
), GFP_KERNEL
);
613 goto err_release_region
;
616 init_completion(&dev
->cmd_complete
);
617 #ifdef CONFIG_CPU_FREQ
618 init_completion(&dev
->xfr_complete
);
620 dev
->dev
= get_device(&pdev
->dev
);
621 dev
->irq
= irq
->start
;
622 platform_set_drvdata(pdev
, dev
);
624 dev
->clk
= clk_get(&pdev
->dev
, NULL
);
625 if (IS_ERR(dev
->clk
)) {
629 clk_enable(dev
->clk
);
631 dev
->base
= ioremap(mem
->start
, resource_size(mem
));
634 goto err_mem_ioremap
;
637 i2c_davinci_init(dev
);
639 r
= request_irq(dev
->irq
, i2c_davinci_isr
, 0, pdev
->name
, dev
);
641 dev_err(&pdev
->dev
, "failure requesting irq %i\n", dev
->irq
);
642 goto err_unuse_clocks
;
645 r
= i2c_davinci_cpufreq_register(dev
);
647 dev_err(&pdev
->dev
, "failed to register cpufreq\n");
651 adap
= &dev
->adapter
;
652 i2c_set_adapdata(adap
, dev
);
653 adap
->owner
= THIS_MODULE
;
654 adap
->class = I2C_CLASS_HWMON
;
655 strlcpy(adap
->name
, "DaVinci I2C adapter", sizeof(adap
->name
));
656 adap
->algo
= &i2c_davinci_algo
;
657 adap
->dev
.parent
= &pdev
->dev
;
658 adap
->timeout
= DAVINCI_I2C_TIMEOUT
;
661 r
= i2c_add_numbered_adapter(adap
);
663 dev_err(&pdev
->dev
, "failure adding adapter\n");
670 free_irq(dev
->irq
, dev
);
674 clk_disable(dev
->clk
);
678 platform_set_drvdata(pdev
, NULL
);
679 put_device(&pdev
->dev
);
682 release_mem_region(mem
->start
, resource_size(mem
));
687 static int davinci_i2c_remove(struct platform_device
*pdev
)
689 struct davinci_i2c_dev
*dev
= platform_get_drvdata(pdev
);
690 struct resource
*mem
;
692 i2c_davinci_cpufreq_deregister(dev
);
694 platform_set_drvdata(pdev
, NULL
);
695 i2c_del_adapter(&dev
->adapter
);
696 put_device(&pdev
->dev
);
698 clk_disable(dev
->clk
);
702 davinci_i2c_write_reg(dev
, DAVINCI_I2C_MDR_REG
, 0);
703 free_irq(IRQ_I2C
, dev
);
707 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
708 release_mem_region(mem
->start
, resource_size(mem
));
713 static int davinci_i2c_suspend(struct device
*dev
)
715 struct platform_device
*pdev
= to_platform_device(dev
);
716 struct davinci_i2c_dev
*i2c_dev
= platform_get_drvdata(pdev
);
718 /* put I2C into reset */
719 davinci_i2c_reset_ctrl(i2c_dev
, 0);
720 clk_disable(i2c_dev
->clk
);
725 static int davinci_i2c_resume(struct device
*dev
)
727 struct platform_device
*pdev
= to_platform_device(dev
);
728 struct davinci_i2c_dev
*i2c_dev
= platform_get_drvdata(pdev
);
730 clk_enable(i2c_dev
->clk
);
731 /* take I2C out of reset */
732 davinci_i2c_reset_ctrl(i2c_dev
, 1);
737 static const struct dev_pm_ops davinci_i2c_pm
= {
738 .suspend
= davinci_i2c_suspend
,
739 .resume
= davinci_i2c_resume
,
742 #define davinci_i2c_pm_ops (&davinci_i2c_pm)
744 #define davinci_i2c_pm_ops NULL
747 /* work with hotplug and coldplug */
748 MODULE_ALIAS("platform:i2c_davinci");
750 static struct platform_driver davinci_i2c_driver
= {
751 .probe
= davinci_i2c_probe
,
752 .remove
= davinci_i2c_remove
,
754 .name
= "i2c_davinci",
755 .owner
= THIS_MODULE
,
756 .pm
= davinci_i2c_pm_ops
,
760 /* I2C may be needed to bring up other drivers */
761 static int __init
davinci_i2c_init_driver(void)
763 return platform_driver_register(&davinci_i2c_driver
);
765 subsys_initcall(davinci_i2c_init_driver
);
767 static void __exit
davinci_i2c_exit_driver(void)
769 platform_driver_unregister(&davinci_i2c_driver
);
771 module_exit(davinci_i2c_exit_driver
);
773 MODULE_AUTHOR("Texas Instruments India");
774 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
775 MODULE_LICENSE("GPL");