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[deliverable/linux.git] / drivers / i2c / busses / i2c-davinci.c
1 /*
2 * TI DAVINCI I2C adapter driver.
3 *
4 * Copyright (C) 2006 Texas Instruments.
5 * Copyright (C) 2007 MontaVista Software Inc.
6 *
7 * Updated by Vinod & Sudhakar Feb 2005
8 *
9 * ----------------------------------------------------------------------------
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 * ----------------------------------------------------------------------------
21 *
22 */
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/delay.h>
26 #include <linux/i2c.h>
27 #include <linux/clk.h>
28 #include <linux/errno.h>
29 #include <linux/sched.h>
30 #include <linux/err.h>
31 #include <linux/interrupt.h>
32 #include <linux/platform_device.h>
33 #include <linux/io.h>
34 #include <linux/slab.h>
35 #include <linux/cpufreq.h>
36 #include <linux/gpio.h>
37 #include <linux/of_device.h>
38 #include <linux/platform_data/i2c-davinci.h>
39
40 /* ----- global defines ----------------------------------------------- */
41
42 #define DAVINCI_I2C_TIMEOUT (1*HZ)
43 #define DAVINCI_I2C_MAX_TRIES 2
44 #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \
45 DAVINCI_I2C_IMR_SCD | \
46 DAVINCI_I2C_IMR_ARDY | \
47 DAVINCI_I2C_IMR_NACK | \
48 DAVINCI_I2C_IMR_AL)
49
50 #define DAVINCI_I2C_OAR_REG 0x00
51 #define DAVINCI_I2C_IMR_REG 0x04
52 #define DAVINCI_I2C_STR_REG 0x08
53 #define DAVINCI_I2C_CLKL_REG 0x0c
54 #define DAVINCI_I2C_CLKH_REG 0x10
55 #define DAVINCI_I2C_CNT_REG 0x14
56 #define DAVINCI_I2C_DRR_REG 0x18
57 #define DAVINCI_I2C_SAR_REG 0x1c
58 #define DAVINCI_I2C_DXR_REG 0x20
59 #define DAVINCI_I2C_MDR_REG 0x24
60 #define DAVINCI_I2C_IVR_REG 0x28
61 #define DAVINCI_I2C_EMDR_REG 0x2c
62 #define DAVINCI_I2C_PSC_REG 0x30
63 #define DAVINCI_I2C_FUNC_REG 0x48
64 #define DAVINCI_I2C_DIR_REG 0x4c
65 #define DAVINCI_I2C_DIN_REG 0x50
66 #define DAVINCI_I2C_DOUT_REG 0x54
67 #define DAVINCI_I2C_DSET_REG 0x58
68 #define DAVINCI_I2C_DCLR_REG 0x5c
69
70 #define DAVINCI_I2C_IVR_AAS 0x07
71 #define DAVINCI_I2C_IVR_SCD 0x06
72 #define DAVINCI_I2C_IVR_XRDY 0x05
73 #define DAVINCI_I2C_IVR_RDR 0x04
74 #define DAVINCI_I2C_IVR_ARDY 0x03
75 #define DAVINCI_I2C_IVR_NACK 0x02
76 #define DAVINCI_I2C_IVR_AL 0x01
77
78 #define DAVINCI_I2C_STR_BB BIT(12)
79 #define DAVINCI_I2C_STR_RSFULL BIT(11)
80 #define DAVINCI_I2C_STR_SCD BIT(5)
81 #define DAVINCI_I2C_STR_ARDY BIT(2)
82 #define DAVINCI_I2C_STR_NACK BIT(1)
83 #define DAVINCI_I2C_STR_AL BIT(0)
84
85 #define DAVINCI_I2C_MDR_NACK BIT(15)
86 #define DAVINCI_I2C_MDR_STT BIT(13)
87 #define DAVINCI_I2C_MDR_STP BIT(11)
88 #define DAVINCI_I2C_MDR_MST BIT(10)
89 #define DAVINCI_I2C_MDR_TRX BIT(9)
90 #define DAVINCI_I2C_MDR_XA BIT(8)
91 #define DAVINCI_I2C_MDR_RM BIT(7)
92 #define DAVINCI_I2C_MDR_IRS BIT(5)
93
94 #define DAVINCI_I2C_IMR_AAS BIT(6)
95 #define DAVINCI_I2C_IMR_SCD BIT(5)
96 #define DAVINCI_I2C_IMR_XRDY BIT(4)
97 #define DAVINCI_I2C_IMR_RRDY BIT(3)
98 #define DAVINCI_I2C_IMR_ARDY BIT(2)
99 #define DAVINCI_I2C_IMR_NACK BIT(1)
100 #define DAVINCI_I2C_IMR_AL BIT(0)
101
102 /* set SDA and SCL as GPIO */
103 #define DAVINCI_I2C_FUNC_PFUNC0 BIT(0)
104
105 /* set SCL as output when used as GPIO*/
106 #define DAVINCI_I2C_DIR_PDIR0 BIT(0)
107 /* set SDA as output when used as GPIO*/
108 #define DAVINCI_I2C_DIR_PDIR1 BIT(1)
109
110 /* read SCL GPIO level */
111 #define DAVINCI_I2C_DIN_PDIN0 BIT(0)
112 /* read SDA GPIO level */
113 #define DAVINCI_I2C_DIN_PDIN1 BIT(1)
114
115 /*set the SCL GPIO high */
116 #define DAVINCI_I2C_DSET_PDSET0 BIT(0)
117 /*set the SDA GPIO high */
118 #define DAVINCI_I2C_DSET_PDSET1 BIT(1)
119
120 /* set the SCL GPIO low */
121 #define DAVINCI_I2C_DCLR_PDCLR0 BIT(0)
122 /* set the SDA GPIO low */
123 #define DAVINCI_I2C_DCLR_PDCLR1 BIT(1)
124
125 struct davinci_i2c_dev {
126 struct device *dev;
127 void __iomem *base;
128 struct completion cmd_complete;
129 struct clk *clk;
130 int cmd_err;
131 u8 *buf;
132 size_t buf_len;
133 int irq;
134 int stop;
135 u8 terminate;
136 struct i2c_adapter adapter;
137 #ifdef CONFIG_CPU_FREQ
138 struct completion xfr_complete;
139 struct notifier_block freq_transition;
140 #endif
141 struct davinci_i2c_platform_data *pdata;
142 };
143
144 /* default platform data to use if not supplied in the platform_device */
145 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
146 .bus_freq = 100,
147 .bus_delay = 0,
148 };
149
150 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
151 int reg, u16 val)
152 {
153 writew_relaxed(val, i2c_dev->base + reg);
154 }
155
156 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
157 {
158 return readw_relaxed(i2c_dev->base + reg);
159 }
160
161 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
162 int val)
163 {
164 u16 w;
165
166 w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
167 if (!val) /* put I2C into reset */
168 w &= ~DAVINCI_I2C_MDR_IRS;
169 else /* take I2C out of reset */
170 w |= DAVINCI_I2C_MDR_IRS;
171
172 davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
173 }
174
175 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
176 {
177 struct davinci_i2c_platform_data *pdata = dev->pdata;
178 u16 psc;
179 u32 clk;
180 u32 d;
181 u32 clkh;
182 u32 clkl;
183 u32 input_clock = clk_get_rate(dev->clk);
184
185 /* NOTE: I2C Clock divider programming info
186 * As per I2C specs the following formulas provide prescaler
187 * and low/high divider values
188 * input clk --> PSC Div -----------> ICCL/H Div --> output clock
189 * module clk
190 *
191 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
192 *
193 * Thus,
194 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
195 *
196 * where if PSC == 0, d = 7,
197 * if PSC == 1, d = 6
198 * if PSC > 1 , d = 5
199 */
200
201 /* get minimum of 7 MHz clock, but max of 12 MHz */
202 psc = (input_clock / 7000000) - 1;
203 if ((input_clock / (psc + 1)) > 12000000)
204 psc++; /* better to run under spec than over */
205 d = (psc >= 2) ? 5 : 7 - psc;
206
207 clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1);
208 clkh = clk >> 1;
209 clkl = clk - clkh;
210
211 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
212 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
213 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
214
215 dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
216 }
217
218 /*
219 * This function configures I2C and brings I2C out of reset.
220 * This function is called during I2C init function. This function
221 * also gets called if I2C encounters any errors.
222 */
223 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
224 {
225 struct davinci_i2c_platform_data *pdata = dev->pdata;
226
227 /* put I2C into reset */
228 davinci_i2c_reset_ctrl(dev, 0);
229
230 /* compute clock dividers */
231 i2c_davinci_calc_clk_dividers(dev);
232
233 /* Respond at reserved "SMBus Host" slave address" (and zero);
234 * we seem to have no option to not respond...
235 */
236 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08);
237
238 dev_dbg(dev->dev, "PSC = %d\n",
239 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
240 dev_dbg(dev->dev, "CLKL = %d\n",
241 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
242 dev_dbg(dev->dev, "CLKH = %d\n",
243 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
244 dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
245 pdata->bus_freq, pdata->bus_delay);
246
247
248 /* Take the I2C module out of reset: */
249 davinci_i2c_reset_ctrl(dev, 1);
250
251 /* Enable interrupts */
252 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
253
254 return 0;
255 }
256
257 /*
258 * This routine does i2c bus recovery by using i2c_generic_gpio_recovery
259 * which is provided by I2C Bus recovery infrastructure.
260 */
261 static void davinci_i2c_prepare_recovery(struct i2c_adapter *adap)
262 {
263 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
264
265 /* Disable interrupts */
266 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, 0);
267
268 /* put I2C into reset */
269 davinci_i2c_reset_ctrl(dev, 0);
270 }
271
272 static void davinci_i2c_unprepare_recovery(struct i2c_adapter *adap)
273 {
274 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
275
276 i2c_davinci_init(dev);
277 }
278
279 static struct i2c_bus_recovery_info davinci_i2c_gpio_recovery_info = {
280 .recover_bus = i2c_generic_gpio_recovery,
281 .prepare_recovery = davinci_i2c_prepare_recovery,
282 .unprepare_recovery = davinci_i2c_unprepare_recovery,
283 };
284
285 static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val)
286 {
287 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
288
289 if (val)
290 davinci_i2c_write_reg(dev, DAVINCI_I2C_DSET_REG,
291 DAVINCI_I2C_DSET_PDSET0);
292 else
293 davinci_i2c_write_reg(dev, DAVINCI_I2C_DCLR_REG,
294 DAVINCI_I2C_DCLR_PDCLR0);
295 }
296
297 static int davinci_i2c_get_scl(struct i2c_adapter *adap)
298 {
299 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
300 int val;
301
302 /* read the state of SCL */
303 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
304 return val & DAVINCI_I2C_DIN_PDIN0;
305 }
306
307 static int davinci_i2c_get_sda(struct i2c_adapter *adap)
308 {
309 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
310 int val;
311
312 /* read the state of SDA */
313 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
314 return val & DAVINCI_I2C_DIN_PDIN1;
315 }
316
317 static void davinci_i2c_scl_prepare_recovery(struct i2c_adapter *adap)
318 {
319 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
320
321 davinci_i2c_prepare_recovery(adap);
322
323 /* SCL output, SDA input */
324 davinci_i2c_write_reg(dev, DAVINCI_I2C_DIR_REG, DAVINCI_I2C_DIR_PDIR0);
325
326 /* change to GPIO mode */
327 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG,
328 DAVINCI_I2C_FUNC_PFUNC0);
329 }
330
331 static void davinci_i2c_scl_unprepare_recovery(struct i2c_adapter *adap)
332 {
333 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
334
335 /* change back to I2C mode */
336 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG, 0);
337
338 davinci_i2c_unprepare_recovery(adap);
339 }
340
341 static struct i2c_bus_recovery_info davinci_i2c_scl_recovery_info = {
342 .recover_bus = i2c_generic_scl_recovery,
343 .set_scl = davinci_i2c_set_scl,
344 .get_scl = davinci_i2c_get_scl,
345 .get_sda = davinci_i2c_get_sda,
346 .prepare_recovery = davinci_i2c_scl_prepare_recovery,
347 .unprepare_recovery = davinci_i2c_scl_unprepare_recovery,
348 };
349
350 /*
351 * Waiting for bus not busy
352 */
353 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev)
354 {
355 unsigned long timeout = jiffies + dev->adapter.timeout;
356
357 do {
358 if (!(davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB))
359 return 0;
360 schedule_timeout_uninterruptible(1);
361 } while (time_before_eq(jiffies, timeout));
362
363 dev_warn(dev->dev, "timeout waiting for bus ready\n");
364 i2c_recover_bus(&dev->adapter);
365
366 /*
367 * if bus is still "busy" here, it's most probably a HW problem like
368 * short-circuit
369 */
370 if (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB)
371 return -EIO;
372
373 return 0;
374 }
375
376 /*
377 * Low level master read/write transaction. This function is called
378 * from i2c_davinci_xfer.
379 */
380 static int
381 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
382 {
383 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
384 struct davinci_i2c_platform_data *pdata = dev->pdata;
385 u32 flag;
386 u16 w;
387 unsigned long time_left;
388
389 /* Introduce a delay, required for some boards (e.g Davinci EVM) */
390 if (pdata->bus_delay)
391 udelay(pdata->bus_delay);
392
393 /* set the slave address */
394 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
395
396 dev->buf = msg->buf;
397 dev->buf_len = msg->len;
398 dev->stop = stop;
399
400 davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
401
402 reinit_completion(&dev->cmd_complete);
403 dev->cmd_err = 0;
404
405 /* Take I2C out of reset and configure it as master */
406 flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
407
408 /* if the slave address is ten bit address, enable XA bit */
409 if (msg->flags & I2C_M_TEN)
410 flag |= DAVINCI_I2C_MDR_XA;
411 if (!(msg->flags & I2C_M_RD))
412 flag |= DAVINCI_I2C_MDR_TRX;
413 if (msg->len == 0)
414 flag |= DAVINCI_I2C_MDR_RM;
415
416 /* Enable receive or transmit interrupts */
417 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
418 if (msg->flags & I2C_M_RD)
419 w |= DAVINCI_I2C_IMR_RRDY;
420 else
421 w |= DAVINCI_I2C_IMR_XRDY;
422 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
423
424 dev->terminate = 0;
425
426 /*
427 * Write mode register first as needed for correct behaviour
428 * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
429 * occurring before we have loaded DXR
430 */
431 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
432
433 /*
434 * First byte should be set here, not after interrupt,
435 * because transmit-data-ready interrupt can come before
436 * NACK-interrupt during sending of previous message and
437 * ICDXR may have wrong data
438 * It also saves us one interrupt, slightly faster
439 */
440 if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
441 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
442 dev->buf_len--;
443 }
444
445 /* Set STT to begin transmit now DXR is loaded */
446 flag |= DAVINCI_I2C_MDR_STT;
447 if (stop && msg->len != 0)
448 flag |= DAVINCI_I2C_MDR_STP;
449 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
450
451 time_left = wait_for_completion_timeout(&dev->cmd_complete,
452 dev->adapter.timeout);
453 if (!time_left) {
454 dev_err(dev->dev, "controller timed out\n");
455 i2c_recover_bus(adap);
456 dev->buf_len = 0;
457 return -ETIMEDOUT;
458 }
459 if (dev->buf_len) {
460 /* This should be 0 if all bytes were transferred
461 * or dev->cmd_err denotes an error.
462 */
463 dev_err(dev->dev, "abnormal termination buf_len=%i\n",
464 dev->buf_len);
465 dev->terminate = 1;
466 wmb();
467 dev->buf_len = 0;
468 return -EREMOTEIO;
469 }
470
471 /* no error */
472 if (likely(!dev->cmd_err))
473 return msg->len;
474
475 /* We have an error */
476 if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
477 i2c_davinci_init(dev);
478 return -EIO;
479 }
480
481 if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
482 if (msg->flags & I2C_M_IGNORE_NAK)
483 return msg->len;
484 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
485 w |= DAVINCI_I2C_MDR_STP;
486 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
487 return -EREMOTEIO;
488 }
489 return -EIO;
490 }
491
492 /*
493 * Prepare controller for a transaction and call i2c_davinci_xfer_msg
494 */
495 static int
496 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
497 {
498 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
499 int i;
500 int ret;
501
502 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
503
504 ret = i2c_davinci_wait_bus_not_busy(dev);
505 if (ret < 0) {
506 dev_warn(dev->dev, "timeout waiting for bus ready\n");
507 return ret;
508 }
509
510 for (i = 0; i < num; i++) {
511 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
512 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
513 ret);
514 if (ret < 0)
515 return ret;
516 }
517
518 #ifdef CONFIG_CPU_FREQ
519 complete(&dev->xfr_complete);
520 #endif
521
522 return num;
523 }
524
525 static u32 i2c_davinci_func(struct i2c_adapter *adap)
526 {
527 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
528 }
529
530 static void terminate_read(struct davinci_i2c_dev *dev)
531 {
532 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
533 w |= DAVINCI_I2C_MDR_NACK;
534 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
535
536 /* Throw away data */
537 davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
538 if (!dev->terminate)
539 dev_err(dev->dev, "RDR IRQ while no data requested\n");
540 }
541 static void terminate_write(struct davinci_i2c_dev *dev)
542 {
543 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
544 w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
545 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
546
547 if (!dev->terminate)
548 dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
549 }
550
551 /*
552 * Interrupt service routine. This gets called whenever an I2C interrupt
553 * occurs.
554 */
555 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
556 {
557 struct davinci_i2c_dev *dev = dev_id;
558 u32 stat;
559 int count = 0;
560 u16 w;
561
562 while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
563 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
564 if (count++ == 100) {
565 dev_warn(dev->dev, "Too much work in one IRQ\n");
566 break;
567 }
568
569 switch (stat) {
570 case DAVINCI_I2C_IVR_AL:
571 /* Arbitration lost, must retry */
572 dev->cmd_err |= DAVINCI_I2C_STR_AL;
573 dev->buf_len = 0;
574 complete(&dev->cmd_complete);
575 break;
576
577 case DAVINCI_I2C_IVR_NACK:
578 dev->cmd_err |= DAVINCI_I2C_STR_NACK;
579 dev->buf_len = 0;
580 complete(&dev->cmd_complete);
581 break;
582
583 case DAVINCI_I2C_IVR_ARDY:
584 davinci_i2c_write_reg(dev,
585 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
586 if (((dev->buf_len == 0) && (dev->stop != 0)) ||
587 (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
588 w = davinci_i2c_read_reg(dev,
589 DAVINCI_I2C_MDR_REG);
590 w |= DAVINCI_I2C_MDR_STP;
591 davinci_i2c_write_reg(dev,
592 DAVINCI_I2C_MDR_REG, w);
593 }
594 complete(&dev->cmd_complete);
595 break;
596
597 case DAVINCI_I2C_IVR_RDR:
598 if (dev->buf_len) {
599 *dev->buf++ =
600 davinci_i2c_read_reg(dev,
601 DAVINCI_I2C_DRR_REG);
602 dev->buf_len--;
603 if (dev->buf_len)
604 continue;
605
606 davinci_i2c_write_reg(dev,
607 DAVINCI_I2C_STR_REG,
608 DAVINCI_I2C_IMR_RRDY);
609 } else {
610 /* signal can terminate transfer */
611 terminate_read(dev);
612 }
613 break;
614
615 case DAVINCI_I2C_IVR_XRDY:
616 if (dev->buf_len) {
617 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
618 *dev->buf++);
619 dev->buf_len--;
620 if (dev->buf_len)
621 continue;
622
623 w = davinci_i2c_read_reg(dev,
624 DAVINCI_I2C_IMR_REG);
625 w &= ~DAVINCI_I2C_IMR_XRDY;
626 davinci_i2c_write_reg(dev,
627 DAVINCI_I2C_IMR_REG,
628 w);
629 } else {
630 /* signal can terminate transfer */
631 terminate_write(dev);
632 }
633 break;
634
635 case DAVINCI_I2C_IVR_SCD:
636 davinci_i2c_write_reg(dev,
637 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
638 complete(&dev->cmd_complete);
639 break;
640
641 case DAVINCI_I2C_IVR_AAS:
642 dev_dbg(dev->dev, "Address as slave interrupt\n");
643 break;
644
645 default:
646 dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
647 break;
648 }
649 }
650
651 return count ? IRQ_HANDLED : IRQ_NONE;
652 }
653
654 #ifdef CONFIG_CPU_FREQ
655 static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
656 unsigned long val, void *data)
657 {
658 struct davinci_i2c_dev *dev;
659
660 dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
661 if (val == CPUFREQ_PRECHANGE) {
662 wait_for_completion(&dev->xfr_complete);
663 davinci_i2c_reset_ctrl(dev, 0);
664 } else if (val == CPUFREQ_POSTCHANGE) {
665 i2c_davinci_calc_clk_dividers(dev);
666 davinci_i2c_reset_ctrl(dev, 1);
667 }
668
669 return 0;
670 }
671
672 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
673 {
674 dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
675
676 return cpufreq_register_notifier(&dev->freq_transition,
677 CPUFREQ_TRANSITION_NOTIFIER);
678 }
679
680 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
681 {
682 cpufreq_unregister_notifier(&dev->freq_transition,
683 CPUFREQ_TRANSITION_NOTIFIER);
684 }
685 #else
686 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
687 {
688 return 0;
689 }
690
691 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
692 {
693 }
694 #endif
695
696 static struct i2c_algorithm i2c_davinci_algo = {
697 .master_xfer = i2c_davinci_xfer,
698 .functionality = i2c_davinci_func,
699 };
700
701 static const struct of_device_id davinci_i2c_of_match[] = {
702 {.compatible = "ti,davinci-i2c", },
703 {},
704 };
705 MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);
706
707 static int davinci_i2c_probe(struct platform_device *pdev)
708 {
709 struct davinci_i2c_dev *dev;
710 struct i2c_adapter *adap;
711 struct resource *mem;
712 int r, irq;
713
714 irq = platform_get_irq(pdev, 0);
715 if (irq <= 0) {
716 if (!irq)
717 irq = -ENXIO;
718 if (irq != -EPROBE_DEFER)
719 dev_err(&pdev->dev,
720 "can't get irq resource ret=%d\n", irq);
721 return irq;
722 }
723
724 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev),
725 GFP_KERNEL);
726 if (!dev) {
727 dev_err(&pdev->dev, "Memory allocation failed\n");
728 return -ENOMEM;
729 }
730
731 init_completion(&dev->cmd_complete);
732 #ifdef CONFIG_CPU_FREQ
733 init_completion(&dev->xfr_complete);
734 #endif
735 dev->dev = &pdev->dev;
736 dev->irq = irq;
737 dev->pdata = dev_get_platdata(&pdev->dev);
738 platform_set_drvdata(pdev, dev);
739
740 if (!dev->pdata && pdev->dev.of_node) {
741 u32 prop;
742
743 dev->pdata = devm_kzalloc(&pdev->dev,
744 sizeof(struct davinci_i2c_platform_data), GFP_KERNEL);
745 if (!dev->pdata)
746 return -ENOMEM;
747
748 memcpy(dev->pdata, &davinci_i2c_platform_data_default,
749 sizeof(struct davinci_i2c_platform_data));
750 if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
751 &prop))
752 dev->pdata->bus_freq = prop / 1000;
753
754 dev->pdata->has_pfunc =
755 of_property_read_bool(pdev->dev.of_node,
756 "ti,has-pfunc");
757 } else if (!dev->pdata) {
758 dev->pdata = &davinci_i2c_platform_data_default;
759 }
760
761 dev->clk = devm_clk_get(&pdev->dev, NULL);
762 if (IS_ERR(dev->clk))
763 return -ENODEV;
764 clk_prepare_enable(dev->clk);
765
766 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
767 dev->base = devm_ioremap_resource(&pdev->dev, mem);
768 if (IS_ERR(dev->base)) {
769 r = PTR_ERR(dev->base);
770 goto err_unuse_clocks;
771 }
772
773 i2c_davinci_init(dev);
774
775 r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0,
776 pdev->name, dev);
777 if (r) {
778 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
779 goto err_unuse_clocks;
780 }
781
782 r = i2c_davinci_cpufreq_register(dev);
783 if (r) {
784 dev_err(&pdev->dev, "failed to register cpufreq\n");
785 goto err_unuse_clocks;
786 }
787
788 adap = &dev->adapter;
789 i2c_set_adapdata(adap, dev);
790 adap->owner = THIS_MODULE;
791 adap->class = I2C_CLASS_DEPRECATED;
792 strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
793 adap->algo = &i2c_davinci_algo;
794 adap->dev.parent = &pdev->dev;
795 adap->timeout = DAVINCI_I2C_TIMEOUT;
796 adap->dev.of_node = pdev->dev.of_node;
797
798 if (dev->pdata->has_pfunc)
799 adap->bus_recovery_info = &davinci_i2c_scl_recovery_info;
800 else if (dev->pdata->scl_pin) {
801 adap->bus_recovery_info = &davinci_i2c_gpio_recovery_info;
802 adap->bus_recovery_info->scl_gpio = dev->pdata->scl_pin;
803 adap->bus_recovery_info->sda_gpio = dev->pdata->sda_pin;
804 }
805
806 adap->nr = pdev->id;
807 r = i2c_add_numbered_adapter(adap);
808 if (r) {
809 dev_err(&pdev->dev, "failure adding adapter\n");
810 goto err_unuse_clocks;
811 }
812
813 return 0;
814
815 err_unuse_clocks:
816 clk_disable_unprepare(dev->clk);
817 dev->clk = NULL;
818 return r;
819 }
820
821 static int davinci_i2c_remove(struct platform_device *pdev)
822 {
823 struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
824
825 i2c_davinci_cpufreq_deregister(dev);
826
827 i2c_del_adapter(&dev->adapter);
828
829 clk_disable_unprepare(dev->clk);
830 dev->clk = NULL;
831
832 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
833
834 return 0;
835 }
836
837 #ifdef CONFIG_PM
838 static int davinci_i2c_suspend(struct device *dev)
839 {
840 struct platform_device *pdev = to_platform_device(dev);
841 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
842
843 /* put I2C into reset */
844 davinci_i2c_reset_ctrl(i2c_dev, 0);
845 clk_disable_unprepare(i2c_dev->clk);
846
847 return 0;
848 }
849
850 static int davinci_i2c_resume(struct device *dev)
851 {
852 struct platform_device *pdev = to_platform_device(dev);
853 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
854
855 clk_prepare_enable(i2c_dev->clk);
856 /* take I2C out of reset */
857 davinci_i2c_reset_ctrl(i2c_dev, 1);
858
859 return 0;
860 }
861
862 static const struct dev_pm_ops davinci_i2c_pm = {
863 .suspend = davinci_i2c_suspend,
864 .resume = davinci_i2c_resume,
865 };
866
867 #define davinci_i2c_pm_ops (&davinci_i2c_pm)
868 #else
869 #define davinci_i2c_pm_ops NULL
870 #endif
871
872 /* work with hotplug and coldplug */
873 MODULE_ALIAS("platform:i2c_davinci");
874
875 static struct platform_driver davinci_i2c_driver = {
876 .probe = davinci_i2c_probe,
877 .remove = davinci_i2c_remove,
878 .driver = {
879 .name = "i2c_davinci",
880 .pm = davinci_i2c_pm_ops,
881 .of_match_table = davinci_i2c_of_match,
882 },
883 };
884
885 /* I2C may be needed to bring up other drivers */
886 static int __init davinci_i2c_init_driver(void)
887 {
888 return platform_driver_register(&davinci_i2c_driver);
889 }
890 subsys_initcall(davinci_i2c_init_driver);
891
892 static void __exit davinci_i2c_exit_driver(void)
893 {
894 platform_driver_unregister(&davinci_i2c_driver);
895 }
896 module_exit(davinci_i2c_exit_driver);
897
898 MODULE_AUTHOR("Texas Instruments India");
899 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
900 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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