drivers/i2c/busses/i2c-designware-core.h

   1 /*
   2  * Synopsys DesignWare I2C adapter driver (master only).
   3  *
   4  * Based on the TI DAVINCI I2C adapter driver.
   5  *
   6  * Copyright (C) 2006 Texas Instruments.
   7  * Copyright (C) 2007 MontaVista Software Inc.
   8  * Copyright (C) 2009 Provigent Ltd.
   9  *
  10  * ----------------------------------------------------------------------------
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  * ----------------------------------------------------------------------------
  22  *
  23  */
  24
  25
  26 #define DW_IC_CON_MASTER                0x1
  27 #define DW_IC_CON_SPEED_STD             0x2
  28 #define DW_IC_CON_SPEED_FAST            0x4
  29 #define DW_IC_CON_10BITADDR_MASTER      0x10
  30 #define DW_IC_CON_RESTART_EN            0x20
  31 #define DW_IC_CON_SLAVE_DISABLE         0x40
  32
  33
  34 /**
  35  * struct dw_i2c_dev - private i2c-designware data
  36  * @dev: driver model device node
  37  * @base: IO registers pointer
  38  * @cmd_complete: tx completion indicator
  39  * @clk: input reference clock
  40  * @cmd_err: run time hadware error code
  41  * @msgs: points to an array of messages currently being transfered
  42  * @msgs_num: the number of elements in msgs
  43  * @msg_write_idx: the element index of the current tx message in the msgs
  44  *      array
  45  * @tx_buf_len: the length of the current tx buffer
  46  * @tx_buf: the current tx buffer
  47  * @msg_read_idx: the element index of the current rx message in the msgs
  48  *      array
  49  * @rx_buf_len: the length of the current rx buffer
  50  * @rx_buf: the current rx buffer
  51  * @msg_err: error status of the current transfer
  52  * @status: i2c master status, one of STATUS_*
  53  * @abort_source: copy of the TX_ABRT_SOURCE register
  54  * @irq: interrupt number for the i2c master
  55  * @adapter: i2c subsystem adapter node
  56  * @tx_fifo_depth: depth of the hardware tx fifo
  57  * @rx_fifo_depth: depth of the hardware rx fifo
  58  * @rx_outstanding: current master-rx elements in tx fifo
  59  * @ss_hcnt: standard speed HCNT value
  60  * @ss_lcnt: standard speed LCNT value
  61  * @fs_hcnt: fast speed HCNT value
  62  * @fs_lcnt: fast speed LCNT value
  63  * @acquire_lock: function to acquire a hardware lock on the bus
  64  * @release_lock: function to release a hardware lock on the bus
  65  * @pm_runtime_disabled: true if pm runtime is disabled
  66  *
  67  * HCNT and LCNT parameters can be used if the platform knows more accurate
  68  * values than the one computed based only on the input clock frequency.
  69  * Leave them to be %0 if not used.
  70  */
  71 struct dw_i2c_dev {
  72         struct device           *dev;
  73         void __iomem            *base;
  74         struct completion       cmd_complete;
  75         struct clk              *clk;
  76         u32                     (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
  77         struct dw_pci_controller *controller;
  78         int                     cmd_err;
  79         struct i2c_msg          *msgs;
  80         int                     msgs_num;
  81         int                     msg_write_idx;
  82         u32                     tx_buf_len;
  83         u8                      *tx_buf;
  84         int                     msg_read_idx;
  85         u32                     rx_buf_len;
  86         u8                      *rx_buf;
  87         int                     msg_err;
  88         unsigned int            status;
  89         u32                     abort_source;
  90         int                     irq;
  91         u32                     accessor_flags;
  92         struct i2c_adapter      adapter;
  93         u32                     functionality;
  94         u32                     master_cfg;
  95         unsigned int            tx_fifo_depth;
  96         unsigned int            rx_fifo_depth;
  97         int                     rx_outstanding;
  98         u32                     sda_hold_time;
  99         u32                     sda_falling_time;
 100         u32                     scl_falling_time;
 101         u16                     ss_hcnt;
 102         u16                     ss_lcnt;
 103         u16                     fs_hcnt;
 104         u16                     fs_lcnt;
 105         int                     (*acquire_lock)(struct dw_i2c_dev *dev);
 106         void                    (*release_lock)(struct dw_i2c_dev *dev);
 107         bool                    pm_runtime_disabled;
 108 };
 109
 110 #define ACCESS_SWAP             0x00000001
 111 #define ACCESS_16BIT            0x00000002
 112 #define ACCESS_INTR_MASK        0x00000004
 113
 114 extern int i2c_dw_init(struct dw_i2c_dev *dev);
 115 extern void i2c_dw_disable(struct dw_i2c_dev *dev);
 116 extern void i2c_dw_disable_int(struct dw_i2c_dev *dev);
 117 extern u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev);
 118 extern int i2c_dw_probe(struct dw_i2c_dev *dev);
 119
 120 #if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL)
 121 extern int i2c_dw_eval_lock_support(struct dw_i2c_dev *dev);
 122 #else
 123 static inline int i2c_dw_eval_lock_support(struct dw_i2c_dev *dev) { return 0; }
 124 #endif