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Merge tag 'master-2014-11-25' of git://git.kernel.org/pub/scm/linux/kernel/git/linvil...
[deliverable/linux.git] / drivers / i2c / busses / i2c-i801.c
1 /*
2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com>
5 Copyright (C) 2007 - 2012 Jean Delvare <jdelvare@suse.de>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18 */
19
20 /*
21 * Supports the following Intel I/O Controller Hubs (ICH):
22 *
23 * I/O Block I2C
24 * region SMBus Block proc. block
25 * Chip name PCI ID size PEC buffer call read
26 * ---------------------------------------------------------------------------
27 * 82801AA (ICH) 0x2413 16 no no no no
28 * 82801AB (ICH0) 0x2423 16 no no no no
29 * 82801BA (ICH2) 0x2443 16 no no no no
30 * 82801CA (ICH3) 0x2483 32 soft no no no
31 * 82801DB (ICH4) 0x24c3 32 hard yes no no
32 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
33 * 6300ESB 0x25a4 32 hard yes yes yes
34 * 82801F (ICH6) 0x266a 32 hard yes yes yes
35 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
36 * 82801G (ICH7) 0x27da 32 hard yes yes yes
37 * 82801H (ICH8) 0x283e 32 hard yes yes yes
38 * 82801I (ICH9) 0x2930 32 hard yes yes yes
39 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
40 * ICH10 0x3a30 32 hard yes yes yes
41 * ICH10 0x3a60 32 hard yes yes yes
42 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
43 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
44 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
45 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
46 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
47 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
48 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
49 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
50 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
51 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
52 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
53 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
54 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
55 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
56 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
57 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
58 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
59 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
60 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
61 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
62 *
63 * Features supported by this driver:
64 * Software PEC no
65 * Hardware PEC yes
66 * Block buffer yes
67 * Block process call transaction no
68 * I2C block read transaction yes (doesn't use the block buffer)
69 * Slave mode no
70 * Interrupt processing yes
71 *
72 * See the file Documentation/i2c/busses/i2c-i801 for details.
73 */
74
75 #include <linux/interrupt.h>
76 #include <linux/module.h>
77 #include <linux/pci.h>
78 #include <linux/kernel.h>
79 #include <linux/stddef.h>
80 #include <linux/delay.h>
81 #include <linux/ioport.h>
82 #include <linux/init.h>
83 #include <linux/i2c.h>
84 #include <linux/acpi.h>
85 #include <linux/io.h>
86 #include <linux/dmi.h>
87 #include <linux/slab.h>
88 #include <linux/wait.h>
89 #include <linux/err.h>
90
91 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
92 defined CONFIG_DMI
93 #include <linux/gpio.h>
94 #include <linux/i2c-mux-gpio.h>
95 #include <linux/platform_device.h>
96 #endif
97
98 /* I801 SMBus address offsets */
99 #define SMBHSTSTS(p) (0 + (p)->smba)
100 #define SMBHSTCNT(p) (2 + (p)->smba)
101 #define SMBHSTCMD(p) (3 + (p)->smba)
102 #define SMBHSTADD(p) (4 + (p)->smba)
103 #define SMBHSTDAT0(p) (5 + (p)->smba)
104 #define SMBHSTDAT1(p) (6 + (p)->smba)
105 #define SMBBLKDAT(p) (7 + (p)->smba)
106 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
107 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
108 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
109
110 /* PCI Address Constants */
111 #define SMBBAR 4
112 #define SMBPCISTS 0x006
113 #define SMBHSTCFG 0x040
114
115 /* Host status bits for SMBPCISTS */
116 #define SMBPCISTS_INTS 0x08
117
118 /* Host configuration bits for SMBHSTCFG */
119 #define SMBHSTCFG_HST_EN 1
120 #define SMBHSTCFG_SMB_SMI_EN 2
121 #define SMBHSTCFG_I2C_EN 4
122
123 /* Auxiliary control register bits, ICH4+ only */
124 #define SMBAUXCTL_CRC 1
125 #define SMBAUXCTL_E32B 2
126
127 /* Other settings */
128 #define MAX_RETRIES 400
129
130 /* I801 command constants */
131 #define I801_QUICK 0x00
132 #define I801_BYTE 0x04
133 #define I801_BYTE_DATA 0x08
134 #define I801_WORD_DATA 0x0C
135 #define I801_PROC_CALL 0x10 /* unimplemented */
136 #define I801_BLOCK_DATA 0x14
137 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
138
139 /* I801 Host Control register bits */
140 #define SMBHSTCNT_INTREN 0x01
141 #define SMBHSTCNT_KILL 0x02
142 #define SMBHSTCNT_LAST_BYTE 0x20
143 #define SMBHSTCNT_START 0x40
144 #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
145
146 /* I801 Hosts Status register bits */
147 #define SMBHSTSTS_BYTE_DONE 0x80
148 #define SMBHSTSTS_INUSE_STS 0x40
149 #define SMBHSTSTS_SMBALERT_STS 0x20
150 #define SMBHSTSTS_FAILED 0x10
151 #define SMBHSTSTS_BUS_ERR 0x08
152 #define SMBHSTSTS_DEV_ERR 0x04
153 #define SMBHSTSTS_INTR 0x02
154 #define SMBHSTSTS_HOST_BUSY 0x01
155
156 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
157 SMBHSTSTS_DEV_ERR)
158
159 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
160 STATUS_ERROR_FLAGS)
161
162 /* Older devices have their ID defined in <linux/pci_ids.h> */
163 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
164 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
165 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
166 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
167 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
168 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
169 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
170 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
171 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
172 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
173 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
174 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
175 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
176 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
177 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
178 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
179 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
180 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
181 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
182 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
183 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
184 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
185
186 struct i801_mux_config {
187 char *gpio_chip;
188 unsigned values[3];
189 int n_values;
190 unsigned classes[3];
191 unsigned gpios[2]; /* Relative to gpio_chip->base */
192 int n_gpios;
193 };
194
195 struct i801_priv {
196 struct i2c_adapter adapter;
197 unsigned long smba;
198 unsigned char original_hstcfg;
199 struct pci_dev *pci_dev;
200 unsigned int features;
201
202 /* isr processing */
203 wait_queue_head_t waitq;
204 u8 status;
205
206 /* Command state used by isr for byte-by-byte block transactions */
207 u8 cmd;
208 bool is_read;
209 int count;
210 int len;
211 u8 *data;
212
213 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
214 defined CONFIG_DMI
215 const struct i801_mux_config *mux_drvdata;
216 struct platform_device *mux_pdev;
217 #endif
218 };
219
220 static struct pci_driver i801_driver;
221
222 #define FEATURE_SMBUS_PEC (1 << 0)
223 #define FEATURE_BLOCK_BUFFER (1 << 1)
224 #define FEATURE_BLOCK_PROC (1 << 2)
225 #define FEATURE_I2C_BLOCK_READ (1 << 3)
226 #define FEATURE_IRQ (1 << 4)
227 /* Not really a feature, but it's convenient to handle it as such */
228 #define FEATURE_IDF (1 << 15)
229
230 static const char *i801_feature_names[] = {
231 "SMBus PEC",
232 "Block buffer",
233 "Block process call",
234 "I2C block read",
235 "Interrupt",
236 };
237
238 static unsigned int disable_features;
239 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
240 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
241 "\t\t 0x01 disable SMBus PEC\n"
242 "\t\t 0x02 disable the block buffer\n"
243 "\t\t 0x08 disable the I2C block read functionality\n"
244 "\t\t 0x10 don't use interrupts ");
245
246 /* Make sure the SMBus host is ready to start transmitting.
247 Return 0 if it is, -EBUSY if it is not. */
248 static int i801_check_pre(struct i801_priv *priv)
249 {
250 int status;
251
252 status = inb_p(SMBHSTSTS(priv));
253 if (status & SMBHSTSTS_HOST_BUSY) {
254 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
255 return -EBUSY;
256 }
257
258 status &= STATUS_FLAGS;
259 if (status) {
260 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
261 status);
262 outb_p(status, SMBHSTSTS(priv));
263 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
264 if (status) {
265 dev_err(&priv->pci_dev->dev,
266 "Failed clearing status flags (%02x)\n",
267 status);
268 return -EBUSY;
269 }
270 }
271
272 return 0;
273 }
274
275 /*
276 * Convert the status register to an error code, and clear it.
277 * Note that status only contains the bits we want to clear, not the
278 * actual register value.
279 */
280 static int i801_check_post(struct i801_priv *priv, int status)
281 {
282 int result = 0;
283
284 /*
285 * If the SMBus is still busy, we give up
286 * Note: This timeout condition only happens when using polling
287 * transactions. For interrupt operation, NAK/timeout is indicated by
288 * DEV_ERR.
289 */
290 if (unlikely(status < 0)) {
291 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
292 /* try to stop the current command */
293 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
294 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
295 SMBHSTCNT(priv));
296 usleep_range(1000, 2000);
297 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
298 SMBHSTCNT(priv));
299
300 /* Check if it worked */
301 status = inb_p(SMBHSTSTS(priv));
302 if ((status & SMBHSTSTS_HOST_BUSY) ||
303 !(status & SMBHSTSTS_FAILED))
304 dev_err(&priv->pci_dev->dev,
305 "Failed terminating the transaction\n");
306 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
307 return -ETIMEDOUT;
308 }
309
310 if (status & SMBHSTSTS_FAILED) {
311 result = -EIO;
312 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
313 }
314 if (status & SMBHSTSTS_DEV_ERR) {
315 result = -ENXIO;
316 dev_dbg(&priv->pci_dev->dev, "No response\n");
317 }
318 if (status & SMBHSTSTS_BUS_ERR) {
319 result = -EAGAIN;
320 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
321 }
322
323 /* Clear status flags except BYTE_DONE, to be cleared by caller */
324 outb_p(status, SMBHSTSTS(priv));
325
326 return result;
327 }
328
329 /* Wait for BUSY being cleared and either INTR or an error flag being set */
330 static int i801_wait_intr(struct i801_priv *priv)
331 {
332 int timeout = 0;
333 int status;
334
335 /* We will always wait for a fraction of a second! */
336 do {
337 usleep_range(250, 500);
338 status = inb_p(SMBHSTSTS(priv));
339 } while (((status & SMBHSTSTS_HOST_BUSY) ||
340 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
341 (timeout++ < MAX_RETRIES));
342
343 if (timeout > MAX_RETRIES) {
344 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
345 return -ETIMEDOUT;
346 }
347 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
348 }
349
350 /* Wait for either BYTE_DONE or an error flag being set */
351 static int i801_wait_byte_done(struct i801_priv *priv)
352 {
353 int timeout = 0;
354 int status;
355
356 /* We will always wait for a fraction of a second! */
357 do {
358 usleep_range(250, 500);
359 status = inb_p(SMBHSTSTS(priv));
360 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
361 (timeout++ < MAX_RETRIES));
362
363 if (timeout > MAX_RETRIES) {
364 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
365 return -ETIMEDOUT;
366 }
367 return status & STATUS_ERROR_FLAGS;
368 }
369
370 static int i801_transaction(struct i801_priv *priv, int xact)
371 {
372 int status;
373 int result;
374
375 result = i801_check_pre(priv);
376 if (result < 0)
377 return result;
378
379 if (priv->features & FEATURE_IRQ) {
380 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
381 SMBHSTCNT(priv));
382 wait_event(priv->waitq, (status = priv->status));
383 priv->status = 0;
384 return i801_check_post(priv, status);
385 }
386
387 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
388 * SMBSCMD are passed in xact */
389 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
390
391 status = i801_wait_intr(priv);
392 return i801_check_post(priv, status);
393 }
394
395 static int i801_block_transaction_by_block(struct i801_priv *priv,
396 union i2c_smbus_data *data,
397 char read_write, int hwpec)
398 {
399 int i, len;
400 int status;
401
402 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
403
404 /* Use 32-byte buffer to process this transaction */
405 if (read_write == I2C_SMBUS_WRITE) {
406 len = data->block[0];
407 outb_p(len, SMBHSTDAT0(priv));
408 for (i = 0; i < len; i++)
409 outb_p(data->block[i+1], SMBBLKDAT(priv));
410 }
411
412 status = i801_transaction(priv, I801_BLOCK_DATA |
413 (hwpec ? SMBHSTCNT_PEC_EN : 0));
414 if (status)
415 return status;
416
417 if (read_write == I2C_SMBUS_READ) {
418 len = inb_p(SMBHSTDAT0(priv));
419 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
420 return -EPROTO;
421
422 data->block[0] = len;
423 for (i = 0; i < len; i++)
424 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
425 }
426 return 0;
427 }
428
429 static void i801_isr_byte_done(struct i801_priv *priv)
430 {
431 if (priv->is_read) {
432 /* For SMBus block reads, length is received with first byte */
433 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
434 (priv->count == 0)) {
435 priv->len = inb_p(SMBHSTDAT0(priv));
436 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
437 dev_err(&priv->pci_dev->dev,
438 "Illegal SMBus block read size %d\n",
439 priv->len);
440 /* FIXME: Recover */
441 priv->len = I2C_SMBUS_BLOCK_MAX;
442 } else {
443 dev_dbg(&priv->pci_dev->dev,
444 "SMBus block read size is %d\n",
445 priv->len);
446 }
447 priv->data[-1] = priv->len;
448 }
449
450 /* Read next byte */
451 if (priv->count < priv->len)
452 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
453 else
454 dev_dbg(&priv->pci_dev->dev,
455 "Discarding extra byte on block read\n");
456
457 /* Set LAST_BYTE for last byte of read transaction */
458 if (priv->count == priv->len - 1)
459 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
460 SMBHSTCNT(priv));
461 } else if (priv->count < priv->len - 1) {
462 /* Write next byte, except for IRQ after last byte */
463 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
464 }
465
466 /* Clear BYTE_DONE to continue with next byte */
467 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
468 }
469
470 /*
471 * There are two kinds of interrupts:
472 *
473 * 1) i801 signals transaction completion with one of these interrupts:
474 * INTR - Success
475 * DEV_ERR - Invalid command, NAK or communication timeout
476 * BUS_ERR - SMI# transaction collision
477 * FAILED - transaction was canceled due to a KILL request
478 * When any of these occur, update ->status and wake up the waitq.
479 * ->status must be cleared before kicking off the next transaction.
480 *
481 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
482 * occurs for each byte of a byte-by-byte to prepare the next byte.
483 */
484 static irqreturn_t i801_isr(int irq, void *dev_id)
485 {
486 struct i801_priv *priv = dev_id;
487 u16 pcists;
488 u8 status;
489
490 /* Confirm this is our interrupt */
491 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
492 if (!(pcists & SMBPCISTS_INTS))
493 return IRQ_NONE;
494
495 status = inb_p(SMBHSTSTS(priv));
496 if (status != 0x42)
497 dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status);
498
499 if (status & SMBHSTSTS_BYTE_DONE)
500 i801_isr_byte_done(priv);
501
502 /*
503 * Clear irq sources and report transaction result.
504 * ->status must be cleared before the next transaction is started.
505 */
506 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
507 if (status) {
508 outb_p(status, SMBHSTSTS(priv));
509 priv->status |= status;
510 wake_up(&priv->waitq);
511 }
512
513 return IRQ_HANDLED;
514 }
515
516 /*
517 * For "byte-by-byte" block transactions:
518 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
519 * I2C read uses cmd=I801_I2C_BLOCK_DATA
520 */
521 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
522 union i2c_smbus_data *data,
523 char read_write, int command,
524 int hwpec)
525 {
526 int i, len;
527 int smbcmd;
528 int status;
529 int result;
530
531 result = i801_check_pre(priv);
532 if (result < 0)
533 return result;
534
535 len = data->block[0];
536
537 if (read_write == I2C_SMBUS_WRITE) {
538 outb_p(len, SMBHSTDAT0(priv));
539 outb_p(data->block[1], SMBBLKDAT(priv));
540 }
541
542 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
543 read_write == I2C_SMBUS_READ)
544 smbcmd = I801_I2C_BLOCK_DATA;
545 else
546 smbcmd = I801_BLOCK_DATA;
547
548 if (priv->features & FEATURE_IRQ) {
549 priv->is_read = (read_write == I2C_SMBUS_READ);
550 if (len == 1 && priv->is_read)
551 smbcmd |= SMBHSTCNT_LAST_BYTE;
552 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
553 priv->len = len;
554 priv->count = 0;
555 priv->data = &data->block[1];
556
557 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
558 wait_event(priv->waitq, (status = priv->status));
559 priv->status = 0;
560 return i801_check_post(priv, status);
561 }
562
563 for (i = 1; i <= len; i++) {
564 if (i == len && read_write == I2C_SMBUS_READ)
565 smbcmd |= SMBHSTCNT_LAST_BYTE;
566 outb_p(smbcmd, SMBHSTCNT(priv));
567
568 if (i == 1)
569 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
570 SMBHSTCNT(priv));
571
572 status = i801_wait_byte_done(priv);
573 if (status)
574 goto exit;
575
576 if (i == 1 && read_write == I2C_SMBUS_READ
577 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
578 len = inb_p(SMBHSTDAT0(priv));
579 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
580 dev_err(&priv->pci_dev->dev,
581 "Illegal SMBus block read size %d\n",
582 len);
583 /* Recover */
584 while (inb_p(SMBHSTSTS(priv)) &
585 SMBHSTSTS_HOST_BUSY)
586 outb_p(SMBHSTSTS_BYTE_DONE,
587 SMBHSTSTS(priv));
588 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
589 return -EPROTO;
590 }
591 data->block[0] = len;
592 }
593
594 /* Retrieve/store value in SMBBLKDAT */
595 if (read_write == I2C_SMBUS_READ)
596 data->block[i] = inb_p(SMBBLKDAT(priv));
597 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
598 outb_p(data->block[i+1], SMBBLKDAT(priv));
599
600 /* signals SMBBLKDAT ready */
601 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
602 }
603
604 status = i801_wait_intr(priv);
605 exit:
606 return i801_check_post(priv, status);
607 }
608
609 static int i801_set_block_buffer_mode(struct i801_priv *priv)
610 {
611 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
612 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
613 return -EIO;
614 return 0;
615 }
616
617 /* Block transaction function */
618 static int i801_block_transaction(struct i801_priv *priv,
619 union i2c_smbus_data *data, char read_write,
620 int command, int hwpec)
621 {
622 int result = 0;
623 unsigned char hostc;
624
625 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
626 if (read_write == I2C_SMBUS_WRITE) {
627 /* set I2C_EN bit in configuration register */
628 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
629 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
630 hostc | SMBHSTCFG_I2C_EN);
631 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
632 dev_err(&priv->pci_dev->dev,
633 "I2C block read is unsupported!\n");
634 return -EOPNOTSUPP;
635 }
636 }
637
638 if (read_write == I2C_SMBUS_WRITE
639 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
640 if (data->block[0] < 1)
641 data->block[0] = 1;
642 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
643 data->block[0] = I2C_SMBUS_BLOCK_MAX;
644 } else {
645 data->block[0] = 32; /* max for SMBus block reads */
646 }
647
648 /* Experience has shown that the block buffer can only be used for
649 SMBus (not I2C) block transactions, even though the datasheet
650 doesn't mention this limitation. */
651 if ((priv->features & FEATURE_BLOCK_BUFFER)
652 && command != I2C_SMBUS_I2C_BLOCK_DATA
653 && i801_set_block_buffer_mode(priv) == 0)
654 result = i801_block_transaction_by_block(priv, data,
655 read_write, hwpec);
656 else
657 result = i801_block_transaction_byte_by_byte(priv, data,
658 read_write,
659 command, hwpec);
660
661 if (command == I2C_SMBUS_I2C_BLOCK_DATA
662 && read_write == I2C_SMBUS_WRITE) {
663 /* restore saved configuration register value */
664 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
665 }
666 return result;
667 }
668
669 /* Return negative errno on error. */
670 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
671 unsigned short flags, char read_write, u8 command,
672 int size, union i2c_smbus_data *data)
673 {
674 int hwpec;
675 int block = 0;
676 int ret, xact = 0;
677 struct i801_priv *priv = i2c_get_adapdata(adap);
678
679 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
680 && size != I2C_SMBUS_QUICK
681 && size != I2C_SMBUS_I2C_BLOCK_DATA;
682
683 switch (size) {
684 case I2C_SMBUS_QUICK:
685 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
686 SMBHSTADD(priv));
687 xact = I801_QUICK;
688 break;
689 case I2C_SMBUS_BYTE:
690 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
691 SMBHSTADD(priv));
692 if (read_write == I2C_SMBUS_WRITE)
693 outb_p(command, SMBHSTCMD(priv));
694 xact = I801_BYTE;
695 break;
696 case I2C_SMBUS_BYTE_DATA:
697 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
698 SMBHSTADD(priv));
699 outb_p(command, SMBHSTCMD(priv));
700 if (read_write == I2C_SMBUS_WRITE)
701 outb_p(data->byte, SMBHSTDAT0(priv));
702 xact = I801_BYTE_DATA;
703 break;
704 case I2C_SMBUS_WORD_DATA:
705 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
706 SMBHSTADD(priv));
707 outb_p(command, SMBHSTCMD(priv));
708 if (read_write == I2C_SMBUS_WRITE) {
709 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
710 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
711 }
712 xact = I801_WORD_DATA;
713 break;
714 case I2C_SMBUS_BLOCK_DATA:
715 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
716 SMBHSTADD(priv));
717 outb_p(command, SMBHSTCMD(priv));
718 block = 1;
719 break;
720 case I2C_SMBUS_I2C_BLOCK_DATA:
721 /* NB: page 240 of ICH5 datasheet shows that the R/#W
722 * bit should be cleared here, even when reading */
723 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
724 if (read_write == I2C_SMBUS_READ) {
725 /* NB: page 240 of ICH5 datasheet also shows
726 * that DATA1 is the cmd field when reading */
727 outb_p(command, SMBHSTDAT1(priv));
728 } else
729 outb_p(command, SMBHSTCMD(priv));
730 block = 1;
731 break;
732 default:
733 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
734 size);
735 return -EOPNOTSUPP;
736 }
737
738 if (hwpec) /* enable/disable hardware PEC */
739 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
740 else
741 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
742 SMBAUXCTL(priv));
743
744 if (block)
745 ret = i801_block_transaction(priv, data, read_write, size,
746 hwpec);
747 else
748 ret = i801_transaction(priv, xact);
749
750 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
751 time, so we forcibly disable it after every transaction. Turn off
752 E32B for the same reason. */
753 if (hwpec || block)
754 outb_p(inb_p(SMBAUXCTL(priv)) &
755 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
756
757 if (block)
758 return ret;
759 if (ret)
760 return ret;
761 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
762 return 0;
763
764 switch (xact & 0x7f) {
765 case I801_BYTE: /* Result put in SMBHSTDAT0 */
766 case I801_BYTE_DATA:
767 data->byte = inb_p(SMBHSTDAT0(priv));
768 break;
769 case I801_WORD_DATA:
770 data->word = inb_p(SMBHSTDAT0(priv)) +
771 (inb_p(SMBHSTDAT1(priv)) << 8);
772 break;
773 }
774 return 0;
775 }
776
777
778 static u32 i801_func(struct i2c_adapter *adapter)
779 {
780 struct i801_priv *priv = i2c_get_adapdata(adapter);
781
782 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
783 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
784 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
785 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
786 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
787 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
788 }
789
790 static const struct i2c_algorithm smbus_algorithm = {
791 .smbus_xfer = i801_access,
792 .functionality = i801_func,
793 };
794
795 static const struct pci_device_id i801_ids[] = {
796 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
797 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
798 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
799 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
800 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
801 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
802 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
803 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
804 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
805 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
806 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
807 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
808 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
809 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
810 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
811 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
812 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
813 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
814 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
815 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
816 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
817 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
818 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
819 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
820 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
821 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
822 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
823 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
824 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
825 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
826 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
827 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
828 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
829 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
830 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
831 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
832 { 0, }
833 };
834
835 MODULE_DEVICE_TABLE(pci, i801_ids);
836
837 #if defined CONFIG_X86 && defined CONFIG_DMI
838 static unsigned char apanel_addr;
839
840 /* Scan the system ROM for the signature "FJKEYINF" */
841 static __init const void __iomem *bios_signature(const void __iomem *bios)
842 {
843 ssize_t offset;
844 const unsigned char signature[] = "FJKEYINF";
845
846 for (offset = 0; offset < 0x10000; offset += 0x10) {
847 if (check_signature(bios + offset, signature,
848 sizeof(signature)-1))
849 return bios + offset;
850 }
851 return NULL;
852 }
853
854 static void __init input_apanel_init(void)
855 {
856 void __iomem *bios;
857 const void __iomem *p;
858
859 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
860 p = bios_signature(bios);
861 if (p) {
862 /* just use the first address */
863 apanel_addr = readb(p + 8 + 3) >> 1;
864 }
865 iounmap(bios);
866 }
867
868 struct dmi_onboard_device_info {
869 const char *name;
870 u8 type;
871 unsigned short i2c_addr;
872 const char *i2c_type;
873 };
874
875 static const struct dmi_onboard_device_info dmi_devices[] = {
876 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
877 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
878 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
879 };
880
881 static void dmi_check_onboard_device(u8 type, const char *name,
882 struct i2c_adapter *adap)
883 {
884 int i;
885 struct i2c_board_info info;
886
887 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
888 /* & ~0x80, ignore enabled/disabled bit */
889 if ((type & ~0x80) != dmi_devices[i].type)
890 continue;
891 if (strcasecmp(name, dmi_devices[i].name))
892 continue;
893
894 memset(&info, 0, sizeof(struct i2c_board_info));
895 info.addr = dmi_devices[i].i2c_addr;
896 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
897 i2c_new_device(adap, &info);
898 break;
899 }
900 }
901
902 /* We use our own function to check for onboard devices instead of
903 dmi_find_device() as some buggy BIOS's have the devices we are interested
904 in marked as disabled */
905 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
906 {
907 int i, count;
908
909 if (dm->type != 10)
910 return;
911
912 count = (dm->length - sizeof(struct dmi_header)) / 2;
913 for (i = 0; i < count; i++) {
914 const u8 *d = (char *)(dm + 1) + (i * 2);
915 const char *name = ((char *) dm) + dm->length;
916 u8 type = d[0];
917 u8 s = d[1];
918
919 if (!s)
920 continue;
921 s--;
922 while (s > 0 && name[0]) {
923 name += strlen(name) + 1;
924 s--;
925 }
926 if (name[0] == 0) /* Bogus string reference */
927 continue;
928
929 dmi_check_onboard_device(type, name, adap);
930 }
931 }
932
933 /* Register optional slaves */
934 static void i801_probe_optional_slaves(struct i801_priv *priv)
935 {
936 /* Only register slaves on main SMBus channel */
937 if (priv->features & FEATURE_IDF)
938 return;
939
940 if (apanel_addr) {
941 struct i2c_board_info info;
942
943 memset(&info, 0, sizeof(struct i2c_board_info));
944 info.addr = apanel_addr;
945 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
946 i2c_new_device(&priv->adapter, &info);
947 }
948
949 if (dmi_name_in_vendors("FUJITSU"))
950 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
951 }
952 #else
953 static void __init input_apanel_init(void) {}
954 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
955 #endif /* CONFIG_X86 && CONFIG_DMI */
956
957 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
958 defined CONFIG_DMI
959 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
960 .gpio_chip = "gpio_ich",
961 .values = { 0x02, 0x03 },
962 .n_values = 2,
963 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
964 .gpios = { 52, 53 },
965 .n_gpios = 2,
966 };
967
968 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
969 .gpio_chip = "gpio_ich",
970 .values = { 0x02, 0x03, 0x01 },
971 .n_values = 3,
972 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
973 .gpios = { 52, 53 },
974 .n_gpios = 2,
975 };
976
977 static const struct dmi_system_id mux_dmi_table[] = {
978 {
979 .matches = {
980 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
981 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
982 },
983 .driver_data = &i801_mux_config_asus_z8_d12,
984 },
985 {
986 .matches = {
987 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
988 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
989 },
990 .driver_data = &i801_mux_config_asus_z8_d12,
991 },
992 {
993 .matches = {
994 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
995 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
996 },
997 .driver_data = &i801_mux_config_asus_z8_d12,
998 },
999 {
1000 .matches = {
1001 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1002 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1003 },
1004 .driver_data = &i801_mux_config_asus_z8_d12,
1005 },
1006 {
1007 .matches = {
1008 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1009 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1010 },
1011 .driver_data = &i801_mux_config_asus_z8_d12,
1012 },
1013 {
1014 .matches = {
1015 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1016 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1017 },
1018 .driver_data = &i801_mux_config_asus_z8_d12,
1019 },
1020 {
1021 .matches = {
1022 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1023 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1024 },
1025 .driver_data = &i801_mux_config_asus_z8_d18,
1026 },
1027 {
1028 .matches = {
1029 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1030 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1031 },
1032 .driver_data = &i801_mux_config_asus_z8_d18,
1033 },
1034 {
1035 .matches = {
1036 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1037 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1038 },
1039 .driver_data = &i801_mux_config_asus_z8_d12,
1040 },
1041 { }
1042 };
1043
1044 /* Setup multiplexing if needed */
1045 static int i801_add_mux(struct i801_priv *priv)
1046 {
1047 struct device *dev = &priv->adapter.dev;
1048 const struct i801_mux_config *mux_config;
1049 struct i2c_mux_gpio_platform_data gpio_data;
1050 int err;
1051
1052 if (!priv->mux_drvdata)
1053 return 0;
1054 mux_config = priv->mux_drvdata;
1055
1056 /* Prepare the platform data */
1057 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1058 gpio_data.parent = priv->adapter.nr;
1059 gpio_data.values = mux_config->values;
1060 gpio_data.n_values = mux_config->n_values;
1061 gpio_data.classes = mux_config->classes;
1062 gpio_data.gpio_chip = mux_config->gpio_chip;
1063 gpio_data.gpios = mux_config->gpios;
1064 gpio_data.n_gpios = mux_config->n_gpios;
1065 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1066
1067 /* Register the mux device */
1068 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1069 PLATFORM_DEVID_AUTO, &gpio_data,
1070 sizeof(struct i2c_mux_gpio_platform_data));
1071 if (IS_ERR(priv->mux_pdev)) {
1072 err = PTR_ERR(priv->mux_pdev);
1073 priv->mux_pdev = NULL;
1074 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1075 return err;
1076 }
1077
1078 return 0;
1079 }
1080
1081 static void i801_del_mux(struct i801_priv *priv)
1082 {
1083 if (priv->mux_pdev)
1084 platform_device_unregister(priv->mux_pdev);
1085 }
1086
1087 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1088 {
1089 const struct dmi_system_id *id;
1090 const struct i801_mux_config *mux_config;
1091 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1092 int i;
1093
1094 id = dmi_first_match(mux_dmi_table);
1095 if (id) {
1096 /* Remove branch classes from trunk */
1097 mux_config = id->driver_data;
1098 for (i = 0; i < mux_config->n_values; i++)
1099 class &= ~mux_config->classes[i];
1100
1101 /* Remember for later */
1102 priv->mux_drvdata = mux_config;
1103 }
1104
1105 return class;
1106 }
1107 #else
1108 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1109 static inline void i801_del_mux(struct i801_priv *priv) { }
1110
1111 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1112 {
1113 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1114 }
1115 #endif
1116
1117 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1118 {
1119 unsigned char temp;
1120 int err, i;
1121 struct i801_priv *priv;
1122
1123 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1124 if (!priv)
1125 return -ENOMEM;
1126
1127 i2c_set_adapdata(&priv->adapter, priv);
1128 priv->adapter.owner = THIS_MODULE;
1129 priv->adapter.class = i801_get_adapter_class(priv);
1130 priv->adapter.algo = &smbus_algorithm;
1131
1132 priv->pci_dev = dev;
1133 switch (dev->device) {
1134 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1135 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1136 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1137 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1138 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1139 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1140 priv->features |= FEATURE_IDF;
1141 /* fall through */
1142 default:
1143 priv->features |= FEATURE_I2C_BLOCK_READ;
1144 priv->features |= FEATURE_IRQ;
1145 /* fall through */
1146 case PCI_DEVICE_ID_INTEL_82801DB_3:
1147 priv->features |= FEATURE_SMBUS_PEC;
1148 priv->features |= FEATURE_BLOCK_BUFFER;
1149 /* fall through */
1150 case PCI_DEVICE_ID_INTEL_82801CA_3:
1151 case PCI_DEVICE_ID_INTEL_82801BA_2:
1152 case PCI_DEVICE_ID_INTEL_82801AB_3:
1153 case PCI_DEVICE_ID_INTEL_82801AA_3:
1154 break;
1155 }
1156
1157 /* Disable features on user request */
1158 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1159 if (priv->features & disable_features & (1 << i))
1160 dev_notice(&dev->dev, "%s disabled by user\n",
1161 i801_feature_names[i]);
1162 }
1163 priv->features &= ~disable_features;
1164
1165 err = pci_enable_device(dev);
1166 if (err) {
1167 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1168 err);
1169 goto exit;
1170 }
1171
1172 /* Determine the address of the SMBus area */
1173 priv->smba = pci_resource_start(dev, SMBBAR);
1174 if (!priv->smba) {
1175 dev_err(&dev->dev, "SMBus base address uninitialized, "
1176 "upgrade BIOS\n");
1177 err = -ENODEV;
1178 goto exit;
1179 }
1180
1181 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
1182 if (err) {
1183 err = -ENODEV;
1184 goto exit;
1185 }
1186
1187 err = pci_request_region(dev, SMBBAR, i801_driver.name);
1188 if (err) {
1189 dev_err(&dev->dev, "Failed to request SMBus region "
1190 "0x%lx-0x%Lx\n", priv->smba,
1191 (unsigned long long)pci_resource_end(dev, SMBBAR));
1192 goto exit;
1193 }
1194
1195 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1196 priv->original_hstcfg = temp;
1197 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1198 if (!(temp & SMBHSTCFG_HST_EN)) {
1199 dev_info(&dev->dev, "Enabling SMBus device\n");
1200 temp |= SMBHSTCFG_HST_EN;
1201 }
1202 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1203
1204 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1205 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1206 /* Disable SMBus interrupt feature if SMBus using SMI# */
1207 priv->features &= ~FEATURE_IRQ;
1208 }
1209
1210 /* Clear special mode bits */
1211 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1212 outb_p(inb_p(SMBAUXCTL(priv)) &
1213 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1214
1215 if (priv->features & FEATURE_IRQ) {
1216 init_waitqueue_head(&priv->waitq);
1217
1218 err = request_irq(dev->irq, i801_isr, IRQF_SHARED,
1219 i801_driver.name, priv);
1220 if (err) {
1221 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1222 dev->irq, err);
1223 goto exit_release;
1224 }
1225 dev_info(&dev->dev, "SMBus using PCI Interrupt\n");
1226 }
1227
1228 /* set up the sysfs linkage to our parent device */
1229 priv->adapter.dev.parent = &dev->dev;
1230
1231 /* Retry up to 3 times on lost arbitration */
1232 priv->adapter.retries = 3;
1233
1234 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1235 "SMBus I801 adapter at %04lx", priv->smba);
1236 err = i2c_add_adapter(&priv->adapter);
1237 if (err) {
1238 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1239 goto exit_free_irq;
1240 }
1241
1242 i801_probe_optional_slaves(priv);
1243 /* We ignore errors - multiplexing is optional */
1244 i801_add_mux(priv);
1245
1246 pci_set_drvdata(dev, priv);
1247
1248 return 0;
1249
1250 exit_free_irq:
1251 if (priv->features & FEATURE_IRQ)
1252 free_irq(dev->irq, priv);
1253 exit_release:
1254 pci_release_region(dev, SMBBAR);
1255 exit:
1256 kfree(priv);
1257 return err;
1258 }
1259
1260 static void i801_remove(struct pci_dev *dev)
1261 {
1262 struct i801_priv *priv = pci_get_drvdata(dev);
1263
1264 i801_del_mux(priv);
1265 i2c_del_adapter(&priv->adapter);
1266 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1267
1268 if (priv->features & FEATURE_IRQ)
1269 free_irq(dev->irq, priv);
1270 pci_release_region(dev, SMBBAR);
1271
1272 kfree(priv);
1273 /*
1274 * do not call pci_disable_device(dev) since it can cause hard hangs on
1275 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1276 */
1277 }
1278
1279 #ifdef CONFIG_PM
1280 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1281 {
1282 struct i801_priv *priv = pci_get_drvdata(dev);
1283
1284 pci_save_state(dev);
1285 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1286 pci_set_power_state(dev, pci_choose_state(dev, mesg));
1287 return 0;
1288 }
1289
1290 static int i801_resume(struct pci_dev *dev)
1291 {
1292 pci_set_power_state(dev, PCI_D0);
1293 pci_restore_state(dev);
1294 return pci_enable_device(dev);
1295 }
1296 #else
1297 #define i801_suspend NULL
1298 #define i801_resume NULL
1299 #endif
1300
1301 static struct pci_driver i801_driver = {
1302 .name = "i801_smbus",
1303 .id_table = i801_ids,
1304 .probe = i801_probe,
1305 .remove = i801_remove,
1306 .suspend = i801_suspend,
1307 .resume = i801_resume,
1308 };
1309
1310 static int __init i2c_i801_init(void)
1311 {
1312 if (dmi_name_in_vendors("FUJITSU"))
1313 input_apanel_init();
1314 return pci_register_driver(&i801_driver);
1315 }
1316
1317 static void __exit i2c_i801_exit(void)
1318 {
1319 pci_unregister_driver(&i801_driver);
1320 }
1321
1322 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1323 MODULE_DESCRIPTION("I801 SMBus driver");
1324 MODULE_LICENSE("GPL");
1325
1326 module_init(i2c_i801_init);
1327 module_exit(i2c_i801_exit);
Linux kernel - Deliverables
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