2 * Copyright (C) 2002 Motorola GSG-China
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 * Darius Augulis, Teltonika Inc.
18 * Implementation of I2C Adapter/Algorithm Driver
19 * for I2C Bus integrated in Freescale i.MX/MXC processors
21 * Derived from Motorola GSG China I2C example driver
23 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
24 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
25 * Copyright (C) 2007 RightHand Technologies, Inc.
26 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
28 * Copyright 2013 Freescale Semiconductor, Inc.
32 /** Includes *******************************************************************
33 *******************************************************************************/
35 #include <linux/clk.h>
36 #include <linux/completion.h>
37 #include <linux/delay.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmaengine.h>
40 #include <linux/dmapool.h>
41 #include <linux/err.h>
42 #include <linux/errno.h>
43 #include <linux/i2c.h>
44 #include <linux/init.h>
45 #include <linux/interrupt.h>
47 #include <linux/kernel.h>
48 #include <linux/module.h>
50 #include <linux/of_device.h>
51 #include <linux/of_dma.h>
52 #include <linux/platform_data/i2c-imx.h>
53 #include <linux/platform_device.h>
54 #include <linux/sched.h>
55 #include <linux/slab.h>
57 /** Defines ********************************************************************
58 *******************************************************************************/
60 /* This will be the driver name the kernel reports */
61 #define DRIVER_NAME "imx-i2c"
64 #define IMX_I2C_BIT_RATE 100000 /* 100kHz */
67 * Enable DMA if transfer byte size is bigger than this threshold.
68 * As the hardware request, it must bigger than 4 bytes.\
69 * I have set '16' here, maybe it's not the best but I think it's
72 #define DMA_THRESHOLD 16
73 #define DMA_TIMEOUT 1000
76 * the I2C register offset is different between SoCs,
77 * to provid support for all these chips, split the
78 * register offset into a fixed base address and a
79 * variable shift value, then the full register offset
80 * will be calculated by
81 * reg_off = ( reg_base_addr << reg_shift)
83 #define IMX_I2C_IADR 0x00 /* i2c slave address */
84 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
85 #define IMX_I2C_I2CR 0x02 /* i2c control */
86 #define IMX_I2C_I2SR 0x03 /* i2c status */
87 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */
89 #define IMX_I2C_REGSHIFT 2
90 #define VF610_I2C_REGSHIFT 0
92 /* Bits of IMX I2C registers */
93 #define I2SR_RXAK 0x01
98 #define I2SR_IAAS 0x40
100 #define I2CR_DMAEN 0x02
101 #define I2CR_RSTA 0x04
102 #define I2CR_TXAK 0x08
103 #define I2CR_MTX 0x10
104 #define I2CR_MSTA 0x20
105 #define I2CR_IIEN 0x40
106 #define I2CR_IEN 0x80
108 /* register bits different operating codes definition:
109 * 1) I2SR: Interrupt flags clear operation differ between SoCs:
110 * - write zero to clear(w0c) INT flag on i.MX,
111 * - but write one to clear(w1c) INT flag on Vybrid.
112 * 2) I2CR: I2C module enable operation also differ between SoCs:
113 * - set I2CR_IEN bit enable the module on i.MX,
114 * - but clear I2CR_IEN bit enable the module on Vybrid.
116 #define I2SR_CLR_OPCODE_W0C 0x0
117 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
118 #define I2CR_IEN_OPCODE_0 0x0
119 #define I2CR_IEN_OPCODE_1 I2CR_IEN
121 /** Variables ******************************************************************
122 *******************************************************************************/
125 * sorted list of clock divider, register value pairs
126 * taken from table 26-5, p.26-9, Freescale i.MX
127 * Integrated Portable System Processor Reference Manual
128 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
130 * Duplicated divider values removed from list
132 struct imx_i2c_clk_pair
{
137 static struct imx_i2c_clk_pair imx_i2c_clk_div
[] = {
138 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
139 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
140 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
141 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
142 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
143 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
144 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
145 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
146 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
147 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
148 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
149 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
150 { 3072, 0x1E }, { 3840, 0x1F }
153 /* Vybrid VF610 clock divider, register value pairs */
154 static struct imx_i2c_clk_pair vf610_i2c_clk_div
[] = {
155 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
156 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
157 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
158 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
159 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
160 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
161 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
162 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
163 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
164 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
165 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
166 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
167 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
168 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
169 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
178 struct imx_i2c_hwdata
{
179 enum imx_i2c_type devtype
;
181 struct imx_i2c_clk_pair
*clk_div
;
183 unsigned i2sr_clr_opcode
;
184 unsigned i2cr_ien_opcode
;
188 struct dma_chan
*chan_tx
;
189 struct dma_chan
*chan_rx
;
190 struct dma_chan
*chan_using
;
191 struct completion cmd_complete
;
193 unsigned int dma_len
;
194 enum dma_transfer_direction dma_transfer_dir
;
195 enum dma_data_direction dma_data_dir
;
198 struct imx_i2c_struct
{
199 struct i2c_adapter adapter
;
202 wait_queue_head_t queue
;
204 unsigned int disable_delay
;
206 unsigned int ifdr
; /* IMX_I2C_IFDR */
207 unsigned int cur_clk
;
208 unsigned int bitrate
;
209 const struct imx_i2c_hwdata
*hwdata
;
211 struct imx_i2c_dma
*dma
;
214 static const struct imx_i2c_hwdata imx1_i2c_hwdata
= {
216 .regshift
= IMX_I2C_REGSHIFT
,
217 .clk_div
= imx_i2c_clk_div
,
218 .ndivs
= ARRAY_SIZE(imx_i2c_clk_div
),
219 .i2sr_clr_opcode
= I2SR_CLR_OPCODE_W0C
,
220 .i2cr_ien_opcode
= I2CR_IEN_OPCODE_1
,
224 static const struct imx_i2c_hwdata imx21_i2c_hwdata
= {
225 .devtype
= IMX21_I2C
,
226 .regshift
= IMX_I2C_REGSHIFT
,
227 .clk_div
= imx_i2c_clk_div
,
228 .ndivs
= ARRAY_SIZE(imx_i2c_clk_div
),
229 .i2sr_clr_opcode
= I2SR_CLR_OPCODE_W0C
,
230 .i2cr_ien_opcode
= I2CR_IEN_OPCODE_1
,
234 static struct imx_i2c_hwdata vf610_i2c_hwdata
= {
235 .devtype
= VF610_I2C
,
236 .regshift
= VF610_I2C_REGSHIFT
,
237 .clk_div
= vf610_i2c_clk_div
,
238 .ndivs
= ARRAY_SIZE(vf610_i2c_clk_div
),
239 .i2sr_clr_opcode
= I2SR_CLR_OPCODE_W1C
,
240 .i2cr_ien_opcode
= I2CR_IEN_OPCODE_0
,
244 static struct platform_device_id imx_i2c_devtype
[] = {
247 .driver_data
= (kernel_ulong_t
)&imx1_i2c_hwdata
,
250 .driver_data
= (kernel_ulong_t
)&imx21_i2c_hwdata
,
255 MODULE_DEVICE_TABLE(platform
, imx_i2c_devtype
);
257 static const struct of_device_id i2c_imx_dt_ids
[] = {
258 { .compatible
= "fsl,imx1-i2c", .data
= &imx1_i2c_hwdata
, },
259 { .compatible
= "fsl,imx21-i2c", .data
= &imx21_i2c_hwdata
, },
260 { .compatible
= "fsl,vf610-i2c", .data
= &vf610_i2c_hwdata
, },
263 MODULE_DEVICE_TABLE(of
, i2c_imx_dt_ids
);
265 static inline int is_imx1_i2c(struct imx_i2c_struct
*i2c_imx
)
267 return i2c_imx
->hwdata
->devtype
== IMX1_I2C
;
270 static inline void imx_i2c_write_reg(unsigned int val
,
271 struct imx_i2c_struct
*i2c_imx
, unsigned int reg
)
273 writeb(val
, i2c_imx
->base
+ (reg
<< i2c_imx
->hwdata
->regshift
));
276 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct
*i2c_imx
,
279 return readb(i2c_imx
->base
+ (reg
<< i2c_imx
->hwdata
->regshift
));
282 /* Functions for DMA support */
283 static void i2c_imx_dma_request(struct imx_i2c_struct
*i2c_imx
,
286 struct imx_i2c_dma
*dma
;
287 struct dma_slave_config dma_sconfig
;
288 struct device
*dev
= &i2c_imx
->adapter
.dev
;
291 dma
= devm_kzalloc(dev
, sizeof(*dma
), GFP_KERNEL
);
295 dma
->chan_tx
= dma_request_slave_channel(dev
, "tx");
297 dev_dbg(dev
, "can't request DMA tx channel\n");
302 dma_sconfig
.dst_addr
= phy_addr
+
303 (IMX_I2C_I2DR
<< i2c_imx
->hwdata
->regshift
);
304 dma_sconfig
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
305 dma_sconfig
.dst_maxburst
= 1;
306 dma_sconfig
.direction
= DMA_MEM_TO_DEV
;
307 ret
= dmaengine_slave_config(dma
->chan_tx
, &dma_sconfig
);
309 dev_dbg(dev
, "can't configure tx channel\n");
313 dma
->chan_rx
= dma_request_slave_channel(dev
, "rx");
315 dev_dbg(dev
, "can't request DMA rx channel\n");
320 dma_sconfig
.src_addr
= phy_addr
+
321 (IMX_I2C_I2DR
<< i2c_imx
->hwdata
->regshift
);
322 dma_sconfig
.src_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
323 dma_sconfig
.src_maxburst
= 1;
324 dma_sconfig
.direction
= DMA_DEV_TO_MEM
;
325 ret
= dmaengine_slave_config(dma
->chan_rx
, &dma_sconfig
);
327 dev_dbg(dev
, "can't configure rx channel\n");
332 init_completion(&dma
->cmd_complete
);
333 dev_info(dev
, "using %s (tx) and %s (rx) for DMA transfers\n",
334 dma_chan_name(dma
->chan_tx
), dma_chan_name(dma
->chan_rx
));
339 dma_release_channel(dma
->chan_rx
);
341 dma_release_channel(dma
->chan_tx
);
343 devm_kfree(dev
, dma
);
344 dev_info(dev
, "can't use DMA\n");
347 static void i2c_imx_dma_callback(void *arg
)
349 struct imx_i2c_struct
*i2c_imx
= (struct imx_i2c_struct
*)arg
;
350 struct imx_i2c_dma
*dma
= i2c_imx
->dma
;
352 dma_unmap_single(dma
->chan_using
->device
->dev
, dma
->dma_buf
,
353 dma
->dma_len
, dma
->dma_data_dir
);
354 complete(&dma
->cmd_complete
);
357 static int i2c_imx_dma_xfer(struct imx_i2c_struct
*i2c_imx
,
358 struct i2c_msg
*msgs
)
360 struct imx_i2c_dma
*dma
= i2c_imx
->dma
;
361 struct dma_async_tx_descriptor
*txdesc
;
362 struct device
*dev
= &i2c_imx
->adapter
.dev
;
363 struct device
*chan_dev
= dma
->chan_using
->device
->dev
;
365 dma
->dma_buf
= dma_map_single(chan_dev
, msgs
->buf
,
366 dma
->dma_len
, dma
->dma_data_dir
);
367 if (dma_mapping_error(chan_dev
, dma
->dma_buf
)) {
368 dev_err(dev
, "DMA mapping failed\n");
372 txdesc
= dmaengine_prep_slave_single(dma
->chan_using
, dma
->dma_buf
,
373 dma
->dma_len
, dma
->dma_transfer_dir
,
374 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
376 dev_err(dev
, "Not able to get desc for DMA xfer\n");
380 txdesc
->callback
= i2c_imx_dma_callback
;
381 txdesc
->callback_param
= i2c_imx
;
382 if (dma_submit_error(dmaengine_submit(txdesc
))) {
383 dev_err(dev
, "DMA submit failed\n");
387 dma_async_issue_pending(dma
->chan_using
);
392 dma_unmap_single(chan_dev
, dma
->dma_buf
,
393 dma
->dma_len
, dma
->dma_data_dir
);
398 static void i2c_imx_dma_free(struct imx_i2c_struct
*i2c_imx
)
400 struct imx_i2c_dma
*dma
= i2c_imx
->dma
;
405 dma_release_channel(dma
->chan_tx
);
408 dma_release_channel(dma
->chan_rx
);
411 dma
->chan_using
= NULL
;
414 /** Functions for IMX I2C adapter driver ***************************************
415 *******************************************************************************/
417 static int i2c_imx_bus_busy(struct imx_i2c_struct
*i2c_imx
, int for_busy
)
419 unsigned long orig_jiffies
= jiffies
;
422 dev_dbg(&i2c_imx
->adapter
.dev
, "<%s>\n", __func__
);
425 temp
= imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2SR
);
427 /* check for arbitration lost */
428 if (temp
& I2SR_IAL
) {
430 imx_i2c_write_reg(temp
, i2c_imx
, IMX_I2C_I2SR
);
434 if (for_busy
&& (temp
& I2SR_IBB
))
436 if (!for_busy
&& !(temp
& I2SR_IBB
))
438 if (time_after(jiffies
, orig_jiffies
+ msecs_to_jiffies(500))) {
439 dev_dbg(&i2c_imx
->adapter
.dev
,
440 "<%s> I2C bus is busy\n", __func__
);
449 static int i2c_imx_trx_complete(struct imx_i2c_struct
*i2c_imx
)
451 wait_event_timeout(i2c_imx
->queue
, i2c_imx
->i2csr
& I2SR_IIF
, HZ
/ 10);
453 if (unlikely(!(i2c_imx
->i2csr
& I2SR_IIF
))) {
454 dev_dbg(&i2c_imx
->adapter
.dev
, "<%s> Timeout\n", __func__
);
457 dev_dbg(&i2c_imx
->adapter
.dev
, "<%s> TRX complete\n", __func__
);
462 static int i2c_imx_acked(struct imx_i2c_struct
*i2c_imx
)
464 if (imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2SR
) & I2SR_RXAK
) {
465 dev_dbg(&i2c_imx
->adapter
.dev
, "<%s> No ACK\n", __func__
);
466 return -EIO
; /* No ACK */
469 dev_dbg(&i2c_imx
->adapter
.dev
, "<%s> ACK received\n", __func__
);
473 static void i2c_imx_set_clk(struct imx_i2c_struct
*i2c_imx
)
475 struct imx_i2c_clk_pair
*i2c_clk_div
= i2c_imx
->hwdata
->clk_div
;
476 unsigned int i2c_clk_rate
;
480 /* Divider value calculation */
481 i2c_clk_rate
= clk_get_rate(i2c_imx
->clk
);
482 if (i2c_imx
->cur_clk
== i2c_clk_rate
)
485 i2c_imx
->cur_clk
= i2c_clk_rate
;
487 div
= (i2c_clk_rate
+ i2c_imx
->bitrate
- 1) / i2c_imx
->bitrate
;
488 if (div
< i2c_clk_div
[0].div
)
490 else if (div
> i2c_clk_div
[i2c_imx
->hwdata
->ndivs
- 1].div
)
491 i
= i2c_imx
->hwdata
->ndivs
- 1;
493 for (i
= 0; i2c_clk_div
[i
].div
< div
; i
++);
495 /* Store divider value */
496 i2c_imx
->ifdr
= i2c_clk_div
[i
].val
;
499 * There dummy delay is calculated.
500 * It should be about one I2C clock period long.
501 * This delay is used in I2C bus disable function
502 * to fix chip hardware bug.
504 i2c_imx
->disable_delay
= (500000U * i2c_clk_div
[i
].div
505 + (i2c_clk_rate
/ 2) - 1) / (i2c_clk_rate
/ 2);
507 #ifdef CONFIG_I2C_DEBUG_BUS
508 dev_dbg(&i2c_imx
->adapter
.dev
, "I2C_CLK=%d, REQ DIV=%d\n",
510 dev_dbg(&i2c_imx
->adapter
.dev
, "IFDR[IC]=0x%x, REAL DIV=%d\n",
511 i2c_clk_div
[i
].val
, i2c_clk_div
[i
].div
);
515 static int i2c_imx_start(struct imx_i2c_struct
*i2c_imx
)
517 unsigned int temp
= 0;
520 dev_dbg(&i2c_imx
->adapter
.dev
, "<%s>\n", __func__
);
522 i2c_imx_set_clk(i2c_imx
);
524 result
= clk_prepare_enable(i2c_imx
->clk
);
527 imx_i2c_write_reg(i2c_imx
->ifdr
, i2c_imx
, IMX_I2C_IFDR
);
528 /* Enable I2C controller */
529 imx_i2c_write_reg(i2c_imx
->hwdata
->i2sr_clr_opcode
, i2c_imx
, IMX_I2C_I2SR
);
530 imx_i2c_write_reg(i2c_imx
->hwdata
->i2cr_ien_opcode
, i2c_imx
, IMX_I2C_I2CR
);
532 /* Wait controller to be stable */
535 /* Start I2C transaction */
536 temp
= imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2CR
);
538 imx_i2c_write_reg(temp
, i2c_imx
, IMX_I2C_I2CR
);
539 result
= i2c_imx_bus_busy(i2c_imx
, 1);
542 i2c_imx
->stopped
= 0;
544 temp
|= I2CR_IIEN
| I2CR_MTX
| I2CR_TXAK
;
546 imx_i2c_write_reg(temp
, i2c_imx
, IMX_I2C_I2CR
);
550 static void i2c_imx_stop(struct imx_i2c_struct
*i2c_imx
)
552 unsigned int temp
= 0;
554 if (!i2c_imx
->stopped
) {
555 /* Stop I2C transaction */
556 dev_dbg(&i2c_imx
->adapter
.dev
, "<%s>\n", __func__
);
557 temp
= imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2CR
);
558 temp
&= ~(I2CR_MSTA
| I2CR_MTX
);
561 imx_i2c_write_reg(temp
, i2c_imx
, IMX_I2C_I2CR
);
563 if (is_imx1_i2c(i2c_imx
)) {
565 * This delay caused by an i.MXL hardware bug.
566 * If no (or too short) delay, no "STOP" bit will be generated.
568 udelay(i2c_imx
->disable_delay
);
571 if (!i2c_imx
->stopped
) {
572 i2c_imx_bus_busy(i2c_imx
, 0);
573 i2c_imx
->stopped
= 1;
576 /* Disable I2C controller */
577 temp
= i2c_imx
->hwdata
->i2cr_ien_opcode
^ I2CR_IEN
,
578 imx_i2c_write_reg(temp
, i2c_imx
, IMX_I2C_I2CR
);
579 clk_disable_unprepare(i2c_imx
->clk
);
582 static irqreturn_t
i2c_imx_isr(int irq
, void *dev_id
)
584 struct imx_i2c_struct
*i2c_imx
= dev_id
;
587 temp
= imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2SR
);
588 if (temp
& I2SR_IIF
) {
589 /* save status register */
590 i2c_imx
->i2csr
= temp
;
592 temp
|= (i2c_imx
->hwdata
->i2sr_clr_opcode
& I2SR_IIF
);
593 imx_i2c_write_reg(temp
, i2c_imx
, IMX_I2C_I2SR
);
594 wake_up(&i2c_imx
->queue
);
601 static int i2c_imx_dma_write(struct imx_i2c_struct
*i2c_imx
,
602 struct i2c_msg
*msgs
)
605 unsigned int temp
= 0;
606 unsigned long orig_jiffies
= jiffies
;
607 struct imx_i2c_dma
*dma
= i2c_imx
->dma
;
608 struct device
*dev
= &i2c_imx
->adapter
.dev
;
610 dma
->chan_using
= dma
->chan_tx
;
611 dma
->dma_transfer_dir
= DMA_MEM_TO_DEV
;
612 dma
->dma_data_dir
= DMA_TO_DEVICE
;
613 dma
->dma_len
= msgs
->len
- 1;
614 result
= i2c_imx_dma_xfer(i2c_imx
, msgs
);
618 temp
= imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2CR
);
620 imx_i2c_write_reg(temp
, i2c_imx
, IMX_I2C_I2CR
);
623 * Write slave address.
624 * The first byte must be transmitted by the CPU.
626 imx_i2c_write_reg(msgs
->addr
<< 1, i2c_imx
, IMX_I2C_I2DR
);
627 reinit_completion(&i2c_imx
->dma
->cmd_complete
);
628 result
= wait_for_completion_timeout(
629 &i2c_imx
->dma
->cmd_complete
,
630 msecs_to_jiffies(DMA_TIMEOUT
));
632 dmaengine_terminate_all(dma
->chan_using
);
633 return result
?: -ETIMEDOUT
;
636 /* Waiting for transfer complete. */
638 temp
= imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2SR
);
641 if (time_after(jiffies
, orig_jiffies
+
642 msecs_to_jiffies(DMA_TIMEOUT
))) {
643 dev_dbg(dev
, "<%s> Timeout\n", __func__
);
649 temp
= imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2CR
);
651 imx_i2c_write_reg(temp
, i2c_imx
, IMX_I2C_I2CR
);
653 /* The last data byte must be transferred by the CPU. */
654 imx_i2c_write_reg(msgs
->buf
[msgs
->len
-1],
655 i2c_imx
, IMX_I2C_I2DR
);
656 result
= i2c_imx_trx_complete(i2c_imx
);
660 return i2c_imx_acked(i2c_imx
);
663 static int i2c_imx_dma_read(struct imx_i2c_struct
*i2c_imx
,
664 struct i2c_msg
*msgs
, bool is_lastmsg
)
668 unsigned long orig_jiffies
= jiffies
;
669 struct imx_i2c_dma
*dma
= i2c_imx
->dma
;
670 struct device
*dev
= &i2c_imx
->adapter
.dev
;
672 temp
= imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2CR
);
674 imx_i2c_write_reg(temp
, i2c_imx
, IMX_I2C_I2CR
);
676 dma
->chan_using
= dma
->chan_rx
;
677 dma
->dma_transfer_dir
= DMA_DEV_TO_MEM
;
678 dma
->dma_data_dir
= DMA_FROM_DEVICE
;
679 /* The last two data bytes must be transferred by the CPU. */
680 dma
->dma_len
= msgs
->len
- 2;
681 result
= i2c_imx_dma_xfer(i2c_imx
, msgs
);
685 reinit_completion(&i2c_imx
->dma
->cmd_complete
);
686 result
= wait_for_completion_timeout(
687 &i2c_imx
->dma
->cmd_complete
,
688 msecs_to_jiffies(DMA_TIMEOUT
));
690 dmaengine_terminate_all(dma
->chan_using
);
691 return result
?: -ETIMEDOUT
;
694 /* waiting for transfer complete. */
696 temp
= imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2SR
);
699 if (time_after(jiffies
, orig_jiffies
+
700 msecs_to_jiffies(DMA_TIMEOUT
))) {
701 dev_dbg(dev
, "<%s> Timeout\n", __func__
);
707 temp
= imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2CR
);
709 imx_i2c_write_reg(temp
, i2c_imx
, IMX_I2C_I2CR
);
711 /* read n-1 byte data */
712 temp
= imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2CR
);
714 imx_i2c_write_reg(temp
, i2c_imx
, IMX_I2C_I2CR
);
716 msgs
->buf
[msgs
->len
-2] = imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2DR
);
717 /* read n byte data */
718 result
= i2c_imx_trx_complete(i2c_imx
);
724 * It must generate STOP before read I2DR to prevent
725 * controller from generating another clock cycle
727 dev_dbg(dev
, "<%s> clear MSTA\n", __func__
);
728 temp
= imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2CR
);
729 temp
&= ~(I2CR_MSTA
| I2CR_MTX
);
730 imx_i2c_write_reg(temp
, i2c_imx
, IMX_I2C_I2CR
);
731 i2c_imx_bus_busy(i2c_imx
, 0);
732 i2c_imx
->stopped
= 1;
735 * For i2c master receiver repeat restart operation like:
736 * read -> repeat MSTA -> read/write
737 * The controller must set MTX before read the last byte in
738 * the first read operation, otherwise the first read cost
739 * one extra clock cycle.
741 temp
= readb(i2c_imx
->base
+ IMX_I2C_I2CR
);
743 writeb(temp
, i2c_imx
->base
+ IMX_I2C_I2CR
);
745 msgs
->buf
[msgs
->len
-1] = imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2DR
);
750 static int i2c_imx_write(struct imx_i2c_struct
*i2c_imx
, struct i2c_msg
*msgs
)
754 dev_dbg(&i2c_imx
->adapter
.dev
, "<%s> write slave address: addr=0x%x\n",
755 __func__
, msgs
->addr
<< 1);
757 /* write slave address */
758 imx_i2c_write_reg(msgs
->addr
<< 1, i2c_imx
, IMX_I2C_I2DR
);
759 result
= i2c_imx_trx_complete(i2c_imx
);
762 result
= i2c_imx_acked(i2c_imx
);
765 dev_dbg(&i2c_imx
->adapter
.dev
, "<%s> write data\n", __func__
);
768 for (i
= 0; i
< msgs
->len
; i
++) {
769 dev_dbg(&i2c_imx
->adapter
.dev
,
770 "<%s> write byte: B%d=0x%X\n",
771 __func__
, i
, msgs
->buf
[i
]);
772 imx_i2c_write_reg(msgs
->buf
[i
], i2c_imx
, IMX_I2C_I2DR
);
773 result
= i2c_imx_trx_complete(i2c_imx
);
776 result
= i2c_imx_acked(i2c_imx
);
783 static int i2c_imx_read(struct imx_i2c_struct
*i2c_imx
, struct i2c_msg
*msgs
, bool is_lastmsg
)
787 int block_data
= msgs
->flags
& I2C_M_RECV_LEN
;
789 dev_dbg(&i2c_imx
->adapter
.dev
,
790 "<%s> write slave address: addr=0x%x\n",
791 __func__
, (msgs
->addr
<< 1) | 0x01);
793 /* write slave address */
794 imx_i2c_write_reg((msgs
->addr
<< 1) | 0x01, i2c_imx
, IMX_I2C_I2DR
);
795 result
= i2c_imx_trx_complete(i2c_imx
);
798 result
= i2c_imx_acked(i2c_imx
);
802 dev_dbg(&i2c_imx
->adapter
.dev
, "<%s> setup bus\n", __func__
);
804 /* setup bus to read data */
805 temp
= imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2CR
);
809 * Reset the I2CR_TXAK flag initially for SMBus block read since the
812 if ((msgs
->len
- 1) || block_data
)
814 imx_i2c_write_reg(temp
, i2c_imx
, IMX_I2C_I2CR
);
815 imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2DR
); /* dummy read */
817 dev_dbg(&i2c_imx
->adapter
.dev
, "<%s> read data\n", __func__
);
819 if (i2c_imx
->dma
&& msgs
->len
>= DMA_THRESHOLD
&& !block_data
)
820 return i2c_imx_dma_read(i2c_imx
, msgs
, is_lastmsg
);
823 for (i
= 0; i
< msgs
->len
; i
++) {
825 result
= i2c_imx_trx_complete(i2c_imx
);
829 * First byte is the length of remaining packet
830 * in the SMBus block data read. Add it to
833 if ((!i
) && block_data
) {
834 len
= imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2DR
);
835 if ((len
== 0) || (len
> I2C_SMBUS_BLOCK_MAX
))
837 dev_dbg(&i2c_imx
->adapter
.dev
,
838 "<%s> read length: 0x%X\n",
842 if (i
== (msgs
->len
- 1)) {
845 * It must generate STOP before read I2DR to prevent
846 * controller from generating another clock cycle
848 dev_dbg(&i2c_imx
->adapter
.dev
,
849 "<%s> clear MSTA\n", __func__
);
850 temp
= imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2CR
);
851 temp
&= ~(I2CR_MSTA
| I2CR_MTX
);
852 imx_i2c_write_reg(temp
, i2c_imx
, IMX_I2C_I2CR
);
853 i2c_imx_bus_busy(i2c_imx
, 0);
854 i2c_imx
->stopped
= 1;
857 * For i2c master receiver repeat restart operation like:
858 * read -> repeat MSTA -> read/write
859 * The controller must set MTX before read the last byte in
860 * the first read operation, otherwise the first read cost
861 * one extra clock cycle.
863 temp
= readb(i2c_imx
->base
+ IMX_I2C_I2CR
);
865 writeb(temp
, i2c_imx
->base
+ IMX_I2C_I2CR
);
867 } else if (i
== (msgs
->len
- 2)) {
868 dev_dbg(&i2c_imx
->adapter
.dev
,
869 "<%s> set TXAK\n", __func__
);
870 temp
= imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2CR
);
872 imx_i2c_write_reg(temp
, i2c_imx
, IMX_I2C_I2CR
);
874 if ((!i
) && block_data
)
877 msgs
->buf
[i
] = imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2DR
);
878 dev_dbg(&i2c_imx
->adapter
.dev
,
879 "<%s> read byte: B%d=0x%X\n",
880 __func__
, i
, msgs
->buf
[i
]);
885 static int i2c_imx_xfer(struct i2c_adapter
*adapter
,
886 struct i2c_msg
*msgs
, int num
)
888 unsigned int i
, temp
;
890 bool is_lastmsg
= false;
891 struct imx_i2c_struct
*i2c_imx
= i2c_get_adapdata(adapter
);
893 dev_dbg(&i2c_imx
->adapter
.dev
, "<%s>\n", __func__
);
895 /* Start I2C transfer */
896 result
= i2c_imx_start(i2c_imx
);
900 /* read/write data */
901 for (i
= 0; i
< num
; i
++) {
906 dev_dbg(&i2c_imx
->adapter
.dev
,
907 "<%s> repeated start\n", __func__
);
908 temp
= imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2CR
);
910 imx_i2c_write_reg(temp
, i2c_imx
, IMX_I2C_I2CR
);
911 result
= i2c_imx_bus_busy(i2c_imx
, 1);
915 dev_dbg(&i2c_imx
->adapter
.dev
,
916 "<%s> transfer message: %d\n", __func__
, i
);
917 /* write/read data */
918 #ifdef CONFIG_I2C_DEBUG_BUS
919 temp
= imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2CR
);
920 dev_dbg(&i2c_imx
->adapter
.dev
, "<%s> CONTROL: IEN=%d, IIEN=%d, "
921 "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__
,
922 (temp
& I2CR_IEN
? 1 : 0), (temp
& I2CR_IIEN
? 1 : 0),
923 (temp
& I2CR_MSTA
? 1 : 0), (temp
& I2CR_MTX
? 1 : 0),
924 (temp
& I2CR_TXAK
? 1 : 0), (temp
& I2CR_RSTA
? 1 : 0));
925 temp
= imx_i2c_read_reg(i2c_imx
, IMX_I2C_I2SR
);
926 dev_dbg(&i2c_imx
->adapter
.dev
,
927 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
928 "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__
,
929 (temp
& I2SR_ICF
? 1 : 0), (temp
& I2SR_IAAS
? 1 : 0),
930 (temp
& I2SR_IBB
? 1 : 0), (temp
& I2SR_IAL
? 1 : 0),
931 (temp
& I2SR_SRW
? 1 : 0), (temp
& I2SR_IIF
? 1 : 0),
932 (temp
& I2SR_RXAK
? 1 : 0));
934 if (msgs
[i
].flags
& I2C_M_RD
)
935 result
= i2c_imx_read(i2c_imx
, &msgs
[i
], is_lastmsg
);
937 if (i2c_imx
->dma
&& msgs
[i
].len
>= DMA_THRESHOLD
)
938 result
= i2c_imx_dma_write(i2c_imx
, &msgs
[i
]);
940 result
= i2c_imx_write(i2c_imx
, &msgs
[i
]);
947 /* Stop I2C transfer */
948 i2c_imx_stop(i2c_imx
);
950 dev_dbg(&i2c_imx
->adapter
.dev
, "<%s> exit with: %s: %d\n", __func__
,
951 (result
< 0) ? "error" : "success msg",
952 (result
< 0) ? result
: num
);
953 return (result
< 0) ? result
: num
;
956 static u32
i2c_imx_func(struct i2c_adapter
*adapter
)
958 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
959 | I2C_FUNC_SMBUS_READ_BLOCK_DATA
;
962 static struct i2c_algorithm i2c_imx_algo
= {
963 .master_xfer
= i2c_imx_xfer
,
964 .functionality
= i2c_imx_func
,
967 static int i2c_imx_probe(struct platform_device
*pdev
)
969 const struct of_device_id
*of_id
= of_match_device(i2c_imx_dt_ids
,
971 struct imx_i2c_struct
*i2c_imx
;
972 struct resource
*res
;
973 struct imxi2c_platform_data
*pdata
= dev_get_platdata(&pdev
->dev
);
978 dev_dbg(&pdev
->dev
, "<%s>\n", __func__
);
980 irq
= platform_get_irq(pdev
, 0);
982 dev_err(&pdev
->dev
, "can't get irq number\n");
986 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
987 base
= devm_ioremap_resource(&pdev
->dev
, res
);
989 return PTR_ERR(base
);
991 phy_addr
= (dma_addr_t
)res
->start
;
992 i2c_imx
= devm_kzalloc(&pdev
->dev
, sizeof(*i2c_imx
), GFP_KERNEL
);
997 i2c_imx
->hwdata
= of_id
->data
;
999 i2c_imx
->hwdata
= (struct imx_i2c_hwdata
*)
1000 platform_get_device_id(pdev
)->driver_data
;
1002 /* Setup i2c_imx driver structure */
1003 strlcpy(i2c_imx
->adapter
.name
, pdev
->name
, sizeof(i2c_imx
->adapter
.name
));
1004 i2c_imx
->adapter
.owner
= THIS_MODULE
;
1005 i2c_imx
->adapter
.algo
= &i2c_imx_algo
;
1006 i2c_imx
->adapter
.dev
.parent
= &pdev
->dev
;
1007 i2c_imx
->adapter
.nr
= pdev
->id
;
1008 i2c_imx
->adapter
.dev
.of_node
= pdev
->dev
.of_node
;
1009 i2c_imx
->base
= base
;
1012 i2c_imx
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1013 if (IS_ERR(i2c_imx
->clk
)) {
1014 dev_err(&pdev
->dev
, "can't get I2C clock\n");
1015 return PTR_ERR(i2c_imx
->clk
);
1018 ret
= clk_prepare_enable(i2c_imx
->clk
);
1020 dev_err(&pdev
->dev
, "can't enable I2C clock\n");
1024 ret
= devm_request_irq(&pdev
->dev
, irq
, i2c_imx_isr
, 0,
1025 pdev
->name
, i2c_imx
);
1027 dev_err(&pdev
->dev
, "can't claim irq %d\n", irq
);
1032 init_waitqueue_head(&i2c_imx
->queue
);
1034 /* Set up adapter data */
1035 i2c_set_adapdata(&i2c_imx
->adapter
, i2c_imx
);
1037 /* Set up clock divider */
1038 i2c_imx
->bitrate
= IMX_I2C_BIT_RATE
;
1039 ret
= of_property_read_u32(pdev
->dev
.of_node
,
1040 "clock-frequency", &i2c_imx
->bitrate
);
1041 if (ret
< 0 && pdata
&& pdata
->bitrate
)
1042 i2c_imx
->bitrate
= pdata
->bitrate
;
1044 /* Set up chip registers to defaults */
1045 imx_i2c_write_reg(i2c_imx
->hwdata
->i2cr_ien_opcode
^ I2CR_IEN
,
1046 i2c_imx
, IMX_I2C_I2CR
);
1047 imx_i2c_write_reg(i2c_imx
->hwdata
->i2sr_clr_opcode
, i2c_imx
, IMX_I2C_I2SR
);
1049 /* Add I2C adapter */
1050 ret
= i2c_add_numbered_adapter(&i2c_imx
->adapter
);
1052 dev_err(&pdev
->dev
, "registration failed\n");
1056 /* Set up platform driver data */
1057 platform_set_drvdata(pdev
, i2c_imx
);
1058 clk_disable_unprepare(i2c_imx
->clk
);
1060 dev_dbg(&i2c_imx
->adapter
.dev
, "claimed irq %d\n", irq
);
1061 dev_dbg(&i2c_imx
->adapter
.dev
, "device resources: %pR\n", res
);
1062 dev_dbg(&i2c_imx
->adapter
.dev
, "adapter name: \"%s\"\n",
1063 i2c_imx
->adapter
.name
);
1064 dev_info(&i2c_imx
->adapter
.dev
, "IMX I2C adapter registered\n");
1066 /* Init DMA config if support*/
1067 i2c_imx_dma_request(i2c_imx
, phy_addr
);
1069 return 0; /* Return OK */
1072 clk_disable_unprepare(i2c_imx
->clk
);
1076 static int i2c_imx_remove(struct platform_device
*pdev
)
1078 struct imx_i2c_struct
*i2c_imx
= platform_get_drvdata(pdev
);
1080 /* remove adapter */
1081 dev_dbg(&i2c_imx
->adapter
.dev
, "adapter removed\n");
1082 i2c_del_adapter(&i2c_imx
->adapter
);
1085 i2c_imx_dma_free(i2c_imx
);
1087 /* setup chip registers to defaults */
1088 imx_i2c_write_reg(0, i2c_imx
, IMX_I2C_IADR
);
1089 imx_i2c_write_reg(0, i2c_imx
, IMX_I2C_IFDR
);
1090 imx_i2c_write_reg(0, i2c_imx
, IMX_I2C_I2CR
);
1091 imx_i2c_write_reg(0, i2c_imx
, IMX_I2C_I2SR
);
1096 static struct platform_driver i2c_imx_driver
= {
1097 .probe
= i2c_imx_probe
,
1098 .remove
= i2c_imx_remove
,
1100 .name
= DRIVER_NAME
,
1101 .owner
= THIS_MODULE
,
1102 .of_match_table
= i2c_imx_dt_ids
,
1104 .id_table
= imx_i2c_devtype
,
1107 static int __init
i2c_adap_imx_init(void)
1109 return platform_driver_register(&i2c_imx_driver
);
1111 subsys_initcall(i2c_adap_imx_init
);
1113 static void __exit
i2c_adap_imx_exit(void)
1115 platform_driver_unregister(&i2c_imx_driver
);
1117 module_exit(i2c_adap_imx_exit
);
1119 MODULE_LICENSE("GPL");
1120 MODULE_AUTHOR("Darius Augulis");
1121 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
1122 MODULE_ALIAS("platform:" DRIVER_NAME
);