2 * (C) Copyright 2003-2004
3 * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
5 * This is a combined i2c adapter and algorithm driver for the
6 * MPC107/Tsi107 PowerPC northbridge and processors that include
7 * the same I2C unit (8240, 8245, 85xx).
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
23 #include <linux/fsl_devices.h>
24 #include <linux/i2c.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
28 #define MPC_I2C_ADDR 0x00
29 #define MPC_I2C_FDR 0x04
30 #define MPC_I2C_CR 0x08
31 #define MPC_I2C_SR 0x0c
32 #define MPC_I2C_DR 0x10
33 #define MPC_I2C_DFSRR 0x14
34 #define MPC_I2C_REGION 0x20
54 wait_queue_head_t queue
;
55 struct i2c_adapter adap
;
60 static __inline__
void writeccr(struct mpc_i2c
*i2c
, u32 x
)
62 writeb(x
, i2c
->base
+ MPC_I2C_CR
);
65 static irqreturn_t
mpc_i2c_isr(int irq
, void *dev_id
)
67 struct mpc_i2c
*i2c
= dev_id
;
68 if (readb(i2c
->base
+ MPC_I2C_SR
) & CSR_MIF
) {
69 /* Read again to allow register to stabilise */
70 i2c
->interrupt
= readb(i2c
->base
+ MPC_I2C_SR
);
71 writeb(0, i2c
->base
+ MPC_I2C_SR
);
72 wake_up_interruptible(&i2c
->queue
);
77 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
78 * the bus, because it wants to send ACK.
79 * Following sequence of enabling/disabling and sending start/stop generates
80 * the pulse, so it's all OK.
82 static void mpc_i2c_fixup(struct mpc_i2c
*i2c
)
86 writeccr(i2c
, CCR_MEN
);
88 writeccr(i2c
, CCR_MSTA
| CCR_MTX
);
90 writeccr(i2c
, CCR_MSTA
| CCR_MTX
| CCR_MEN
);
92 writeccr(i2c
, CCR_MEN
);
96 static int i2c_wait(struct mpc_i2c
*i2c
, unsigned timeout
, int writing
)
98 unsigned long orig_jiffies
= jiffies
;
104 while (!(readb(i2c
->base
+ MPC_I2C_SR
) & CSR_MIF
)) {
106 if (time_after(jiffies
, orig_jiffies
+ timeout
)) {
107 pr_debug("I2C: timeout\n");
112 x
= readb(i2c
->base
+ MPC_I2C_SR
);
113 writeb(0, i2c
->base
+ MPC_I2C_SR
);
116 result
= wait_event_interruptible_timeout(i2c
->queue
,
117 (i2c
->interrupt
& CSR_MIF
), timeout
* HZ
);
119 if (unlikely(result
< 0))
120 pr_debug("I2C: wait interrupted\n");
121 else if (unlikely(!(i2c
->interrupt
& CSR_MIF
))) {
122 pr_debug("I2C: wait timeout\n");
133 if (!(x
& CSR_MCF
)) {
134 pr_debug("I2C: unfinished\n");
139 pr_debug("I2C: MAL\n");
143 if (writing
&& (x
& CSR_RXAK
)) {
144 pr_debug("I2C: No RXAK\n");
146 writeccr(i2c
, CCR_MEN
);
152 static void mpc_i2c_setclock(struct mpc_i2c
*i2c
)
154 /* Set clock and filters */
155 if (i2c
->flags
& FSL_I2C_DEV_SEPARATE_DFSRR
) {
156 writeb(0x31, i2c
->base
+ MPC_I2C_FDR
);
157 writeb(0x10, i2c
->base
+ MPC_I2C_DFSRR
);
158 } else if (i2c
->flags
& FSL_I2C_DEV_CLOCK_5200
)
159 writeb(0x3f, i2c
->base
+ MPC_I2C_FDR
);
161 writel(0x1031, i2c
->base
+ MPC_I2C_FDR
);
164 static void mpc_i2c_start(struct mpc_i2c
*i2c
)
166 /* Clear arbitration */
167 writeb(0, i2c
->base
+ MPC_I2C_SR
);
169 writeccr(i2c
, CCR_MEN
);
172 static void mpc_i2c_stop(struct mpc_i2c
*i2c
)
174 writeccr(i2c
, CCR_MEN
);
178 static int mpc_write(struct mpc_i2c
*i2c
, int target
,
179 const u8
* data
, int length
, int restart
)
182 unsigned timeout
= i2c
->adap
.timeout
;
183 u32 flags
= restart
? CCR_RSTA
: 0;
187 writeccr(i2c
, CCR_MEN
);
188 /* Start as master */
189 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_MSTA
| CCR_MTX
| flags
);
190 /* Write target byte */
191 writeb((target
<< 1), i2c
->base
+ MPC_I2C_DR
);
193 if (i2c_wait(i2c
, timeout
, 1) < 0)
196 for (i
= 0; i
< length
; i
++) {
197 /* Write data byte */
198 writeb(data
[i
], i2c
->base
+ MPC_I2C_DR
);
200 if (i2c_wait(i2c
, timeout
, 1) < 0)
207 static int mpc_read(struct mpc_i2c
*i2c
, int target
,
208 u8
* data
, int length
, int restart
)
210 unsigned timeout
= i2c
->adap
.timeout
;
212 u32 flags
= restart
? CCR_RSTA
: 0;
216 writeccr(i2c
, CCR_MEN
);
217 /* Switch to read - restart */
218 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_MSTA
| CCR_MTX
| flags
);
219 /* Write target address byte - this time with the read flag set */
220 writeb((target
<< 1) | 1, i2c
->base
+ MPC_I2C_DR
);
222 if (i2c_wait(i2c
, timeout
, 1) < 0)
227 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_MSTA
| CCR_TXAK
);
229 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_MSTA
);
231 readb(i2c
->base
+ MPC_I2C_DR
);
234 for (i
= 0; i
< length
; i
++) {
235 if (i2c_wait(i2c
, timeout
, 0) < 0)
238 /* Generate txack on next to last byte */
240 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_MSTA
| CCR_TXAK
);
241 /* Generate stop on last byte */
243 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_TXAK
);
244 data
[i
] = readb(i2c
->base
+ MPC_I2C_DR
);
250 static int mpc_xfer(struct i2c_adapter
*adap
, struct i2c_msg
*msgs
, int num
)
252 struct i2c_msg
*pmsg
;
255 unsigned long orig_jiffies
= jiffies
;
256 struct mpc_i2c
*i2c
= i2c_get_adapdata(adap
);
260 /* Allow bus up to 1s to become not busy */
261 while (readb(i2c
->base
+ MPC_I2C_SR
) & CSR_MBB
) {
262 if (signal_pending(current
)) {
263 pr_debug("I2C: Interrupted\n");
266 if (time_after(jiffies
, orig_jiffies
+ HZ
)) {
267 pr_debug("I2C: timeout\n");
268 if (readb(i2c
->base
+ MPC_I2C_SR
) ==
269 (CSR_MCF
| CSR_MBB
| CSR_RXAK
))
276 for (i
= 0; ret
>= 0 && i
< num
; i
++) {
278 pr_debug("Doing %s %d bytes to 0x%02x - %d of %d messages\n",
279 pmsg
->flags
& I2C_M_RD
? "read" : "write",
280 pmsg
->len
, pmsg
->addr
, i
+ 1, num
);
281 if (pmsg
->flags
& I2C_M_RD
)
283 mpc_read(i2c
, pmsg
->addr
, pmsg
->buf
, pmsg
->len
, i
);
286 mpc_write(i2c
, pmsg
->addr
, pmsg
->buf
, pmsg
->len
, i
);
289 return (ret
< 0) ? ret
: num
;
292 static u32
mpc_functionality(struct i2c_adapter
*adap
)
294 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
297 static const struct i2c_algorithm mpc_algo
= {
298 .master_xfer
= mpc_xfer
,
299 .functionality
= mpc_functionality
,
302 static struct i2c_adapter mpc_ops
= {
303 .owner
= THIS_MODULE
,
304 .name
= "MPC adapter",
307 .class = I2C_CLASS_HWMON
,
312 static int fsl_i2c_probe(struct platform_device
*pdev
)
316 struct fsl_i2c_platform_data
*pdata
;
317 struct resource
*r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
319 pdata
= (struct fsl_i2c_platform_data
*) pdev
->dev
.platform_data
;
321 if (!(i2c
= kzalloc(sizeof(*i2c
), GFP_KERNEL
))) {
325 i2c
->irq
= platform_get_irq(pdev
, 0);
330 i2c
->flags
= pdata
->device_flags
;
331 init_waitqueue_head(&i2c
->queue
);
333 i2c
->base
= ioremap((phys_addr_t
)r
->start
, MPC_I2C_REGION
);
336 printk(KERN_ERR
"i2c-mpc - failed to map controller\n");
342 if ((result
= request_irq(i2c
->irq
, mpc_i2c_isr
,
343 IRQF_SHARED
, "i2c-mpc", i2c
)) < 0) {
345 "i2c-mpc - failed to attach interrupt\n");
349 mpc_i2c_setclock(i2c
);
350 platform_set_drvdata(pdev
, i2c
);
353 i2c
->adap
.nr
= pdev
->id
;
354 i2c_set_adapdata(&i2c
->adap
, i2c
);
355 i2c
->adap
.dev
.parent
= &pdev
->dev
;
356 if ((result
= i2c_add_numbered_adapter(&i2c
->adap
)) < 0) {
357 printk(KERN_ERR
"i2c-mpc - failed to add adapter\n");
365 free_irq(i2c
->irq
, NULL
);
374 static int fsl_i2c_remove(struct platform_device
*pdev
)
376 struct mpc_i2c
*i2c
= platform_get_drvdata(pdev
);
378 i2c_del_adapter(&i2c
->adap
);
379 platform_set_drvdata(pdev
, NULL
);
382 free_irq(i2c
->irq
, i2c
);
389 /* Structure for a device driver */
390 static struct platform_driver fsl_i2c_driver
= {
391 .probe
= fsl_i2c_probe
,
392 .remove
= fsl_i2c_remove
,
394 .owner
= THIS_MODULE
,
399 static int __init
fsl_i2c_init(void)
401 return platform_driver_register(&fsl_i2c_driver
);
404 static void __exit
fsl_i2c_exit(void)
406 platform_driver_unregister(&fsl_i2c_driver
);
409 module_init(fsl_i2c_init
);
410 module_exit(fsl_i2c_exit
);
412 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
414 ("I2C-Bus adapter for MPC107 bridge and MPC824x/85xx/52xx processors");
415 MODULE_LICENSE("GPL");