2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Xudong Chen <xudong.chen@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/clk.h>
16 #include <linux/completion.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/err.h>
21 #include <linux/errno.h>
22 #include <linux/i2c.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
26 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/platform_device.h>
32 #include <linux/scatterlist.h>
33 #include <linux/sched.h>
34 #include <linux/slab.h>
36 #define I2C_RS_TRANSFER (1 << 4)
37 #define I2C_HS_NACKERR (1 << 2)
38 #define I2C_ACKERR (1 << 1)
39 #define I2C_TRANSAC_COMP (1 << 0)
40 #define I2C_TRANSAC_START (1 << 0)
41 #define I2C_RS_MUL_CNFG (1 << 15)
42 #define I2C_RS_MUL_TRIG (1 << 14)
43 #define I2C_DCM_DISABLE 0x0000
44 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
45 #define I2C_IO_CONFIG_PUSH_PULL 0x0000
46 #define I2C_SOFT_RST 0x0001
47 #define I2C_FIFO_ADDR_CLR 0x0001
48 #define I2C_DELAY_LEN 0x0002
49 #define I2C_ST_START_CON 0x8001
50 #define I2C_FS_START_CON 0x1800
51 #define I2C_TIME_CLR_VALUE 0x0000
52 #define I2C_TIME_DEFAULT_VALUE 0x0003
53 #define I2C_FS_TIME_INIT_VALUE 0x1303
54 #define I2C_WRRD_TRANAC_VALUE 0x0002
55 #define I2C_RD_TRANAC_VALUE 0x0001
57 #define I2C_DMA_CON_TX 0x0000
58 #define I2C_DMA_CON_RX 0x0001
59 #define I2C_DMA_START_EN 0x0001
60 #define I2C_DMA_INT_FLAG_NONE 0x0000
61 #define I2C_DMA_CLR_FLAG 0x0000
62 #define I2C_DMA_HARD_RST 0x0002
63 #define I2C_DMA_4G_MODE 0x0001
65 #define I2C_DEFAULT_SPEED 100000 /* hz */
66 #define MAX_FS_MODE_SPEED 400000
67 #define MAX_HS_MODE_SPEED 3400000
68 #define MAX_SAMPLE_CNT_DIV 8
69 #define MAX_STEP_CNT_DIV 64
70 #define MAX_HS_STEP_CNT_DIV 8
72 #define I2C_CONTROL_RS (0x1 << 1)
73 #define I2C_CONTROL_DMA_EN (0x1 << 2)
74 #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3)
75 #define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
76 #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
77 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
78 #define I2C_CONTROL_WRAPPER (0x1 << 0)
80 #define I2C_DRV_NAME "i2c-mt65xx"
82 enum DMA_REGS_OFFSET
{
83 OFFSET_INT_FLAG
= 0x0,
88 OFFSET_TX_MEM_ADDR
= 0x1c,
89 OFFSET_RX_MEM_ADDR
= 0x20,
92 OFFSET_TX_4G_MODE
= 0x54,
93 OFFSET_RX_4G_MODE
= 0x58,
96 enum i2c_trans_st_rs
{
98 I2C_TRANS_REPEATED_START
,
107 enum I2C_REGS_OFFSET
{
108 OFFSET_DATA_PORT
= 0x0,
109 OFFSET_SLAVE_ADDR
= 0x04,
110 OFFSET_INTR_MASK
= 0x08,
111 OFFSET_INTR_STAT
= 0x0c,
112 OFFSET_CONTROL
= 0x10,
113 OFFSET_TRANSFER_LEN
= 0x14,
114 OFFSET_TRANSAC_LEN
= 0x18,
115 OFFSET_DELAY_LEN
= 0x1c,
116 OFFSET_TIMING
= 0x20,
118 OFFSET_EXT_CONF
= 0x28,
119 OFFSET_FIFO_STAT
= 0x30,
120 OFFSET_FIFO_THRESH
= 0x34,
121 OFFSET_FIFO_ADDR_CLR
= 0x38,
122 OFFSET_IO_CONFIG
= 0x40,
123 OFFSET_RSV_DEBUG
= 0x44,
125 OFFSET_SOFTRESET
= 0x50,
126 OFFSET_DCM_EN
= 0x54,
127 OFFSET_PATH_DIR
= 0x60,
128 OFFSET_DEBUGSTAT
= 0x64,
129 OFFSET_DEBUGCTRL
= 0x68,
130 OFFSET_TRANSFER_LEN_AUX
= 0x6c,
133 struct mtk_i2c_compatible
{
134 const struct i2c_adapter_quirks
*quirks
;
135 unsigned char pmic_i2c
: 1;
136 unsigned char dcm
: 1;
137 unsigned char auto_restart
: 1;
138 unsigned char aux_len_reg
: 1;
139 unsigned char support_33bits
: 1;
143 struct i2c_adapter adap
; /* i2c host adapter */
145 struct completion msg_complete
;
147 /* set in i2c probe */
148 void __iomem
*base
; /* i2c base addr */
149 void __iomem
*pdmabase
; /* dma base address*/
150 struct clk
*clk_main
; /* main clock for i2c bus */
151 struct clk
*clk_dma
; /* DMA clock for i2c via DMA */
152 struct clk
*clk_pmic
; /* PMIC clock for i2c from PMIC */
153 bool have_pmic
; /* can use i2c pins from PMIC */
154 bool use_push_pull
; /* IO config push-pull mode */
156 u16 irq_stat
; /* interrupt status */
157 unsigned int speed_hz
; /* The speed in transfer */
158 enum mtk_trans_op op
;
161 unsigned char auto_restart
;
162 bool ignore_restart_irq
;
163 const struct mtk_i2c_compatible
*dev_comp
;
166 static const struct i2c_adapter_quirks mt6577_i2c_quirks
= {
167 .flags
= I2C_AQ_COMB_WRITE_THEN_READ
,
169 .max_write_len
= 255,
171 .max_comb_1st_msg_len
= 255,
172 .max_comb_2nd_msg_len
= 31,
175 static const struct i2c_adapter_quirks mt8173_i2c_quirks
= {
176 .max_num_msgs
= 65535,
177 .max_write_len
= 65535,
178 .max_read_len
= 65535,
179 .max_comb_1st_msg_len
= 65535,
180 .max_comb_2nd_msg_len
= 65535,
183 static const struct mtk_i2c_compatible mt6577_compat
= {
184 .quirks
= &mt6577_i2c_quirks
,
192 static const struct mtk_i2c_compatible mt6589_compat
= {
193 .quirks
= &mt6577_i2c_quirks
,
201 static const struct mtk_i2c_compatible mt8173_compat
= {
202 .quirks
= &mt8173_i2c_quirks
,
210 static const struct of_device_id mtk_i2c_of_match
[] = {
211 { .compatible
= "mediatek,mt6577-i2c", .data
= &mt6577_compat
},
212 { .compatible
= "mediatek,mt6589-i2c", .data
= &mt6589_compat
},
213 { .compatible
= "mediatek,mt8173-i2c", .data
= &mt8173_compat
},
216 MODULE_DEVICE_TABLE(of
, mtk_i2c_of_match
);
218 static int mtk_i2c_clock_enable(struct mtk_i2c
*i2c
)
222 ret
= clk_prepare_enable(i2c
->clk_dma
);
226 ret
= clk_prepare_enable(i2c
->clk_main
);
230 if (i2c
->have_pmic
) {
231 ret
= clk_prepare_enable(i2c
->clk_pmic
);
238 clk_disable_unprepare(i2c
->clk_main
);
240 clk_disable_unprepare(i2c
->clk_dma
);
245 static void mtk_i2c_clock_disable(struct mtk_i2c
*i2c
)
248 clk_disable_unprepare(i2c
->clk_pmic
);
250 clk_disable_unprepare(i2c
->clk_main
);
251 clk_disable_unprepare(i2c
->clk_dma
);
254 static void mtk_i2c_init_hw(struct mtk_i2c
*i2c
)
258 writew(I2C_SOFT_RST
, i2c
->base
+ OFFSET_SOFTRESET
);
261 if (i2c
->use_push_pull
)
262 writew(I2C_IO_CONFIG_PUSH_PULL
, i2c
->base
+ OFFSET_IO_CONFIG
);
264 writew(I2C_IO_CONFIG_OPEN_DRAIN
, i2c
->base
+ OFFSET_IO_CONFIG
);
266 if (i2c
->dev_comp
->dcm
)
267 writew(I2C_DCM_DISABLE
, i2c
->base
+ OFFSET_DCM_EN
);
269 writew(i2c
->timing_reg
, i2c
->base
+ OFFSET_TIMING
);
270 writew(i2c
->high_speed_reg
, i2c
->base
+ OFFSET_HS
);
272 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
274 writew(I2C_CONTROL_WRAPPER
, i2c
->base
+ OFFSET_PATH_DIR
);
276 control_reg
= I2C_CONTROL_ACKERR_DET_EN
|
277 I2C_CONTROL_CLK_EXT_EN
| I2C_CONTROL_DMA_EN
;
278 writew(control_reg
, i2c
->base
+ OFFSET_CONTROL
);
279 writew(I2C_DELAY_LEN
, i2c
->base
+ OFFSET_DELAY_LEN
);
281 writel(I2C_DMA_HARD_RST
, i2c
->pdmabase
+ OFFSET_RST
);
283 writel(I2C_DMA_CLR_FLAG
, i2c
->pdmabase
+ OFFSET_RST
);
287 * Calculate i2c port speed
290 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
291 * clock_div: fixed in hardware, but may be various in different SoCs
293 * The calculation want to pick the highest bus frequency that is still
294 * less than or equal to i2c->speed_hz. The calculation try to get
295 * sample_cnt and step_cn
297 static int mtk_i2c_set_speed(struct mtk_i2c
*i2c
, unsigned int parent_clk
,
298 unsigned int clock_div
)
300 unsigned int clk_src
;
301 unsigned int step_cnt
;
302 unsigned int sample_cnt
;
303 unsigned int max_step_cnt
;
304 unsigned int target_speed
;
305 unsigned int base_sample_cnt
= MAX_SAMPLE_CNT_DIV
;
306 unsigned int base_step_cnt
;
307 unsigned int opt_div
;
308 unsigned int best_mul
;
309 unsigned int cnt_mul
;
311 clk_src
= parent_clk
/ clock_div
;
312 target_speed
= i2c
->speed_hz
;
314 if (target_speed
> MAX_HS_MODE_SPEED
)
315 target_speed
= MAX_HS_MODE_SPEED
;
317 if (target_speed
> MAX_FS_MODE_SPEED
)
318 max_step_cnt
= MAX_HS_STEP_CNT_DIV
;
320 max_step_cnt
= MAX_STEP_CNT_DIV
;
322 base_step_cnt
= max_step_cnt
;
323 /* Find the best combination */
324 opt_div
= DIV_ROUND_UP(clk_src
>> 1, target_speed
);
325 best_mul
= MAX_SAMPLE_CNT_DIV
* max_step_cnt
;
327 /* Search for the best pair (sample_cnt, step_cnt) with
328 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
329 * 0 < step_cnt < max_step_cnt
330 * sample_cnt * step_cnt >= opt_div
331 * optimizing for sample_cnt * step_cnt being minimal
333 for (sample_cnt
= 1; sample_cnt
<= MAX_SAMPLE_CNT_DIV
; sample_cnt
++) {
334 step_cnt
= DIV_ROUND_UP(opt_div
, sample_cnt
);
335 cnt_mul
= step_cnt
* sample_cnt
;
336 if (step_cnt
> max_step_cnt
)
339 if (cnt_mul
< best_mul
) {
341 base_sample_cnt
= sample_cnt
;
342 base_step_cnt
= step_cnt
;
343 if (best_mul
== opt_div
)
348 sample_cnt
= base_sample_cnt
;
349 step_cnt
= base_step_cnt
;
351 if ((clk_src
/ (2 * sample_cnt
* step_cnt
)) > target_speed
) {
352 /* In this case, hardware can't support such
355 dev_dbg(i2c
->dev
, "Unsupported speed (%uhz)\n", target_speed
);
362 if (target_speed
> MAX_FS_MODE_SPEED
) {
363 /* Set the high speed mode register */
364 i2c
->timing_reg
= I2C_FS_TIME_INIT_VALUE
;
365 i2c
->high_speed_reg
= I2C_TIME_DEFAULT_VALUE
|
366 (sample_cnt
<< 12) | (step_cnt
<< 8);
368 i2c
->timing_reg
= (sample_cnt
<< 8) | (step_cnt
<< 0);
369 /* Disable the high speed transaction */
370 i2c
->high_speed_reg
= I2C_TIME_CLR_VALUE
;
376 static inline u32
mtk_i2c_set_4g_mode(dma_addr_t addr
)
378 return (addr
& BIT_ULL(32)) ? I2C_DMA_4G_MODE
: I2C_DMA_CLR_FLAG
;
381 static int mtk_i2c_do_transfer(struct mtk_i2c
*i2c
, struct i2c_msg
*msgs
,
382 int num
, int left_num
)
387 u16 restart_flag
= 0;
389 dma_addr_t rpaddr
= 0;
390 dma_addr_t wpaddr
= 0;
395 if (i2c
->auto_restart
)
396 restart_flag
= I2C_RS_TRANSFER
;
398 reinit_completion(&i2c
->msg_complete
);
400 control_reg
= readw(i2c
->base
+ OFFSET_CONTROL
) &
401 ~(I2C_CONTROL_DIR_CHANGE
| I2C_CONTROL_RS
);
402 if ((i2c
->speed_hz
> 400000) || (left_num
>= 1))
403 control_reg
|= I2C_CONTROL_RS
;
405 if (i2c
->op
== I2C_MASTER_WRRD
)
406 control_reg
|= I2C_CONTROL_DIR_CHANGE
| I2C_CONTROL_RS
;
408 writew(control_reg
, i2c
->base
+ OFFSET_CONTROL
);
410 /* set start condition */
411 if (i2c
->speed_hz
<= 100000)
412 writew(I2C_ST_START_CON
, i2c
->base
+ OFFSET_EXT_CONF
);
414 writew(I2C_FS_START_CON
, i2c
->base
+ OFFSET_EXT_CONF
);
416 addr_reg
= i2c_8bit_addr_from_msg(msgs
);
417 writew(addr_reg
, i2c
->base
+ OFFSET_SLAVE_ADDR
);
419 /* Clear interrupt status */
420 writew(restart_flag
| I2C_HS_NACKERR
| I2C_ACKERR
|
421 I2C_TRANSAC_COMP
, i2c
->base
+ OFFSET_INTR_STAT
);
422 writew(I2C_FIFO_ADDR_CLR
, i2c
->base
+ OFFSET_FIFO_ADDR_CLR
);
424 /* Enable interrupt */
425 writew(restart_flag
| I2C_HS_NACKERR
| I2C_ACKERR
|
426 I2C_TRANSAC_COMP
, i2c
->base
+ OFFSET_INTR_MASK
);
428 /* Set transfer and transaction len */
429 if (i2c
->op
== I2C_MASTER_WRRD
) {
430 if (i2c
->dev_comp
->aux_len_reg
) {
431 writew(msgs
->len
, i2c
->base
+ OFFSET_TRANSFER_LEN
);
432 writew((msgs
+ 1)->len
, i2c
->base
+
433 OFFSET_TRANSFER_LEN_AUX
);
435 writew(msgs
->len
| ((msgs
+ 1)->len
) << 8,
436 i2c
->base
+ OFFSET_TRANSFER_LEN
);
438 writew(I2C_WRRD_TRANAC_VALUE
, i2c
->base
+ OFFSET_TRANSAC_LEN
);
440 writew(msgs
->len
, i2c
->base
+ OFFSET_TRANSFER_LEN
);
441 writew(num
, i2c
->base
+ OFFSET_TRANSAC_LEN
);
444 /* Prepare buffer data to start transfer */
445 if (i2c
->op
== I2C_MASTER_RD
) {
446 writel(I2C_DMA_INT_FLAG_NONE
, i2c
->pdmabase
+ OFFSET_INT_FLAG
);
447 writel(I2C_DMA_CON_RX
, i2c
->pdmabase
+ OFFSET_CON
);
448 rpaddr
= dma_map_single(i2c
->dev
, msgs
->buf
,
449 msgs
->len
, DMA_FROM_DEVICE
);
450 if (dma_mapping_error(i2c
->dev
, rpaddr
))
453 if (i2c
->dev_comp
->support_33bits
) {
454 reg_4g_mode
= mtk_i2c_set_4g_mode(rpaddr
);
455 writel(reg_4g_mode
, i2c
->pdmabase
+ OFFSET_RX_4G_MODE
);
458 writel((u32
)rpaddr
, i2c
->pdmabase
+ OFFSET_RX_MEM_ADDR
);
459 writel(msgs
->len
, i2c
->pdmabase
+ OFFSET_RX_LEN
);
460 } else if (i2c
->op
== I2C_MASTER_WR
) {
461 writel(I2C_DMA_INT_FLAG_NONE
, i2c
->pdmabase
+ OFFSET_INT_FLAG
);
462 writel(I2C_DMA_CON_TX
, i2c
->pdmabase
+ OFFSET_CON
);
463 wpaddr
= dma_map_single(i2c
->dev
, msgs
->buf
,
464 msgs
->len
, DMA_TO_DEVICE
);
465 if (dma_mapping_error(i2c
->dev
, wpaddr
))
468 if (i2c
->dev_comp
->support_33bits
) {
469 reg_4g_mode
= mtk_i2c_set_4g_mode(wpaddr
);
470 writel(reg_4g_mode
, i2c
->pdmabase
+ OFFSET_TX_4G_MODE
);
473 writel((u32
)wpaddr
, i2c
->pdmabase
+ OFFSET_TX_MEM_ADDR
);
474 writel(msgs
->len
, i2c
->pdmabase
+ OFFSET_TX_LEN
);
476 writel(I2C_DMA_CLR_FLAG
, i2c
->pdmabase
+ OFFSET_INT_FLAG
);
477 writel(I2C_DMA_CLR_FLAG
, i2c
->pdmabase
+ OFFSET_CON
);
478 wpaddr
= dma_map_single(i2c
->dev
, msgs
->buf
,
479 msgs
->len
, DMA_TO_DEVICE
);
480 if (dma_mapping_error(i2c
->dev
, wpaddr
))
482 rpaddr
= dma_map_single(i2c
->dev
, (msgs
+ 1)->buf
,
485 if (dma_mapping_error(i2c
->dev
, rpaddr
)) {
486 dma_unmap_single(i2c
->dev
, wpaddr
,
487 msgs
->len
, DMA_TO_DEVICE
);
491 if (i2c
->dev_comp
->support_33bits
) {
492 reg_4g_mode
= mtk_i2c_set_4g_mode(wpaddr
);
493 writel(reg_4g_mode
, i2c
->pdmabase
+ OFFSET_TX_4G_MODE
);
495 reg_4g_mode
= mtk_i2c_set_4g_mode(rpaddr
);
496 writel(reg_4g_mode
, i2c
->pdmabase
+ OFFSET_RX_4G_MODE
);
499 writel((u32
)wpaddr
, i2c
->pdmabase
+ OFFSET_TX_MEM_ADDR
);
500 writel((u32
)rpaddr
, i2c
->pdmabase
+ OFFSET_RX_MEM_ADDR
);
501 writel(msgs
->len
, i2c
->pdmabase
+ OFFSET_TX_LEN
);
502 writel((msgs
+ 1)->len
, i2c
->pdmabase
+ OFFSET_RX_LEN
);
505 writel(I2C_DMA_START_EN
, i2c
->pdmabase
+ OFFSET_EN
);
507 if (!i2c
->auto_restart
) {
508 start_reg
= I2C_TRANSAC_START
;
510 start_reg
= I2C_TRANSAC_START
| I2C_RS_MUL_TRIG
;
512 start_reg
|= I2C_RS_MUL_CNFG
;
514 writew(start_reg
, i2c
->base
+ OFFSET_START
);
516 ret
= wait_for_completion_timeout(&i2c
->msg_complete
,
519 /* Clear interrupt mask */
520 writew(~(restart_flag
| I2C_HS_NACKERR
| I2C_ACKERR
|
521 I2C_TRANSAC_COMP
), i2c
->base
+ OFFSET_INTR_MASK
);
523 if (i2c
->op
== I2C_MASTER_WR
) {
524 dma_unmap_single(i2c
->dev
, wpaddr
,
525 msgs
->len
, DMA_TO_DEVICE
);
526 } else if (i2c
->op
== I2C_MASTER_RD
) {
527 dma_unmap_single(i2c
->dev
, rpaddr
,
528 msgs
->len
, DMA_FROM_DEVICE
);
530 dma_unmap_single(i2c
->dev
, wpaddr
, msgs
->len
,
532 dma_unmap_single(i2c
->dev
, rpaddr
, (msgs
+ 1)->len
,
537 dev_dbg(i2c
->dev
, "addr: %x, transfer timeout\n", msgs
->addr
);
538 mtk_i2c_init_hw(i2c
);
542 completion_done(&i2c
->msg_complete
);
544 if (i2c
->irq_stat
& (I2C_HS_NACKERR
| I2C_ACKERR
)) {
545 dev_dbg(i2c
->dev
, "addr: %x, transfer ACK error\n", msgs
->addr
);
546 mtk_i2c_init_hw(i2c
);
553 static int mtk_i2c_transfer(struct i2c_adapter
*adap
,
554 struct i2c_msg msgs
[], int num
)
558 struct mtk_i2c
*i2c
= i2c_get_adapdata(adap
);
560 ret
= mtk_i2c_clock_enable(i2c
);
564 i2c
->auto_restart
= i2c
->dev_comp
->auto_restart
;
566 /* checking if we can skip restart and optimize using WRRD mode */
567 if (i2c
->auto_restart
&& num
== 2) {
568 if (!(msgs
[0].flags
& I2C_M_RD
) && (msgs
[1].flags
& I2C_M_RD
) &&
569 msgs
[0].addr
== msgs
[1].addr
) {
570 i2c
->auto_restart
= 0;
574 if (i2c
->auto_restart
&& num
>= 2 && i2c
->speed_hz
> MAX_FS_MODE_SPEED
)
575 /* ignore the first restart irq after the master code,
576 * otherwise the first transfer will be discarded.
578 i2c
->ignore_restart_irq
= true;
580 i2c
->ignore_restart_irq
= false;
584 dev_dbg(i2c
->dev
, "data buffer is NULL.\n");
589 if (msgs
->flags
& I2C_M_RD
)
590 i2c
->op
= I2C_MASTER_RD
;
592 i2c
->op
= I2C_MASTER_WR
;
594 if (!i2c
->auto_restart
) {
596 /* combined two messages into one transaction */
597 i2c
->op
= I2C_MASTER_WRRD
;
602 /* always use DMA mode. */
603 ret
= mtk_i2c_do_transfer(i2c
, msgs
, num
, left_num
);
609 /* the return value is number of executed messages */
613 mtk_i2c_clock_disable(i2c
);
617 static irqreturn_t
mtk_i2c_irq(int irqno
, void *dev_id
)
619 struct mtk_i2c
*i2c
= dev_id
;
620 u16 restart_flag
= 0;
623 if (i2c
->auto_restart
)
624 restart_flag
= I2C_RS_TRANSFER
;
626 intr_stat
= readw(i2c
->base
+ OFFSET_INTR_STAT
);
627 writew(intr_stat
, i2c
->base
+ OFFSET_INTR_STAT
);
630 * when occurs ack error, i2c controller generate two interrupts
631 * first is the ack error interrupt, then the complete interrupt
632 * i2c->irq_stat need keep the two interrupt value.
634 i2c
->irq_stat
|= intr_stat
;
636 if (i2c
->ignore_restart_irq
&& (i2c
->irq_stat
& restart_flag
)) {
637 i2c
->ignore_restart_irq
= false;
639 writew(I2C_RS_MUL_CNFG
| I2C_RS_MUL_TRIG
| I2C_TRANSAC_START
,
640 i2c
->base
+ OFFSET_START
);
642 if (i2c
->irq_stat
& (I2C_TRANSAC_COMP
| restart_flag
))
643 complete(&i2c
->msg_complete
);
649 static u32
mtk_i2c_functionality(struct i2c_adapter
*adap
)
651 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
654 static const struct i2c_algorithm mtk_i2c_algorithm
= {
655 .master_xfer
= mtk_i2c_transfer
,
656 .functionality
= mtk_i2c_functionality
,
659 static int mtk_i2c_parse_dt(struct device_node
*np
, struct mtk_i2c
*i2c
,
660 unsigned int *clk_src_div
)
664 ret
= of_property_read_u32(np
, "clock-frequency", &i2c
->speed_hz
);
666 i2c
->speed_hz
= I2C_DEFAULT_SPEED
;
668 ret
= of_property_read_u32(np
, "clock-div", clk_src_div
);
672 if (*clk_src_div
== 0)
675 i2c
->have_pmic
= of_property_read_bool(np
, "mediatek,have-pmic");
677 of_property_read_bool(np
, "mediatek,use-push-pull");
682 static int mtk_i2c_probe(struct platform_device
*pdev
)
684 const struct of_device_id
*of_id
;
688 unsigned int clk_src_div
;
689 struct resource
*res
;
692 i2c
= devm_kzalloc(&pdev
->dev
, sizeof(*i2c
), GFP_KERNEL
);
696 ret
= mtk_i2c_parse_dt(pdev
->dev
.of_node
, i2c
, &clk_src_div
);
700 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
701 i2c
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
702 if (IS_ERR(i2c
->base
))
703 return PTR_ERR(i2c
->base
);
705 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
706 i2c
->pdmabase
= devm_ioremap_resource(&pdev
->dev
, res
);
707 if (IS_ERR(i2c
->pdmabase
))
708 return PTR_ERR(i2c
->pdmabase
);
710 irq
= platform_get_irq(pdev
, 0);
714 init_completion(&i2c
->msg_complete
);
716 of_id
= of_match_node(mtk_i2c_of_match
, pdev
->dev
.of_node
);
720 i2c
->dev_comp
= of_id
->data
;
721 i2c
->adap
.dev
.of_node
= pdev
->dev
.of_node
;
722 i2c
->dev
= &pdev
->dev
;
723 i2c
->adap
.dev
.parent
= &pdev
->dev
;
724 i2c
->adap
.owner
= THIS_MODULE
;
725 i2c
->adap
.algo
= &mtk_i2c_algorithm
;
726 i2c
->adap
.quirks
= i2c
->dev_comp
->quirks
;
727 i2c
->adap
.timeout
= 2 * HZ
;
728 i2c
->adap
.retries
= 1;
730 if (i2c
->have_pmic
&& !i2c
->dev_comp
->pmic_i2c
)
733 i2c
->clk_main
= devm_clk_get(&pdev
->dev
, "main");
734 if (IS_ERR(i2c
->clk_main
)) {
735 dev_err(&pdev
->dev
, "cannot get main clock\n");
736 return PTR_ERR(i2c
->clk_main
);
739 i2c
->clk_dma
= devm_clk_get(&pdev
->dev
, "dma");
740 if (IS_ERR(i2c
->clk_dma
)) {
741 dev_err(&pdev
->dev
, "cannot get dma clock\n");
742 return PTR_ERR(i2c
->clk_dma
);
746 if (i2c
->have_pmic
) {
747 i2c
->clk_pmic
= devm_clk_get(&pdev
->dev
, "pmic");
748 if (IS_ERR(i2c
->clk_pmic
)) {
749 dev_err(&pdev
->dev
, "cannot get pmic clock\n");
750 return PTR_ERR(i2c
->clk_pmic
);
755 strlcpy(i2c
->adap
.name
, I2C_DRV_NAME
, sizeof(i2c
->adap
.name
));
757 ret
= mtk_i2c_set_speed(i2c
, clk_get_rate(clk
), clk_src_div
);
759 dev_err(&pdev
->dev
, "Failed to set the speed.\n");
763 if (i2c
->dev_comp
->support_33bits
) {
764 ret
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(33));
766 dev_err(&pdev
->dev
, "dma_set_mask return error.\n");
771 ret
= mtk_i2c_clock_enable(i2c
);
773 dev_err(&pdev
->dev
, "clock enable failed!\n");
776 mtk_i2c_init_hw(i2c
);
777 mtk_i2c_clock_disable(i2c
);
779 ret
= devm_request_irq(&pdev
->dev
, irq
, mtk_i2c_irq
,
780 IRQF_TRIGGER_NONE
, I2C_DRV_NAME
, i2c
);
783 "Request I2C IRQ %d fail\n", irq
);
787 i2c_set_adapdata(&i2c
->adap
, i2c
);
788 ret
= i2c_add_adapter(&i2c
->adap
);
790 dev_err(&pdev
->dev
, "Failed to add i2c bus to i2c core\n");
794 platform_set_drvdata(pdev
, i2c
);
799 static int mtk_i2c_remove(struct platform_device
*pdev
)
801 struct mtk_i2c
*i2c
= platform_get_drvdata(pdev
);
803 i2c_del_adapter(&i2c
->adap
);
808 #ifdef CONFIG_PM_SLEEP
809 static int mtk_i2c_resume(struct device
*dev
)
811 struct mtk_i2c
*i2c
= dev_get_drvdata(dev
);
813 mtk_i2c_init_hw(i2c
);
819 static const struct dev_pm_ops mtk_i2c_pm
= {
820 SET_SYSTEM_SLEEP_PM_OPS(NULL
, mtk_i2c_resume
)
823 static struct platform_driver mtk_i2c_driver
= {
824 .probe
= mtk_i2c_probe
,
825 .remove
= mtk_i2c_remove
,
827 .name
= I2C_DRV_NAME
,
829 .of_match_table
= of_match_ptr(mtk_i2c_of_match
),
833 module_platform_driver(mtk_i2c_driver
);
835 MODULE_LICENSE("GPL v2");
836 MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
837 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");