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i2c: mv64xxx: use BIT() macro for register value definitions
[deliverable/linux.git] / drivers / i2c / busses / i2c-mv64xxx.c
1 /*
2 * Driver for the i2c controller on the Marvell line of host bridges
3 * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
4 *
5 * Author: Mark A. Greer <mgreer@mvista.com>
6 *
7 * 2005 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/spinlock.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
18 #include <linux/mv643xx_i2c.h>
19 #include <linux/platform_device.h>
20 #include <linux/reset.h>
21 #include <linux/io.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/of_irq.h>
25 #include <linux/clk.h>
26 #include <linux/err.h>
27 #include <linux/delay.h>
28
29 #define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1)
30 #define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7)
31 #define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3)
32
33 #define MV64XXX_I2C_REG_CONTROL_ACK BIT(2)
34 #define MV64XXX_I2C_REG_CONTROL_IFLG BIT(3)
35 #define MV64XXX_I2C_REG_CONTROL_STOP BIT(4)
36 #define MV64XXX_I2C_REG_CONTROL_START BIT(5)
37 #define MV64XXX_I2C_REG_CONTROL_TWSIEN BIT(6)
38 #define MV64XXX_I2C_REG_CONTROL_INTEN BIT(7)
39
40 /* Ctlr status values */
41 #define MV64XXX_I2C_STATUS_BUS_ERR 0x00
42 #define MV64XXX_I2C_STATUS_MAST_START 0x08
43 #define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
44 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
45 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
46 #define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
47 #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
48 #define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
49 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
50 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
51 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
52 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
53 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
54 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
55 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
56 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
57 #define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
58
59 /* Register defines (I2C bridge) */
60 #define MV64XXX_I2C_REG_TX_DATA_LO 0xc0
61 #define MV64XXX_I2C_REG_TX_DATA_HI 0xc4
62 #define MV64XXX_I2C_REG_RX_DATA_LO 0xc8
63 #define MV64XXX_I2C_REG_RX_DATA_HI 0xcc
64 #define MV64XXX_I2C_REG_BRIDGE_CONTROL 0xd0
65 #define MV64XXX_I2C_REG_BRIDGE_STATUS 0xd4
66 #define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE 0xd8
67 #define MV64XXX_I2C_REG_BRIDGE_INTR_MASK 0xdC
68 #define MV64XXX_I2C_REG_BRIDGE_TIMING 0xe0
69
70 /* Bridge Control values */
71 #define MV64XXX_I2C_BRIDGE_CONTROL_WR BIT(0)
72 #define MV64XXX_I2C_BRIDGE_CONTROL_RD BIT(1)
73 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT 2
74 #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT BIT(12)
75 #define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13
76 #define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16
77 #define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE BIT(19)
78
79 /* Bridge Status values */
80 #define MV64XXX_I2C_BRIDGE_STATUS_ERROR BIT(0)
81 #define MV64XXX_I2C_STATUS_OFFLOAD_ERROR 0xf0000001
82 #define MV64XXX_I2C_STATUS_OFFLOAD_OK 0xf0000000
83
84
85 /* Driver states */
86 enum {
87 MV64XXX_I2C_STATE_INVALID,
88 MV64XXX_I2C_STATE_IDLE,
89 MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
90 MV64XXX_I2C_STATE_WAITING_FOR_RESTART,
91 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
92 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
93 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
94 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
95 };
96
97 /* Driver actions */
98 enum {
99 MV64XXX_I2C_ACTION_INVALID,
100 MV64XXX_I2C_ACTION_CONTINUE,
101 MV64XXX_I2C_ACTION_SEND_RESTART,
102 MV64XXX_I2C_ACTION_OFFLOAD_RESTART,
103 MV64XXX_I2C_ACTION_SEND_ADDR_1,
104 MV64XXX_I2C_ACTION_SEND_ADDR_2,
105 MV64XXX_I2C_ACTION_SEND_DATA,
106 MV64XXX_I2C_ACTION_RCV_DATA,
107 MV64XXX_I2C_ACTION_RCV_DATA_STOP,
108 MV64XXX_I2C_ACTION_SEND_STOP,
109 MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP,
110 };
111
112 struct mv64xxx_i2c_regs {
113 u8 addr;
114 u8 ext_addr;
115 u8 data;
116 u8 control;
117 u8 status;
118 u8 clock;
119 u8 soft_reset;
120 };
121
122 struct mv64xxx_i2c_data {
123 struct i2c_msg *msgs;
124 int num_msgs;
125 int irq;
126 u32 state;
127 u32 action;
128 u32 aborting;
129 u32 cntl_bits;
130 void __iomem *reg_base;
131 struct mv64xxx_i2c_regs reg_offsets;
132 u32 addr1;
133 u32 addr2;
134 u32 bytes_left;
135 u32 byte_posn;
136 u32 send_stop;
137 u32 block;
138 int rc;
139 u32 freq_m;
140 u32 freq_n;
141 #if defined(CONFIG_HAVE_CLK)
142 struct clk *clk;
143 #endif
144 wait_queue_head_t waitq;
145 spinlock_t lock;
146 struct i2c_msg *msg;
147 struct i2c_adapter adapter;
148 bool offload_enabled;
149 /* 5us delay in order to avoid repeated start timing violation */
150 bool errata_delay;
151 struct reset_control *rstc;
152 bool irq_clear_inverted;
153 };
154
155 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
156 .addr = 0x00,
157 .ext_addr = 0x10,
158 .data = 0x04,
159 .control = 0x08,
160 .status = 0x0c,
161 .clock = 0x0c,
162 .soft_reset = 0x1c,
163 };
164
165 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = {
166 .addr = 0x00,
167 .ext_addr = 0x04,
168 .data = 0x08,
169 .control = 0x0c,
170 .status = 0x10,
171 .clock = 0x14,
172 .soft_reset = 0x18,
173 };
174
175 static void
176 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
177 struct i2c_msg *msg)
178 {
179 u32 dir = 0;
180
181 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
182 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
183
184 if (msg->flags & I2C_M_RD)
185 dir = 1;
186
187 if (msg->flags & I2C_M_TEN) {
188 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
189 drv_data->addr2 = (u32)msg->addr & 0xff;
190 } else {
191 drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir;
192 drv_data->addr2 = 0;
193 }
194 }
195
196 static int mv64xxx_i2c_offload_msg(struct mv64xxx_i2c_data *drv_data)
197 {
198 unsigned long data_reg_hi = 0;
199 unsigned long data_reg_lo = 0;
200 unsigned long ctrl_reg;
201 struct i2c_msg *msg = drv_data->msgs;
202
203 if (!drv_data->offload_enabled)
204 return -EOPNOTSUPP;
205
206 /* Only regular transactions can be offloaded */
207 if ((msg->flags & ~(I2C_M_TEN | I2C_M_RD)) != 0)
208 return -EINVAL;
209
210 /* Only 1-8 byte transfers can be offloaded */
211 if (msg->len < 1 || msg->len > 8)
212 return -EINVAL;
213
214 /* Build transaction */
215 ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |
216 (msg->addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT);
217
218 if ((msg->flags & I2C_M_TEN) != 0)
219 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;
220
221 if ((msg->flags & I2C_M_RD) == 0) {
222 u8 local_buf[8] = { 0 };
223
224 memcpy(local_buf, msg->buf, msg->len);
225 data_reg_lo = cpu_to_le32(*((u32 *)local_buf));
226 data_reg_hi = cpu_to_le32(*((u32 *)(local_buf+4)));
227
228 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
229 (msg->len - 1) << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT;
230
231 writel(data_reg_lo,
232 drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
233 writel(data_reg_hi,
234 drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
235
236 } else {
237 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |
238 (msg->len - 1) << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT;
239 }
240
241 /* Execute transaction */
242 writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
243
244 return 0;
245 }
246
247 static void
248 mv64xxx_i2c_update_offload_data(struct mv64xxx_i2c_data *drv_data)
249 {
250 struct i2c_msg *msg = drv_data->msg;
251
252 if (msg->flags & I2C_M_RD) {
253 u32 data_reg_lo = readl(drv_data->reg_base +
254 MV64XXX_I2C_REG_RX_DATA_LO);
255 u32 data_reg_hi = readl(drv_data->reg_base +
256 MV64XXX_I2C_REG_RX_DATA_HI);
257 u8 local_buf[8] = { 0 };
258
259 *((u32 *)local_buf) = le32_to_cpu(data_reg_lo);
260 *((u32 *)(local_buf+4)) = le32_to_cpu(data_reg_hi);
261 memcpy(msg->buf, local_buf, msg->len);
262 }
263
264 }
265 /*
266 *****************************************************************************
267 *
268 * Finite State Machine & Interrupt Routines
269 *
270 *****************************************************************************
271 */
272
273 /* Reset hardware and initialize FSM */
274 static void
275 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
276 {
277 if (drv_data->offload_enabled) {
278 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
279 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING);
280 writel(0, drv_data->reg_base +
281 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
282 writel(0, drv_data->reg_base +
283 MV64XXX_I2C_REG_BRIDGE_INTR_MASK);
284 }
285
286 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
287 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
288 drv_data->reg_base + drv_data->reg_offsets.clock);
289 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
290 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
291 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
292 drv_data->reg_base + drv_data->reg_offsets.control);
293 drv_data->state = MV64XXX_I2C_STATE_IDLE;
294 }
295
296 static void
297 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
298 {
299 /*
300 * If state is idle, then this is likely the remnants of an old
301 * operation that driver has given up on or the user has killed.
302 * If so, issue the stop condition and go to idle.
303 */
304 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
305 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
306 return;
307 }
308
309 /* The status from the ctlr [mostly] tells us what to do next */
310 switch (status) {
311 /* Start condition interrupt */
312 case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
313 case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
314 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
315 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
316 break;
317
318 /* Performing a write */
319 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
320 if (drv_data->msg->flags & I2C_M_TEN) {
321 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
322 drv_data->state =
323 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
324 break;
325 }
326 /* FALLTHRU */
327 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
328 case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
329 if ((drv_data->bytes_left == 0)
330 || (drv_data->aborting
331 && (drv_data->byte_posn != 0))) {
332 if (drv_data->send_stop || drv_data->aborting) {
333 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
334 drv_data->state = MV64XXX_I2C_STATE_IDLE;
335 } else {
336 drv_data->action =
337 MV64XXX_I2C_ACTION_SEND_RESTART;
338 drv_data->state =
339 MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
340 }
341 } else {
342 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
343 drv_data->state =
344 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
345 drv_data->bytes_left--;
346 }
347 break;
348
349 /* Performing a read */
350 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
351 if (drv_data->msg->flags & I2C_M_TEN) {
352 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
353 drv_data->state =
354 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
355 break;
356 }
357 /* FALLTHRU */
358 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
359 if (drv_data->bytes_left == 0) {
360 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
361 drv_data->state = MV64XXX_I2C_STATE_IDLE;
362 break;
363 }
364 /* FALLTHRU */
365 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
366 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
367 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
368 else {
369 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
370 drv_data->bytes_left--;
371 }
372 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
373
374 if ((drv_data->bytes_left == 1) || drv_data->aborting)
375 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
376 break;
377
378 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
379 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
380 drv_data->state = MV64XXX_I2C_STATE_IDLE;
381 break;
382
383 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
384 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
385 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
386 /* Doesn't seem to be a device at other end */
387 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
388 drv_data->state = MV64XXX_I2C_STATE_IDLE;
389 drv_data->rc = -ENXIO;
390 break;
391
392 case MV64XXX_I2C_STATUS_OFFLOAD_OK:
393 if (drv_data->send_stop || drv_data->aborting) {
394 drv_data->action = MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP;
395 drv_data->state = MV64XXX_I2C_STATE_IDLE;
396 } else {
397 drv_data->action = MV64XXX_I2C_ACTION_OFFLOAD_RESTART;
398 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
399 }
400 break;
401
402 default:
403 dev_err(&drv_data->adapter.dev,
404 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
405 "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
406 drv_data->state, status, drv_data->msg->addr,
407 drv_data->msg->flags);
408 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
409 mv64xxx_i2c_hw_init(drv_data);
410 drv_data->rc = -EIO;
411 }
412 }
413
414 static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data)
415 {
416 drv_data->msg = drv_data->msgs;
417 drv_data->byte_posn = 0;
418 drv_data->bytes_left = drv_data->msg->len;
419 drv_data->aborting = 0;
420 drv_data->rc = 0;
421
422 /* Can we offload this msg ? */
423 if (mv64xxx_i2c_offload_msg(drv_data) < 0) {
424 /* No, switch to standard path */
425 mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
426 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
427 drv_data->reg_base + drv_data->reg_offsets.control);
428 }
429 }
430
431 static void
432 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
433 {
434 switch(drv_data->action) {
435 case MV64XXX_I2C_ACTION_OFFLOAD_RESTART:
436 mv64xxx_i2c_update_offload_data(drv_data);
437 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
438 writel(0, drv_data->reg_base +
439 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
440 /* FALLTHRU */
441 case MV64XXX_I2C_ACTION_SEND_RESTART:
442 /* We should only get here if we have further messages */
443 BUG_ON(drv_data->num_msgs == 0);
444
445 drv_data->msgs++;
446 drv_data->num_msgs--;
447 mv64xxx_i2c_send_start(drv_data);
448
449 if (drv_data->errata_delay)
450 udelay(5);
451
452 /*
453 * We're never at the start of the message here, and by this
454 * time it's already too late to do any protocol mangling.
455 * Thankfully, do not advertise support for that feature.
456 */
457 drv_data->send_stop = drv_data->num_msgs == 1;
458 break;
459
460 case MV64XXX_I2C_ACTION_CONTINUE:
461 writel(drv_data->cntl_bits,
462 drv_data->reg_base + drv_data->reg_offsets.control);
463 break;
464
465 case MV64XXX_I2C_ACTION_SEND_ADDR_1:
466 writel(drv_data->addr1,
467 drv_data->reg_base + drv_data->reg_offsets.data);
468 writel(drv_data->cntl_bits,
469 drv_data->reg_base + drv_data->reg_offsets.control);
470 break;
471
472 case MV64XXX_I2C_ACTION_SEND_ADDR_2:
473 writel(drv_data->addr2,
474 drv_data->reg_base + drv_data->reg_offsets.data);
475 writel(drv_data->cntl_bits,
476 drv_data->reg_base + drv_data->reg_offsets.control);
477 break;
478
479 case MV64XXX_I2C_ACTION_SEND_DATA:
480 writel(drv_data->msg->buf[drv_data->byte_posn++],
481 drv_data->reg_base + drv_data->reg_offsets.data);
482 writel(drv_data->cntl_bits,
483 drv_data->reg_base + drv_data->reg_offsets.control);
484 break;
485
486 case MV64XXX_I2C_ACTION_RCV_DATA:
487 drv_data->msg->buf[drv_data->byte_posn++] =
488 readl(drv_data->reg_base + drv_data->reg_offsets.data);
489 writel(drv_data->cntl_bits,
490 drv_data->reg_base + drv_data->reg_offsets.control);
491 break;
492
493 case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
494 drv_data->msg->buf[drv_data->byte_posn++] =
495 readl(drv_data->reg_base + drv_data->reg_offsets.data);
496 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
497 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
498 drv_data->reg_base + drv_data->reg_offsets.control);
499 drv_data->block = 0;
500 if (drv_data->errata_delay)
501 udelay(5);
502
503 wake_up(&drv_data->waitq);
504 break;
505
506 case MV64XXX_I2C_ACTION_INVALID:
507 default:
508 dev_err(&drv_data->adapter.dev,
509 "mv64xxx_i2c_do_action: Invalid action: %d\n",
510 drv_data->action);
511 drv_data->rc = -EIO;
512
513 /* FALLTHRU */
514 case MV64XXX_I2C_ACTION_SEND_STOP:
515 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
516 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
517 drv_data->reg_base + drv_data->reg_offsets.control);
518 drv_data->block = 0;
519 wake_up(&drv_data->waitq);
520 break;
521
522 case MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP:
523 mv64xxx_i2c_update_offload_data(drv_data);
524 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
525 writel(0, drv_data->reg_base +
526 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
527 drv_data->block = 0;
528 wake_up(&drv_data->waitq);
529 break;
530 }
531 }
532
533 static irqreturn_t
534 mv64xxx_i2c_intr(int irq, void *dev_id)
535 {
536 struct mv64xxx_i2c_data *drv_data = dev_id;
537 unsigned long flags;
538 u32 status;
539 irqreturn_t rc = IRQ_NONE;
540
541 spin_lock_irqsave(&drv_data->lock, flags);
542
543 if (drv_data->offload_enabled) {
544 while (readl(drv_data->reg_base +
545 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE)) {
546 int reg_status = readl(drv_data->reg_base +
547 MV64XXX_I2C_REG_BRIDGE_STATUS);
548 if (reg_status & MV64XXX_I2C_BRIDGE_STATUS_ERROR)
549 status = MV64XXX_I2C_STATUS_OFFLOAD_ERROR;
550 else
551 status = MV64XXX_I2C_STATUS_OFFLOAD_OK;
552 mv64xxx_i2c_fsm(drv_data, status);
553 mv64xxx_i2c_do_action(drv_data);
554 rc = IRQ_HANDLED;
555 }
556 }
557 while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
558 MV64XXX_I2C_REG_CONTROL_IFLG) {
559 status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
560 mv64xxx_i2c_fsm(drv_data, status);
561 mv64xxx_i2c_do_action(drv_data);
562
563 if (drv_data->irq_clear_inverted)
564 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG,
565 drv_data->reg_base + drv_data->reg_offsets.control);
566
567 rc = IRQ_HANDLED;
568 }
569 spin_unlock_irqrestore(&drv_data->lock, flags);
570
571 return rc;
572 }
573
574 /*
575 *****************************************************************************
576 *
577 * I2C Msg Execution Routines
578 *
579 *****************************************************************************
580 */
581 static void
582 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
583 {
584 long time_left;
585 unsigned long flags;
586 char abort = 0;
587
588 time_left = wait_event_timeout(drv_data->waitq,
589 !drv_data->block, drv_data->adapter.timeout);
590
591 spin_lock_irqsave(&drv_data->lock, flags);
592 if (!time_left) { /* Timed out */
593 drv_data->rc = -ETIMEDOUT;
594 abort = 1;
595 } else if (time_left < 0) { /* Interrupted/Error */
596 drv_data->rc = time_left; /* errno value */
597 abort = 1;
598 }
599
600 if (abort && drv_data->block) {
601 drv_data->aborting = 1;
602 spin_unlock_irqrestore(&drv_data->lock, flags);
603
604 time_left = wait_event_timeout(drv_data->waitq,
605 !drv_data->block, drv_data->adapter.timeout);
606
607 if ((time_left <= 0) && drv_data->block) {
608 drv_data->state = MV64XXX_I2C_STATE_IDLE;
609 dev_err(&drv_data->adapter.dev,
610 "mv64xxx: I2C bus locked, block: %d, "
611 "time_left: %d\n", drv_data->block,
612 (int)time_left);
613 mv64xxx_i2c_hw_init(drv_data);
614 }
615 } else
616 spin_unlock_irqrestore(&drv_data->lock, flags);
617 }
618
619 static int
620 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
621 int is_last)
622 {
623 unsigned long flags;
624
625 spin_lock_irqsave(&drv_data->lock, flags);
626
627 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
628
629 drv_data->send_stop = is_last;
630 drv_data->block = 1;
631 mv64xxx_i2c_send_start(drv_data);
632 spin_unlock_irqrestore(&drv_data->lock, flags);
633
634 mv64xxx_i2c_wait_for_completion(drv_data);
635 return drv_data->rc;
636 }
637
638 /*
639 *****************************************************************************
640 *
641 * I2C Core Support Routines (Interface to higher level I2C code)
642 *
643 *****************************************************************************
644 */
645 static u32
646 mv64xxx_i2c_functionality(struct i2c_adapter *adap)
647 {
648 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
649 }
650
651 static int
652 mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
653 {
654 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
655 int rc, ret = num;
656
657 BUG_ON(drv_data->msgs != NULL);
658 drv_data->msgs = msgs;
659 drv_data->num_msgs = num;
660
661 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
662 if (rc < 0)
663 ret = rc;
664
665 drv_data->num_msgs = 0;
666 drv_data->msgs = NULL;
667
668 return ret;
669 }
670
671 static const struct i2c_algorithm mv64xxx_i2c_algo = {
672 .master_xfer = mv64xxx_i2c_xfer,
673 .functionality = mv64xxx_i2c_functionality,
674 };
675
676 /*
677 *****************************************************************************
678 *
679 * Driver Interface & Early Init Routines
680 *
681 *****************************************************************************
682 */
683 static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
684 { .compatible = "allwinner,sun4i-a10-i2c", .data = &mv64xxx_i2c_regs_sun4i},
685 { .compatible = "allwinner,sun6i-a31-i2c", .data = &mv64xxx_i2c_regs_sun4i},
686 { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
687 { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
688 { .compatible = "marvell,mv78230-a0-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
689 {}
690 };
691 MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
692
693 #ifdef CONFIG_OF
694 #ifdef CONFIG_HAVE_CLK
695 static int
696 mv64xxx_calc_freq(const int tclk, const int n, const int m)
697 {
698 return tclk / (10 * (m + 1) * (2 << n));
699 }
700
701 static bool
702 mv64xxx_find_baud_factors(const u32 req_freq, const u32 tclk, u32 *best_n,
703 u32 *best_m)
704 {
705 int freq, delta, best_delta = INT_MAX;
706 int m, n;
707
708 for (n = 0; n <= 7; n++)
709 for (m = 0; m <= 15; m++) {
710 freq = mv64xxx_calc_freq(tclk, n, m);
711 delta = req_freq - freq;
712 if (delta >= 0 && delta < best_delta) {
713 *best_m = m;
714 *best_n = n;
715 best_delta = delta;
716 }
717 if (best_delta == 0)
718 return true;
719 }
720 if (best_delta == INT_MAX)
721 return false;
722 return true;
723 }
724 #endif /* CONFIG_HAVE_CLK */
725
726 static int
727 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
728 struct device *dev)
729 {
730 /* CLK is mandatory when using DT to describe the i2c bus. We
731 * need to know tclk in order to calculate bus clock
732 * factors.
733 */
734 #if !defined(CONFIG_HAVE_CLK)
735 /* Have OF but no CLK */
736 return -ENODEV;
737 #else
738 const struct of_device_id *device;
739 struct device_node *np = dev->of_node;
740 u32 bus_freq, tclk;
741 int rc = 0;
742
743 if (IS_ERR(drv_data->clk)) {
744 rc = -ENODEV;
745 goto out;
746 }
747 tclk = clk_get_rate(drv_data->clk);
748
749 if (of_property_read_u32(np, "clock-frequency", &bus_freq))
750 bus_freq = 100000; /* 100kHz by default */
751
752 if (!mv64xxx_find_baud_factors(bus_freq, tclk,
753 &drv_data->freq_n, &drv_data->freq_m)) {
754 rc = -EINVAL;
755 goto out;
756 }
757 drv_data->irq = irq_of_parse_and_map(np, 0);
758
759 drv_data->rstc = devm_reset_control_get_optional(dev, NULL);
760 if (IS_ERR(drv_data->rstc)) {
761 if (PTR_ERR(drv_data->rstc) == -EPROBE_DEFER) {
762 rc = -EPROBE_DEFER;
763 goto out;
764 }
765 } else {
766 reset_control_deassert(drv_data->rstc);
767 }
768
769 /* Its not yet defined how timeouts will be specified in device tree.
770 * So hard code the value to 1 second.
771 */
772 drv_data->adapter.timeout = HZ;
773
774 device = of_match_device(mv64xxx_i2c_of_match_table, dev);
775 if (!device)
776 return -ENODEV;
777
778 memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets));
779
780 /*
781 * For controllers embedded in new SoCs activate the
782 * Transaction Generator support and the errata fix.
783 */
784 if (of_device_is_compatible(np, "marvell,mv78230-i2c")) {
785 drv_data->offload_enabled = true;
786 drv_data->errata_delay = true;
787 }
788
789 if (of_device_is_compatible(np, "marvell,mv78230-a0-i2c")) {
790 drv_data->offload_enabled = false;
791 drv_data->errata_delay = true;
792 }
793
794 if (of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
795 drv_data->irq_clear_inverted = true;
796
797 out:
798 return rc;
799 #endif
800 }
801 #else /* CONFIG_OF */
802 static int
803 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
804 struct device *dev)
805 {
806 return -ENODEV;
807 }
808 #endif /* CONFIG_OF */
809
810 static int
811 mv64xxx_i2c_probe(struct platform_device *pd)
812 {
813 struct mv64xxx_i2c_data *drv_data;
814 struct mv64xxx_i2c_pdata *pdata = dev_get_platdata(&pd->dev);
815 struct resource *r;
816 int rc;
817
818 if ((!pdata && !pd->dev.of_node))
819 return -ENODEV;
820
821 drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
822 GFP_KERNEL);
823 if (!drv_data)
824 return -ENOMEM;
825
826 r = platform_get_resource(pd, IORESOURCE_MEM, 0);
827 drv_data->reg_base = devm_ioremap_resource(&pd->dev, r);
828 if (IS_ERR(drv_data->reg_base))
829 return PTR_ERR(drv_data->reg_base);
830
831 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
832 sizeof(drv_data->adapter.name));
833
834 init_waitqueue_head(&drv_data->waitq);
835 spin_lock_init(&drv_data->lock);
836
837 #if defined(CONFIG_HAVE_CLK)
838 /* Not all platforms have a clk */
839 drv_data->clk = devm_clk_get(&pd->dev, NULL);
840 if (!IS_ERR(drv_data->clk)) {
841 clk_prepare(drv_data->clk);
842 clk_enable(drv_data->clk);
843 }
844 #endif
845 if (pdata) {
846 drv_data->freq_m = pdata->freq_m;
847 drv_data->freq_n = pdata->freq_n;
848 drv_data->irq = platform_get_irq(pd, 0);
849 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
850 drv_data->offload_enabled = false;
851 memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));
852 } else if (pd->dev.of_node) {
853 rc = mv64xxx_of_config(drv_data, &pd->dev);
854 if (rc)
855 goto exit_clk;
856 }
857 if (drv_data->irq < 0) {
858 rc = -ENXIO;
859 goto exit_reset;
860 }
861
862 drv_data->adapter.dev.parent = &pd->dev;
863 drv_data->adapter.algo = &mv64xxx_i2c_algo;
864 drv_data->adapter.owner = THIS_MODULE;
865 drv_data->adapter.class = I2C_CLASS_DEPRECATED;
866 drv_data->adapter.nr = pd->id;
867 drv_data->adapter.dev.of_node = pd->dev.of_node;
868 platform_set_drvdata(pd, drv_data);
869 i2c_set_adapdata(&drv_data->adapter, drv_data);
870
871 mv64xxx_i2c_hw_init(drv_data);
872
873 rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
874 MV64XXX_I2C_CTLR_NAME, drv_data);
875 if (rc) {
876 dev_err(&drv_data->adapter.dev,
877 "mv64xxx: Can't register intr handler irq%d: %d\n",
878 drv_data->irq, rc);
879 goto exit_reset;
880 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
881 dev_err(&drv_data->adapter.dev,
882 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
883 goto exit_free_irq;
884 }
885
886 return 0;
887
888 exit_free_irq:
889 free_irq(drv_data->irq, drv_data);
890 exit_reset:
891 if (!IS_ERR_OR_NULL(drv_data->rstc))
892 reset_control_assert(drv_data->rstc);
893 exit_clk:
894 #if defined(CONFIG_HAVE_CLK)
895 /* Not all platforms have a clk */
896 if (!IS_ERR(drv_data->clk)) {
897 clk_disable(drv_data->clk);
898 clk_unprepare(drv_data->clk);
899 }
900 #endif
901 return rc;
902 }
903
904 static int
905 mv64xxx_i2c_remove(struct platform_device *dev)
906 {
907 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev);
908
909 i2c_del_adapter(&drv_data->adapter);
910 free_irq(drv_data->irq, drv_data);
911 if (!IS_ERR_OR_NULL(drv_data->rstc))
912 reset_control_assert(drv_data->rstc);
913 #if defined(CONFIG_HAVE_CLK)
914 /* Not all platforms have a clk */
915 if (!IS_ERR(drv_data->clk)) {
916 clk_disable(drv_data->clk);
917 clk_unprepare(drv_data->clk);
918 }
919 #endif
920
921 return 0;
922 }
923
924 static struct platform_driver mv64xxx_i2c_driver = {
925 .probe = mv64xxx_i2c_probe,
926 .remove = mv64xxx_i2c_remove,
927 .driver = {
928 .name = MV64XXX_I2C_CTLR_NAME,
929 .of_match_table = mv64xxx_i2c_of_match_table,
930 },
931 };
932
933 module_platform_driver(mv64xxx_i2c_driver);
934
935 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
936 MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
937 MODULE_LICENSE("GPL");
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