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i2c-omap: Close suspected race between omap_i2c_idle() and omap_i2c_isr()
[deliverable/linux.git] / drivers / i2c / busses / i2c-omap.c
1 /*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2004 Texas Instruments.
6 *
7 * Updated to work with multiple I2C interfaces on 24xx by
8 * Tony Lindgren <tony@atomide.com> and Imre Deak <imre.deak@nokia.com>
9 * Copyright (C) 2005 Nokia Corporation
10 *
11 * Cleaned up by Juha Yrjölä <juha.yrjola@nokia.com>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28 #include <linux/module.h>
29 #include <linux/delay.h>
30 #include <linux/i2c.h>
31 #include <linux/err.h>
32 #include <linux/interrupt.h>
33 #include <linux/completion.h>
34 #include <linux/platform_device.h>
35 #include <linux/clk.h>
36
37 #include <asm/io.h>
38
39 /* timeout waiting for the controller to respond */
40 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
41
42 #define OMAP_I2C_REV_REG 0x00
43 #define OMAP_I2C_IE_REG 0x04
44 #define OMAP_I2C_STAT_REG 0x08
45 #define OMAP_I2C_IV_REG 0x0c
46 #define OMAP_I2C_SYSS_REG 0x10
47 #define OMAP_I2C_BUF_REG 0x14
48 #define OMAP_I2C_CNT_REG 0x18
49 #define OMAP_I2C_DATA_REG 0x1c
50 #define OMAP_I2C_SYSC_REG 0x20
51 #define OMAP_I2C_CON_REG 0x24
52 #define OMAP_I2C_OA_REG 0x28
53 #define OMAP_I2C_SA_REG 0x2c
54 #define OMAP_I2C_PSC_REG 0x30
55 #define OMAP_I2C_SCLL_REG 0x34
56 #define OMAP_I2C_SCLH_REG 0x38
57 #define OMAP_I2C_SYSTEST_REG 0x3c
58
59 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
60 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
61 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
62 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
63 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
64 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
65
66 /* I2C Status Register (OMAP_I2C_STAT): */
67 #define OMAP_I2C_STAT_SBD (1 << 15) /* Single byte data */
68 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
69 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
70 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
71 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
72 #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
73 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
74 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
75 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
76 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
77 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
78
79 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
80 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
81 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
82
83 /* I2C Configuration Register (OMAP_I2C_CON): */
84 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
85 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
86 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
87 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
88 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
89 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
90 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
91 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
92 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
93
94 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
95 #ifdef DEBUG
96 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
97 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
98 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
99 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
100 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
101 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
102 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
103 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
104 #endif
105
106 /* I2C System Status register (OMAP_I2C_SYSS): */
107 #define OMAP_I2C_SYSS_RDONE (1 << 0) /* Reset Done */
108
109 /* I2C System Configuration Register (OMAP_I2C_SYSC): */
110 #define OMAP_I2C_SYSC_SRST (1 << 1) /* Soft Reset */
111
112 /* REVISIT: Use platform_data instead of module parameters */
113 /* Fast Mode = 400 kHz, Standard = 100 kHz */
114 static int clock = 100; /* Default: 100 kHz */
115 module_param(clock, int, 0);
116 MODULE_PARM_DESC(clock, "Set I2C clock in kHz: 400=fast mode (default == 100)");
117
118 struct omap_i2c_dev {
119 struct device *dev;
120 void __iomem *base; /* virtual */
121 int irq;
122 struct clk *iclk; /* Interface clock */
123 struct clk *fclk; /* Functional clock */
124 struct completion cmd_complete;
125 struct resource *ioarea;
126 u16 cmd_err;
127 u8 *buf;
128 size_t buf_len;
129 struct i2c_adapter adapter;
130 unsigned rev1:1;
131 unsigned idle:1;
132 u16 iestate; /* Saved interrupt register */
133 };
134
135 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
136 int reg, u16 val)
137 {
138 __raw_writew(val, i2c_dev->base + reg);
139 }
140
141 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
142 {
143 return __raw_readw(i2c_dev->base + reg);
144 }
145
146 static int omap_i2c_get_clocks(struct omap_i2c_dev *dev)
147 {
148 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
149 dev->iclk = clk_get(dev->dev, "i2c_ick");
150 if (IS_ERR(dev->iclk)) {
151 dev->iclk = NULL;
152 return -ENODEV;
153 }
154 }
155
156 dev->fclk = clk_get(dev->dev, "i2c_fck");
157 if (IS_ERR(dev->fclk)) {
158 if (dev->iclk != NULL) {
159 clk_put(dev->iclk);
160 dev->iclk = NULL;
161 }
162 dev->fclk = NULL;
163 return -ENODEV;
164 }
165
166 return 0;
167 }
168
169 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
170 {
171 clk_put(dev->fclk);
172 dev->fclk = NULL;
173 if (dev->iclk != NULL) {
174 clk_put(dev->iclk);
175 dev->iclk = NULL;
176 }
177 }
178
179 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
180 {
181 if (dev->iclk != NULL)
182 clk_enable(dev->iclk);
183 clk_enable(dev->fclk);
184 dev->idle = 0;
185 if (dev->iestate)
186 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
187 }
188
189 static void omap_i2c_idle(struct omap_i2c_dev *dev)
190 {
191 u16 iv;
192
193 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
194 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
195 if (dev->rev1) {
196 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
197 } else {
198 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
199
200 /* Flush posted write before the dev->idle store occurs */
201 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
202 }
203 dev->idle = 1;
204 clk_disable(dev->fclk);
205 if (dev->iclk != NULL)
206 clk_disable(dev->iclk);
207 }
208
209 static int omap_i2c_init(struct omap_i2c_dev *dev)
210 {
211 u16 psc = 0;
212 unsigned long fclk_rate = 12000000;
213 unsigned long timeout;
214
215 if (!dev->rev1) {
216 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
217 /* For some reason we need to set the EN bit before the
218 * reset done bit gets set. */
219 timeout = jiffies + OMAP_I2C_TIMEOUT;
220 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
221 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
222 OMAP_I2C_SYSS_RDONE)) {
223 if (time_after(jiffies, timeout)) {
224 dev_warn(dev->dev, "timeout waiting "
225 "for controller reset\n");
226 return -ETIMEDOUT;
227 }
228 msleep(1);
229 }
230 }
231 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
232
233 if (cpu_class_is_omap1()) {
234 struct clk *armxor_ck;
235
236 armxor_ck = clk_get(NULL, "armxor_ck");
237 if (IS_ERR(armxor_ck))
238 dev_warn(dev->dev, "Could not get armxor_ck\n");
239 else {
240 fclk_rate = clk_get_rate(armxor_ck);
241 clk_put(armxor_ck);
242 }
243 /* TRM for 5912 says the I2C clock must be prescaled to be
244 * between 7 - 12 MHz. The XOR input clock is typically
245 * 12, 13 or 19.2 MHz. So we should have code that produces:
246 *
247 * XOR MHz Divider Prescaler
248 * 12 1 0
249 * 13 2 1
250 * 19.2 2 1
251 */
252 if (fclk_rate > 12000000)
253 psc = fclk_rate / 12000000;
254 }
255
256 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
257 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
258
259 /* Program desired operating rate */
260 fclk_rate /= (psc + 1) * 1000;
261 if (psc > 2)
262 psc = 2;
263
264 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG,
265 fclk_rate / (clock * 2) - 7 + psc);
266 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG,
267 fclk_rate / (clock * 2) - 7 + psc);
268
269 /* Take the I2C module out of reset: */
270 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
271
272 /* Enable interrupts */
273 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
274 (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
275 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
276 OMAP_I2C_IE_AL));
277 return 0;
278 }
279
280 /*
281 * Waiting on Bus Busy
282 */
283 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
284 {
285 unsigned long timeout;
286
287 timeout = jiffies + OMAP_I2C_TIMEOUT;
288 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
289 if (time_after(jiffies, timeout)) {
290 dev_warn(dev->dev, "timeout waiting for bus ready\n");
291 return -ETIMEDOUT;
292 }
293 msleep(1);
294 }
295
296 return 0;
297 }
298
299 /*
300 * Low level master read/write transaction.
301 */
302 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
303 struct i2c_msg *msg, int stop)
304 {
305 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
306 int r;
307 u16 w;
308
309 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
310 msg->addr, msg->len, msg->flags, stop);
311
312 if (msg->len == 0)
313 return -EINVAL;
314
315 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
316
317 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
318 dev->buf = msg->buf;
319 dev->buf_len = msg->len;
320
321 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
322
323 init_completion(&dev->cmd_complete);
324 dev->cmd_err = 0;
325
326 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
327 if (msg->flags & I2C_M_TEN)
328 w |= OMAP_I2C_CON_XA;
329 if (!(msg->flags & I2C_M_RD))
330 w |= OMAP_I2C_CON_TRX;
331 if (stop)
332 w |= OMAP_I2C_CON_STP;
333 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
334
335 /*
336 * REVISIT: We should abort the transfer on signals, but the bus goes
337 * into arbitration and we're currently unable to recover from it.
338 */
339 r = wait_for_completion_timeout(&dev->cmd_complete,
340 OMAP_I2C_TIMEOUT);
341 dev->buf_len = 0;
342 if (r < 0)
343 return r;
344 if (r == 0) {
345 dev_err(dev->dev, "controller timed out\n");
346 omap_i2c_init(dev);
347 return -ETIMEDOUT;
348 }
349
350 if (likely(!dev->cmd_err))
351 return 0;
352
353 /* We have an error */
354 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
355 OMAP_I2C_STAT_XUDF)) {
356 omap_i2c_init(dev);
357 return -EIO;
358 }
359
360 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
361 if (msg->flags & I2C_M_IGNORE_NAK)
362 return 0;
363 if (stop) {
364 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
365 w |= OMAP_I2C_CON_STP;
366 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
367 }
368 return -EREMOTEIO;
369 }
370 return -EIO;
371 }
372
373
374 /*
375 * Prepare controller for a transaction and call omap_i2c_xfer_msg
376 * to do the work during IRQ processing.
377 */
378 static int
379 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
380 {
381 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
382 int i;
383 int r;
384
385 omap_i2c_unidle(dev);
386
387 if ((r = omap_i2c_wait_for_bb(dev)) < 0)
388 goto out;
389
390 for (i = 0; i < num; i++) {
391 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
392 if (r != 0)
393 break;
394 }
395
396 if (r == 0)
397 r = num;
398 out:
399 omap_i2c_idle(dev);
400 return r;
401 }
402
403 static u32
404 omap_i2c_func(struct i2c_adapter *adap)
405 {
406 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
407 }
408
409 static inline void
410 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
411 {
412 dev->cmd_err |= err;
413 complete(&dev->cmd_complete);
414 }
415
416 static inline void
417 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
418 {
419 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
420 }
421
422 static irqreturn_t
423 omap_i2c_rev1_isr(int this_irq, void *dev_id)
424 {
425 struct omap_i2c_dev *dev = dev_id;
426 u16 iv, w;
427
428 if (dev->idle)
429 return IRQ_NONE;
430
431 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
432 switch (iv) {
433 case 0x00: /* None */
434 break;
435 case 0x01: /* Arbitration lost */
436 dev_err(dev->dev, "Arbitration lost\n");
437 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
438 break;
439 case 0x02: /* No acknowledgement */
440 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
441 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
442 break;
443 case 0x03: /* Register access ready */
444 omap_i2c_complete_cmd(dev, 0);
445 break;
446 case 0x04: /* Receive data ready */
447 if (dev->buf_len) {
448 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
449 *dev->buf++ = w;
450 dev->buf_len--;
451 if (dev->buf_len) {
452 *dev->buf++ = w >> 8;
453 dev->buf_len--;
454 }
455 } else
456 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
457 break;
458 case 0x05: /* Transmit data ready */
459 if (dev->buf_len) {
460 w = *dev->buf++;
461 dev->buf_len--;
462 if (dev->buf_len) {
463 w |= *dev->buf++ << 8;
464 dev->buf_len--;
465 }
466 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
467 } else
468 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
469 break;
470 default:
471 return IRQ_NONE;
472 }
473
474 return IRQ_HANDLED;
475 }
476
477 static irqreturn_t
478 omap_i2c_isr(int this_irq, void *dev_id)
479 {
480 struct omap_i2c_dev *dev = dev_id;
481 u16 bits;
482 u16 stat, w;
483 int count = 0;
484
485 if (dev->idle)
486 return IRQ_NONE;
487
488 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
489 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
490 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
491 if (count++ == 100) {
492 dev_warn(dev->dev, "Too much work in one IRQ\n");
493 break;
494 }
495
496 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
497
498 if (stat & OMAP_I2C_STAT_ARDY) {
499 omap_i2c_complete_cmd(dev, 0);
500 continue;
501 }
502 if (stat & OMAP_I2C_STAT_RRDY) {
503 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
504 if (dev->buf_len) {
505 *dev->buf++ = w;
506 dev->buf_len--;
507 if (dev->buf_len) {
508 *dev->buf++ = w >> 8;
509 dev->buf_len--;
510 }
511 } else
512 dev_err(dev->dev, "RRDY IRQ while no data "
513 "requested\n");
514 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
515 continue;
516 }
517 if (stat & OMAP_I2C_STAT_XRDY) {
518 w = 0;
519 if (dev->buf_len) {
520 w = *dev->buf++;
521 dev->buf_len--;
522 if (dev->buf_len) {
523 w |= *dev->buf++ << 8;
524 dev->buf_len--;
525 }
526 } else
527 dev_err(dev->dev, "XRDY IRQ while no "
528 "data to send\n");
529 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
530 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
531 continue;
532 }
533 if (stat & OMAP_I2C_STAT_ROVR) {
534 dev_err(dev->dev, "Receive overrun\n");
535 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
536 }
537 if (stat & OMAP_I2C_STAT_XUDF) {
538 dev_err(dev->dev, "Transmit overflow\n");
539 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
540 }
541 if (stat & OMAP_I2C_STAT_NACK) {
542 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
543 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
544 OMAP_I2C_CON_STP);
545 }
546 if (stat & OMAP_I2C_STAT_AL) {
547 dev_err(dev->dev, "Arbitration lost\n");
548 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
549 }
550 }
551
552 return count ? IRQ_HANDLED : IRQ_NONE;
553 }
554
555 static const struct i2c_algorithm omap_i2c_algo = {
556 .master_xfer = omap_i2c_xfer,
557 .functionality = omap_i2c_func,
558 };
559
560 static int
561 omap_i2c_probe(struct platform_device *pdev)
562 {
563 struct omap_i2c_dev *dev;
564 struct i2c_adapter *adap;
565 struct resource *mem, *irq, *ioarea;
566 int r;
567
568 /* NOTE: driver uses the static register mapping */
569 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
570 if (!mem) {
571 dev_err(&pdev->dev, "no mem resource?\n");
572 return -ENODEV;
573 }
574 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
575 if (!irq) {
576 dev_err(&pdev->dev, "no irq resource?\n");
577 return -ENODEV;
578 }
579
580 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
581 pdev->name);
582 if (!ioarea) {
583 dev_err(&pdev->dev, "I2C region already claimed\n");
584 return -EBUSY;
585 }
586
587 if (clock > 200)
588 clock = 400; /* Fast mode */
589 else
590 clock = 100; /* Standard mode */
591
592 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
593 if (!dev) {
594 r = -ENOMEM;
595 goto err_release_region;
596 }
597
598 dev->dev = &pdev->dev;
599 dev->irq = irq->start;
600 dev->base = ioremap(mem->start, mem->end - mem->start + 1);
601 if (!dev->base) {
602 r = -ENOMEM;
603 goto err_free_mem;
604 }
605
606 platform_set_drvdata(pdev, dev);
607
608 if ((r = omap_i2c_get_clocks(dev)) != 0)
609 goto err_iounmap;
610
611 omap_i2c_unidle(dev);
612
613 if (cpu_is_omap15xx())
614 dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
615
616 /* reset ASAP, clearing any IRQs */
617 omap_i2c_init(dev);
618
619 r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
620 0, pdev->name, dev);
621
622 if (r) {
623 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
624 goto err_unuse_clocks;
625 }
626 r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
627 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
628 pdev->id, r >> 4, r & 0xf, clock);
629
630 adap = &dev->adapter;
631 i2c_set_adapdata(adap, dev);
632 adap->owner = THIS_MODULE;
633 adap->class = I2C_CLASS_HWMON;
634 strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
635 adap->algo = &omap_i2c_algo;
636 adap->dev.parent = &pdev->dev;
637
638 /* i2c device drivers may be active on return from add_adapter() */
639 adap->nr = pdev->id;
640 r = i2c_add_numbered_adapter(adap);
641 if (r) {
642 dev_err(dev->dev, "failure adding adapter\n");
643 goto err_free_irq;
644 }
645
646 omap_i2c_idle(dev);
647
648 return 0;
649
650 err_free_irq:
651 free_irq(dev->irq, dev);
652 err_unuse_clocks:
653 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
654 omap_i2c_idle(dev);
655 omap_i2c_put_clocks(dev);
656 err_iounmap:
657 iounmap(dev->base);
658 err_free_mem:
659 platform_set_drvdata(pdev, NULL);
660 kfree(dev);
661 err_release_region:
662 release_mem_region(mem->start, (mem->end - mem->start) + 1);
663
664 return r;
665 }
666
667 static int
668 omap_i2c_remove(struct platform_device *pdev)
669 {
670 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
671 struct resource *mem;
672
673 platform_set_drvdata(pdev, NULL);
674
675 free_irq(dev->irq, dev);
676 i2c_del_adapter(&dev->adapter);
677 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
678 omap_i2c_put_clocks(dev);
679 iounmap(dev->base);
680 kfree(dev);
681 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
682 release_mem_region(mem->start, (mem->end - mem->start) + 1);
683 return 0;
684 }
685
686 static struct platform_driver omap_i2c_driver = {
687 .probe = omap_i2c_probe,
688 .remove = omap_i2c_remove,
689 .driver = {
690 .name = "i2c_omap",
691 .owner = THIS_MODULE,
692 },
693 };
694
695 /* I2C may be needed to bring up other drivers */
696 static int __init
697 omap_i2c_init_driver(void)
698 {
699 return platform_driver_register(&omap_i2c_driver);
700 }
701 subsys_initcall(omap_i2c_init_driver);
702
703 static void __exit omap_i2c_exit_driver(void)
704 {
705 platform_driver_unregister(&omap_i2c_driver);
706 }
707 module_exit(omap_i2c_exit_driver);
708
709 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
710 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
711 MODULE_LICENSE("GPL");
712 MODULE_ALIAS("platform:i2c_omap");
Linux kernel - Deliverables
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