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i2c-s3c2410: s3c24xx_i2c_init: don't clobber IICLC value
[deliverable/linux.git] / drivers / i2c / busses / i2c-omap.c
1 /*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
7 *
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/i2c.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/completion.h>
37 #include <linux/platform_device.h>
38 #include <linux/clk.h>
39 #include <linux/io.h>
40
41 /* I2C controller revisions */
42 #define OMAP_I2C_REV_2 0x20
43
44 /* I2C controller revisions present on specific hardware */
45 #define OMAP_I2C_REV_ON_2430 0x36
46 #define OMAP_I2C_REV_ON_3430 0x3C
47
48 /* timeout waiting for the controller to respond */
49 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
50
51 #define OMAP_I2C_REV_REG 0x00
52 #define OMAP_I2C_IE_REG 0x04
53 #define OMAP_I2C_STAT_REG 0x08
54 #define OMAP_I2C_IV_REG 0x0c
55 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
56 #define OMAP_I2C_WE_REG 0x0c
57 #define OMAP_I2C_SYSS_REG 0x10
58 #define OMAP_I2C_BUF_REG 0x14
59 #define OMAP_I2C_CNT_REG 0x18
60 #define OMAP_I2C_DATA_REG 0x1c
61 #define OMAP_I2C_SYSC_REG 0x20
62 #define OMAP_I2C_CON_REG 0x24
63 #define OMAP_I2C_OA_REG 0x28
64 #define OMAP_I2C_SA_REG 0x2c
65 #define OMAP_I2C_PSC_REG 0x30
66 #define OMAP_I2C_SCLL_REG 0x34
67 #define OMAP_I2C_SCLH_REG 0x38
68 #define OMAP_I2C_SYSTEST_REG 0x3c
69 #define OMAP_I2C_BUFSTAT_REG 0x40
70
71 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
72 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
73 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
74 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
75 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
76 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
77 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
78 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
79
80 /* I2C Status Register (OMAP_I2C_STAT): */
81 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
82 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
83 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
84 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
85 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
86 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
87 #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
88 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
89 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
90 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
91 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
92 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
93
94 /* I2C WE wakeup enable register */
95 #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
96 #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
97 #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
98 #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
99 #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
100 #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
101 #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
102 #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
103 #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
104 #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
105
106 #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
107 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
108 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
109 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
110 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
111
112 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
113 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
114 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
115 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
116 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
117
118 /* I2C Configuration Register (OMAP_I2C_CON): */
119 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
120 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
121 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
122 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
123 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
124 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
125 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
126 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
127 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
128 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
129
130 /* I2C SCL time value when Master */
131 #define OMAP_I2C_SCLL_HSSCLL 8
132 #define OMAP_I2C_SCLH_HSSCLH 8
133
134 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
135 #ifdef DEBUG
136 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
137 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
138 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
139 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
140 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
141 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
142 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
143 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
144 #endif
145
146 /* OCP_SYSSTATUS bit definitions */
147 #define SYSS_RESETDONE_MASK (1 << 0)
148
149 /* OCP_SYSCONFIG bit definitions */
150 #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
151 #define SYSC_SIDLEMODE_MASK (0x3 << 3)
152 #define SYSC_ENAWAKEUP_MASK (1 << 2)
153 #define SYSC_SOFTRESET_MASK (1 << 1)
154 #define SYSC_AUTOIDLE_MASK (1 << 0)
155
156 #define SYSC_IDLEMODE_SMART 0x2
157 #define SYSC_CLOCKACTIVITY_FCLK 0x2
158
159
160 struct omap_i2c_dev {
161 struct device *dev;
162 void __iomem *base; /* virtual */
163 int irq;
164 struct clk *iclk; /* Interface clock */
165 struct clk *fclk; /* Functional clock */
166 struct completion cmd_complete;
167 struct resource *ioarea;
168 u32 speed; /* Speed of bus in Khz */
169 u16 cmd_err;
170 u8 *buf;
171 size_t buf_len;
172 struct i2c_adapter adapter;
173 u8 fifo_size; /* use as flag and value
174 * fifo_size==0 implies no fifo
175 * if set, should be trsh+1
176 */
177 u8 rev;
178 unsigned b_hw:1; /* bad h/w fixes */
179 unsigned idle:1;
180 u16 iestate; /* Saved interrupt register */
181 };
182
183 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
184 int reg, u16 val)
185 {
186 __raw_writew(val, i2c_dev->base + reg);
187 }
188
189 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
190 {
191 return __raw_readw(i2c_dev->base + reg);
192 }
193
194 static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
195 {
196 int ret;
197
198 dev->iclk = clk_get(dev->dev, "ick");
199 if (IS_ERR(dev->iclk)) {
200 ret = PTR_ERR(dev->iclk);
201 dev->iclk = NULL;
202 return ret;
203 }
204
205 dev->fclk = clk_get(dev->dev, "fck");
206 if (IS_ERR(dev->fclk)) {
207 ret = PTR_ERR(dev->fclk);
208 if (dev->iclk != NULL) {
209 clk_put(dev->iclk);
210 dev->iclk = NULL;
211 }
212 dev->fclk = NULL;
213 return ret;
214 }
215
216 return 0;
217 }
218
219 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
220 {
221 clk_put(dev->fclk);
222 dev->fclk = NULL;
223 clk_put(dev->iclk);
224 dev->iclk = NULL;
225 }
226
227 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
228 {
229 WARN_ON(!dev->idle);
230
231 clk_enable(dev->iclk);
232 clk_enable(dev->fclk);
233 dev->idle = 0;
234 if (dev->iestate)
235 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
236 }
237
238 static void omap_i2c_idle(struct omap_i2c_dev *dev)
239 {
240 u16 iv;
241
242 WARN_ON(dev->idle);
243
244 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
245 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
246 if (dev->rev < OMAP_I2C_REV_2) {
247 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
248 } else {
249 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
250
251 /* Flush posted write before the dev->idle store occurs */
252 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
253 }
254 dev->idle = 1;
255 clk_disable(dev->fclk);
256 clk_disable(dev->iclk);
257 }
258
259 static int omap_i2c_init(struct omap_i2c_dev *dev)
260 {
261 u16 psc = 0, scll = 0, sclh = 0;
262 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
263 unsigned long fclk_rate = 12000000;
264 unsigned long timeout;
265 unsigned long internal_clk = 0;
266
267 if (dev->rev >= OMAP_I2C_REV_2) {
268 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
269 /* For some reason we need to set the EN bit before the
270 * reset done bit gets set. */
271 timeout = jiffies + OMAP_I2C_TIMEOUT;
272 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
273 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
274 SYSS_RESETDONE_MASK)) {
275 if (time_after(jiffies, timeout)) {
276 dev_warn(dev->dev, "timeout waiting "
277 "for controller reset\n");
278 return -ETIMEDOUT;
279 }
280 msleep(1);
281 }
282
283 /* SYSC register is cleared by the reset; rewrite it */
284 if (dev->rev == OMAP_I2C_REV_ON_2430) {
285
286 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
287 SYSC_AUTOIDLE_MASK);
288
289 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
290 u32 v;
291
292 v = SYSC_AUTOIDLE_MASK;
293 v |= SYSC_ENAWAKEUP_MASK;
294 v |= (SYSC_IDLEMODE_SMART <<
295 __ffs(SYSC_SIDLEMODE_MASK));
296 v |= (SYSC_CLOCKACTIVITY_FCLK <<
297 __ffs(SYSC_CLOCKACTIVITY_MASK));
298
299 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, v);
300 /*
301 * Enabling all wakup sources to stop I2C freezing on
302 * WFI instruction.
303 * REVISIT: Some wkup sources might not be needed.
304 */
305 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
306 OMAP_I2C_WE_ALL);
307
308 }
309 }
310 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
311
312 if (cpu_class_is_omap1()) {
313 /*
314 * The I2C functional clock is the armxor_ck, so there's
315 * no need to get "armxor_ck" separately. Now, if OMAP2420
316 * always returns 12MHz for the functional clock, we can
317 * do this bit unconditionally.
318 */
319 fclk_rate = clk_get_rate(dev->fclk);
320
321 /* TRM for 5912 says the I2C clock must be prescaled to be
322 * between 7 - 12 MHz. The XOR input clock is typically
323 * 12, 13 or 19.2 MHz. So we should have code that produces:
324 *
325 * XOR MHz Divider Prescaler
326 * 12 1 0
327 * 13 2 1
328 * 19.2 2 1
329 */
330 if (fclk_rate > 12000000)
331 psc = fclk_rate / 12000000;
332 }
333
334 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
335
336 /*
337 * HSI2C controller internal clk rate should be 19.2 Mhz for
338 * HS and for all modes on 2430. On 34xx we can use lower rate
339 * to get longer filter period for better noise suppression.
340 * The filter is iclk (fclk for HS) period.
341 */
342 if (dev->speed > 400 || cpu_is_omap2430())
343 internal_clk = 19200;
344 else if (dev->speed > 100)
345 internal_clk = 9600;
346 else
347 internal_clk = 4000;
348 fclk_rate = clk_get_rate(dev->fclk) / 1000;
349
350 /* Compute prescaler divisor */
351 psc = fclk_rate / internal_clk;
352 psc = psc - 1;
353
354 /* If configured for High Speed */
355 if (dev->speed > 400) {
356 unsigned long scl;
357
358 /* For first phase of HS mode */
359 scl = internal_clk / 400;
360 fsscll = scl - (scl / 3) - 7;
361 fssclh = (scl / 3) - 5;
362
363 /* For second phase of HS mode */
364 scl = fclk_rate / dev->speed;
365 hsscll = scl - (scl / 3) - 7;
366 hssclh = (scl / 3) - 5;
367 } else if (dev->speed > 100) {
368 unsigned long scl;
369
370 /* Fast mode */
371 scl = internal_clk / dev->speed;
372 fsscll = scl - (scl / 3) - 7;
373 fssclh = (scl / 3) - 5;
374 } else {
375 /* Standard mode */
376 fsscll = internal_clk / (dev->speed * 2) - 7;
377 fssclh = internal_clk / (dev->speed * 2) - 5;
378 }
379 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
380 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
381 } else {
382 /* Program desired operating rate */
383 fclk_rate /= (psc + 1) * 1000;
384 if (psc > 2)
385 psc = 2;
386 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
387 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
388 }
389
390 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
391 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
392
393 /* SCL low and high time values */
394 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
395 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
396
397 if (dev->fifo_size)
398 /* Note: setup required fifo size - 1 */
399 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
400 (dev->fifo_size - 1) << 8 | /* RTRSH */
401 OMAP_I2C_BUF_RXFIF_CLR |
402 (dev->fifo_size - 1) | /* XTRSH */
403 OMAP_I2C_BUF_TXFIF_CLR);
404
405 /* Take the I2C module out of reset: */
406 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
407
408 /* Enable interrupts */
409 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
410 (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
411 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
412 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
413 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
414 return 0;
415 }
416
417 /*
418 * Waiting on Bus Busy
419 */
420 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
421 {
422 unsigned long timeout;
423
424 timeout = jiffies + OMAP_I2C_TIMEOUT;
425 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
426 if (time_after(jiffies, timeout)) {
427 dev_warn(dev->dev, "timeout waiting for bus ready\n");
428 return -ETIMEDOUT;
429 }
430 msleep(1);
431 }
432
433 return 0;
434 }
435
436 /*
437 * Low level master read/write transaction.
438 */
439 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
440 struct i2c_msg *msg, int stop)
441 {
442 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
443 int r;
444 u16 w;
445
446 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
447 msg->addr, msg->len, msg->flags, stop);
448
449 if (msg->len == 0)
450 return -EINVAL;
451
452 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
453
454 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
455 dev->buf = msg->buf;
456 dev->buf_len = msg->len;
457
458 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
459
460 /* Clear the FIFO Buffers */
461 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
462 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
463 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
464
465 init_completion(&dev->cmd_complete);
466 dev->cmd_err = 0;
467
468 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
469
470 /* High speed configuration */
471 if (dev->speed > 400)
472 w |= OMAP_I2C_CON_OPMODE_HS;
473
474 if (msg->flags & I2C_M_TEN)
475 w |= OMAP_I2C_CON_XA;
476 if (!(msg->flags & I2C_M_RD))
477 w |= OMAP_I2C_CON_TRX;
478
479 if (!dev->b_hw && stop)
480 w |= OMAP_I2C_CON_STP;
481
482 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
483
484 /*
485 * Don't write stt and stp together on some hardware.
486 */
487 if (dev->b_hw && stop) {
488 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
489 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
490 while (con & OMAP_I2C_CON_STT) {
491 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
492
493 /* Let the user know if i2c is in a bad state */
494 if (time_after(jiffies, delay)) {
495 dev_err(dev->dev, "controller timed out "
496 "waiting for start condition to finish\n");
497 return -ETIMEDOUT;
498 }
499 cpu_relax();
500 }
501
502 w |= OMAP_I2C_CON_STP;
503 w &= ~OMAP_I2C_CON_STT;
504 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
505 }
506
507 /*
508 * REVISIT: We should abort the transfer on signals, but the bus goes
509 * into arbitration and we're currently unable to recover from it.
510 */
511 r = wait_for_completion_timeout(&dev->cmd_complete,
512 OMAP_I2C_TIMEOUT);
513 dev->buf_len = 0;
514 if (r < 0)
515 return r;
516 if (r == 0) {
517 dev_err(dev->dev, "controller timed out\n");
518 omap_i2c_init(dev);
519 return -ETIMEDOUT;
520 }
521
522 if (likely(!dev->cmd_err))
523 return 0;
524
525 /* We have an error */
526 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
527 OMAP_I2C_STAT_XUDF)) {
528 omap_i2c_init(dev);
529 return -EIO;
530 }
531
532 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
533 if (msg->flags & I2C_M_IGNORE_NAK)
534 return 0;
535 if (stop) {
536 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
537 w |= OMAP_I2C_CON_STP;
538 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
539 }
540 return -EREMOTEIO;
541 }
542 return -EIO;
543 }
544
545
546 /*
547 * Prepare controller for a transaction and call omap_i2c_xfer_msg
548 * to do the work during IRQ processing.
549 */
550 static int
551 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
552 {
553 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
554 int i;
555 int r;
556
557 omap_i2c_unidle(dev);
558
559 r = omap_i2c_wait_for_bb(dev);
560 if (r < 0)
561 goto out;
562
563 for (i = 0; i < num; i++) {
564 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
565 if (r != 0)
566 break;
567 }
568
569 if (r == 0)
570 r = num;
571 out:
572 omap_i2c_idle(dev);
573 return r;
574 }
575
576 static u32
577 omap_i2c_func(struct i2c_adapter *adap)
578 {
579 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
580 }
581
582 static inline void
583 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
584 {
585 dev->cmd_err |= err;
586 complete(&dev->cmd_complete);
587 }
588
589 static inline void
590 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
591 {
592 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
593 }
594
595 /* rev1 devices are apparently only on some 15xx */
596 #ifdef CONFIG_ARCH_OMAP15XX
597
598 static irqreturn_t
599 omap_i2c_rev1_isr(int this_irq, void *dev_id)
600 {
601 struct omap_i2c_dev *dev = dev_id;
602 u16 iv, w;
603
604 if (dev->idle)
605 return IRQ_NONE;
606
607 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
608 switch (iv) {
609 case 0x00: /* None */
610 break;
611 case 0x01: /* Arbitration lost */
612 dev_err(dev->dev, "Arbitration lost\n");
613 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
614 break;
615 case 0x02: /* No acknowledgement */
616 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
617 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
618 break;
619 case 0x03: /* Register access ready */
620 omap_i2c_complete_cmd(dev, 0);
621 break;
622 case 0x04: /* Receive data ready */
623 if (dev->buf_len) {
624 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
625 *dev->buf++ = w;
626 dev->buf_len--;
627 if (dev->buf_len) {
628 *dev->buf++ = w >> 8;
629 dev->buf_len--;
630 }
631 } else
632 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
633 break;
634 case 0x05: /* Transmit data ready */
635 if (dev->buf_len) {
636 w = *dev->buf++;
637 dev->buf_len--;
638 if (dev->buf_len) {
639 w |= *dev->buf++ << 8;
640 dev->buf_len--;
641 }
642 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
643 } else
644 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
645 break;
646 default:
647 return IRQ_NONE;
648 }
649
650 return IRQ_HANDLED;
651 }
652 #else
653 #define omap_i2c_rev1_isr NULL
654 #endif
655
656 static irqreturn_t
657 omap_i2c_isr(int this_irq, void *dev_id)
658 {
659 struct omap_i2c_dev *dev = dev_id;
660 u16 bits;
661 u16 stat, w;
662 int err, count = 0;
663
664 if (dev->idle)
665 return IRQ_NONE;
666
667 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
668 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
669 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
670 if (count++ == 100) {
671 dev_warn(dev->dev, "Too much work in one IRQ\n");
672 break;
673 }
674
675 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
676
677 err = 0;
678 if (stat & OMAP_I2C_STAT_NACK) {
679 err |= OMAP_I2C_STAT_NACK;
680 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
681 OMAP_I2C_CON_STP);
682 }
683 if (stat & OMAP_I2C_STAT_AL) {
684 dev_err(dev->dev, "Arbitration lost\n");
685 err |= OMAP_I2C_STAT_AL;
686 }
687 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
688 OMAP_I2C_STAT_AL))
689 omap_i2c_complete_cmd(dev, err);
690 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
691 u8 num_bytes = 1;
692 if (dev->fifo_size) {
693 if (stat & OMAP_I2C_STAT_RRDY)
694 num_bytes = dev->fifo_size;
695 else
696 num_bytes = omap_i2c_read_reg(dev,
697 OMAP_I2C_BUFSTAT_REG);
698 }
699 while (num_bytes) {
700 num_bytes--;
701 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
702 if (dev->buf_len) {
703 *dev->buf++ = w;
704 dev->buf_len--;
705 /* Data reg from 2430 is 8 bit wide */
706 if (!cpu_is_omap2430() &&
707 !cpu_is_omap34xx()) {
708 if (dev->buf_len) {
709 *dev->buf++ = w >> 8;
710 dev->buf_len--;
711 }
712 }
713 } else {
714 if (stat & OMAP_I2C_STAT_RRDY)
715 dev_err(dev->dev,
716 "RRDY IRQ while no data"
717 " requested\n");
718 if (stat & OMAP_I2C_STAT_RDR)
719 dev_err(dev->dev,
720 "RDR IRQ while no data"
721 " requested\n");
722 break;
723 }
724 }
725 omap_i2c_ack_stat(dev,
726 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
727 continue;
728 }
729 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
730 u8 num_bytes = 1;
731 if (dev->fifo_size) {
732 if (stat & OMAP_I2C_STAT_XRDY)
733 num_bytes = dev->fifo_size;
734 else
735 num_bytes = omap_i2c_read_reg(dev,
736 OMAP_I2C_BUFSTAT_REG);
737 }
738 while (num_bytes) {
739 num_bytes--;
740 w = 0;
741 if (dev->buf_len) {
742 w = *dev->buf++;
743 dev->buf_len--;
744 /* Data reg from 2430 is 8 bit wide */
745 if (!cpu_is_omap2430() &&
746 !cpu_is_omap34xx()) {
747 if (dev->buf_len) {
748 w |= *dev->buf++ << 8;
749 dev->buf_len--;
750 }
751 }
752 } else {
753 if (stat & OMAP_I2C_STAT_XRDY)
754 dev_err(dev->dev,
755 "XRDY IRQ while no "
756 "data to send\n");
757 if (stat & OMAP_I2C_STAT_XDR)
758 dev_err(dev->dev,
759 "XDR IRQ while no "
760 "data to send\n");
761 break;
762 }
763 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
764 }
765 omap_i2c_ack_stat(dev,
766 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
767 continue;
768 }
769 if (stat & OMAP_I2C_STAT_ROVR) {
770 dev_err(dev->dev, "Receive overrun\n");
771 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
772 }
773 if (stat & OMAP_I2C_STAT_XUDF) {
774 dev_err(dev->dev, "Transmit underflow\n");
775 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
776 }
777 }
778
779 return count ? IRQ_HANDLED : IRQ_NONE;
780 }
781
782 static const struct i2c_algorithm omap_i2c_algo = {
783 .master_xfer = omap_i2c_xfer,
784 .functionality = omap_i2c_func,
785 };
786
787 static int __init
788 omap_i2c_probe(struct platform_device *pdev)
789 {
790 struct omap_i2c_dev *dev;
791 struct i2c_adapter *adap;
792 struct resource *mem, *irq, *ioarea;
793 irq_handler_t isr;
794 int r;
795 u32 speed = 0;
796
797 /* NOTE: driver uses the static register mapping */
798 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
799 if (!mem) {
800 dev_err(&pdev->dev, "no mem resource?\n");
801 return -ENODEV;
802 }
803 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
804 if (!irq) {
805 dev_err(&pdev->dev, "no irq resource?\n");
806 return -ENODEV;
807 }
808
809 ioarea = request_mem_region(mem->start, resource_size(mem),
810 pdev->name);
811 if (!ioarea) {
812 dev_err(&pdev->dev, "I2C region already claimed\n");
813 return -EBUSY;
814 }
815
816 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
817 if (!dev) {
818 r = -ENOMEM;
819 goto err_release_region;
820 }
821
822 if (pdev->dev.platform_data != NULL)
823 speed = *(u32 *)pdev->dev.platform_data;
824 else
825 speed = 100; /* Defualt speed */
826
827 dev->speed = speed;
828 dev->idle = 1;
829 dev->dev = &pdev->dev;
830 dev->irq = irq->start;
831 dev->base = ioremap(mem->start, resource_size(mem));
832 if (!dev->base) {
833 r = -ENOMEM;
834 goto err_free_mem;
835 }
836
837 platform_set_drvdata(pdev, dev);
838
839 if ((r = omap_i2c_get_clocks(dev)) != 0)
840 goto err_iounmap;
841
842 omap_i2c_unidle(dev);
843
844 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
845
846 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
847 u16 s;
848
849 /* Set up the fifo size - Get total size */
850 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
851 dev->fifo_size = 0x8 << s;
852
853 /*
854 * Set up notification threshold as half the total available
855 * size. This is to ensure that we can handle the status on int
856 * call back latencies.
857 */
858 dev->fifo_size = (dev->fifo_size / 2);
859 dev->b_hw = 1; /* Enable hardware fixes */
860 }
861
862 /* reset ASAP, clearing any IRQs */
863 omap_i2c_init(dev);
864
865 isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
866 r = request_irq(dev->irq, isr, 0, pdev->name, dev);
867
868 if (r) {
869 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
870 goto err_unuse_clocks;
871 }
872
873 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
874 pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
875
876 omap_i2c_idle(dev);
877
878 adap = &dev->adapter;
879 i2c_set_adapdata(adap, dev);
880 adap->owner = THIS_MODULE;
881 adap->class = I2C_CLASS_HWMON;
882 strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
883 adap->algo = &omap_i2c_algo;
884 adap->dev.parent = &pdev->dev;
885
886 /* i2c device drivers may be active on return from add_adapter() */
887 adap->nr = pdev->id;
888 r = i2c_add_numbered_adapter(adap);
889 if (r) {
890 dev_err(dev->dev, "failure adding adapter\n");
891 goto err_free_irq;
892 }
893
894 return 0;
895
896 err_free_irq:
897 free_irq(dev->irq, dev);
898 err_unuse_clocks:
899 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
900 omap_i2c_idle(dev);
901 omap_i2c_put_clocks(dev);
902 err_iounmap:
903 iounmap(dev->base);
904 err_free_mem:
905 platform_set_drvdata(pdev, NULL);
906 kfree(dev);
907 err_release_region:
908 release_mem_region(mem->start, resource_size(mem));
909
910 return r;
911 }
912
913 static int
914 omap_i2c_remove(struct platform_device *pdev)
915 {
916 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
917 struct resource *mem;
918
919 platform_set_drvdata(pdev, NULL);
920
921 free_irq(dev->irq, dev);
922 i2c_del_adapter(&dev->adapter);
923 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
924 omap_i2c_put_clocks(dev);
925 iounmap(dev->base);
926 kfree(dev);
927 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
928 release_mem_region(mem->start, resource_size(mem));
929 return 0;
930 }
931
932 static struct platform_driver omap_i2c_driver = {
933 .probe = omap_i2c_probe,
934 .remove = omap_i2c_remove,
935 .driver = {
936 .name = "i2c_omap",
937 .owner = THIS_MODULE,
938 },
939 };
940
941 /* I2C may be needed to bring up other drivers */
942 static int __init
943 omap_i2c_init_driver(void)
944 {
945 return platform_driver_register(&omap_i2c_driver);
946 }
947 subsys_initcall(omap_i2c_init_driver);
948
949 static void __exit omap_i2c_exit_driver(void)
950 {
951 platform_driver_unregister(&omap_i2c_driver);
952 }
953 module_exit(omap_i2c_exit_driver);
954
955 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
956 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
957 MODULE_LICENSE("GPL");
958 MODULE_ALIAS("platform:i2c_omap");
Linux kernel - Deliverables
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