drivers/i2c/busses/i2c-piix4.c

   1 /*
   2     Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
   3     Philip Edelbrock <phil@netroedge.com>
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 2 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18 */
  19
  20 /*
  21    Supports:
  22         Intel PIIX4, 440MX
  23         Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
  24         ATI IXP200, IXP300, IXP400, SB600, SB700, SB800
  25         AMD Hudson-2
  26         SMSC Victory66
  27
  28    Note: we assume there can only be one device, with one SMBus interface.
  29 */
  30
  31 #include <linux/module.h>
  32 #include <linux/moduleparam.h>
  33 #include <linux/pci.h>
  34 #include <linux/kernel.h>
  35 #include <linux/delay.h>
  36 #include <linux/stddef.h>
  37 #include <linux/ioport.h>
  38 #include <linux/i2c.h>
  39 #include <linux/init.h>
  40 #include <linux/dmi.h>
  41 #include <linux/acpi.h>
  42 #include <linux/io.h>
  43
  44
  45 /* PIIX4 SMBus address offsets */
  46 #define SMBHSTSTS       (0 + piix4_smba)
  47 #define SMBHSLVSTS      (1 + piix4_smba)
  48 #define SMBHSTCNT       (2 + piix4_smba)
  49 #define SMBHSTCMD       (3 + piix4_smba)
  50 #define SMBHSTADD       (4 + piix4_smba)
  51 #define SMBHSTDAT0      (5 + piix4_smba)
  52 #define SMBHSTDAT1      (6 + piix4_smba)
  53 #define SMBBLKDAT       (7 + piix4_smba)
  54 #define SMBSLVCNT       (8 + piix4_smba)
  55 #define SMBSHDWCMD      (9 + piix4_smba)
  56 #define SMBSLVEVT       (0xA + piix4_smba)
  57 #define SMBSLVDAT       (0xC + piix4_smba)
  58
  59 /* count for request_region */
  60 #define SMBIOSIZE       8
  61
  62 /* PCI Address Constants */
  63 #define SMBBA           0x090
  64 #define SMBHSTCFG       0x0D2
  65 #define SMBSLVC         0x0D3
  66 #define SMBSHDW1        0x0D4
  67 #define SMBSHDW2        0x0D5
  68 #define SMBREV          0x0D6
  69
  70 /* Other settings */
  71 #define MAX_TIMEOUT     500
  72 #define  ENABLE_INT9    0
  73
  74 /* PIIX4 constants */
  75 #define PIIX4_QUICK             0x00
  76 #define PIIX4_BYTE              0x04
  77 #define PIIX4_BYTE_DATA         0x08
  78 #define PIIX4_WORD_DATA         0x0C
  79 #define PIIX4_BLOCK_DATA        0x14
  80
  81 /* insmod parameters */
  82
  83 /* If force is set to anything different from 0, we forcibly enable the
  84    PIIX4. DANGEROUS! */
  85 static int force;
  86 module_param (force, int, 0);
  87 MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
  88
  89 /* If force_addr is set to anything different from 0, we forcibly enable
  90    the PIIX4 at the given address. VERY DANGEROUS! */
  91 static int force_addr;
  92 module_param (force_addr, int, 0);
  93 MODULE_PARM_DESC(force_addr,
  94                  "Forcibly enable the PIIX4 at the given address. "
  95                  "EXTREMELY DANGEROUS!");
  96
  97 static int srvrworks_csb5_delay;
  98 static struct pci_driver piix4_driver;
  99 static struct i2c_adapter piix4_adapter;
 100
 101 static struct dmi_system_id __devinitdata piix4_dmi_blacklist[] = {
 102         {
 103                 .ident = "Sapphire AM2RD790",
 104                 .matches = {
 105                         DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
 106                         DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
 107                 },
 108         },
 109         {
 110                 .ident = "DFI Lanparty UT 790FX",
 111                 .matches = {
 112                         DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
 113                         DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
 114                 },
 115         },
 116         { }
 117 };
 118
 119 /* The IBM entry is in a separate table because we only check it
 120    on Intel-based systems */
 121 static struct dmi_system_id __devinitdata piix4_dmi_ibm[] = {
 122         {
 123                 .ident = "IBM",
 124                 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
 125         },
 126         { },
 127 };
 128
 129 struct i2c_piix4_adapdata {
 130         unsigned short smba;
 131 };
 132
 133 static int __devinit piix4_setup(struct pci_dev *PIIX4_dev,
 134                                 const struct pci_device_id *id)
 135 {
 136         unsigned char temp;
 137         unsigned short piix4_smba;
 138
 139         if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
 140             (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
 141                 srvrworks_csb5_delay = 1;
 142
 143         /* On some motherboards, it was reported that accessing the SMBus
 144            caused severe hardware problems */
 145         if (dmi_check_system(piix4_dmi_blacklist)) {
 146                 dev_err(&PIIX4_dev->dev,
 147                         "Accessing the SMBus on this system is unsafe!\n");
 148                 return -EPERM;
 149         }
 150
 151         /* Don't access SMBus on IBM systems which get corrupted eeproms */
 152         if (dmi_check_system(piix4_dmi_ibm) &&
 153                         PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
 154                 dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
 155                         "may corrupt your serial eeprom! Refusing to load "
 156                         "module!\n");
 157                 return -EPERM;
 158         }
 159
 160         /* Determine the address of the SMBus areas */
 161         if (force_addr) {
 162                 piix4_smba = force_addr & 0xfff0;
 163                 force = 0;
 164         } else {
 165                 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
 166                 piix4_smba &= 0xfff0;
 167                 if(piix4_smba == 0) {
 168                         dev_err(&PIIX4_dev->dev, "SMBus base address "
 169                                 "uninitialized - upgrade BIOS or use "
 170                                 "force_addr=0xaddr\n");
 171                         return -ENODEV;
 172                 }
 173         }
 174
 175         if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
 176                 return -ENODEV;
 177
 178         if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
 179                 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
 180                         piix4_smba);
 181                 return -EBUSY;
 182         }
 183
 184         pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
 185
 186         /* If force_addr is set, we program the new address here. Just to make
 187            sure, we disable the PIIX4 first. */
 188         if (force_addr) {
 189                 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
 190                 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
 191                 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
 192                 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
 193                         "new address %04x!\n", piix4_smba);
 194         } else if ((temp & 1) == 0) {
 195                 if (force) {
 196                         /* This should never need to be done, but has been
 197                          * noted that many Dell machines have the SMBus
 198                          * interface on the PIIX4 disabled!? NOTE: This assumes
 199                          * I/O space and other allocations WERE done by the
 200                          * Bios!  Don't complain if your hardware does weird
 201                          * things after enabling this. :') Check for Bios
 202                          * updates before resorting to this.
 203                          */
 204                         pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
 205                                               temp | 1);
 206                         dev_printk(KERN_NOTICE, &PIIX4_dev->dev,
 207                                 "WARNING: SMBus interface has been "
 208                                 "FORCEFULLY ENABLED!\n");
 209                 } else {
 210                         dev_err(&PIIX4_dev->dev,
 211                                 "Host SMBus controller not enabled!\n");
 212                         release_region(piix4_smba, SMBIOSIZE);
 213                         return -ENODEV;
 214                 }
 215         }
 216
 217         if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
 218                 dev_dbg(&PIIX4_dev->dev, "Using Interrupt 9 for SMBus.\n");
 219         else if ((temp & 0x0E) == 0)
 220                 dev_dbg(&PIIX4_dev->dev, "Using Interrupt SMI# for SMBus.\n");
 221         else
 222                 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
 223                         "(or code out of date)!\n");
 224
 225         pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
 226         dev_info(&PIIX4_dev->dev,
 227                  "SMBus Host Controller at 0x%x, revision %d\n",
 228                  piix4_smba, temp);
 229
 230         return piix4_smba;
 231 }
 232
 233 static int __devinit piix4_setup_sb800(struct pci_dev *PIIX4_dev,
 234                                 const struct pci_device_id *id)
 235 {
 236         unsigned short piix4_smba;
 237         unsigned short smba_idx = 0xcd6;
 238         u8 smba_en_lo, smba_en_hi, i2ccfg, i2ccfg_offset = 0x10, smb_en = 0x2c;
 239
 240         /* SB800 and later SMBus does not support forcing address */
 241         if (force || force_addr) {
 242                 dev_err(&PIIX4_dev->dev, "SMBus does not support "
 243                         "forcing address!\n");
 244                 return -EINVAL;
 245         }
 246
 247         /* Determine the address of the SMBus areas */
 248         if (!request_region(smba_idx, 2, "smba_idx")) {
 249                 dev_err(&PIIX4_dev->dev, "SMBus base address index region "
 250                         "0x%x already in use!\n", smba_idx);
 251                 return -EBUSY;
 252         }
 253         outb_p(smb_en, smba_idx);
 254         smba_en_lo = inb_p(smba_idx + 1);
 255         outb_p(smb_en + 1, smba_idx);
 256         smba_en_hi = inb_p(smba_idx + 1);
 257         release_region(smba_idx, 2);
 258
 259         if ((smba_en_lo & 1) == 0) {
 260                 dev_err(&PIIX4_dev->dev,
 261                         "Host SMBus controller not enabled!\n");
 262                 return -ENODEV;
 263         }
 264
 265         piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0;
 266         if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
 267                 return -ENODEV;
 268
 269         if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
 270                 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
 271                         piix4_smba);
 272                 return -EBUSY;
 273         }
 274
 275         /* Request the SMBus I2C bus config region */
 276         if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) {
 277                 dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region "
 278                         "0x%x already in use!\n", piix4_smba + i2ccfg_offset);
 279                 release_region(piix4_smba, SMBIOSIZE);
 280                 return -EBUSY;
 281         }
 282         i2ccfg = inb_p(piix4_smba + i2ccfg_offset);
 283         release_region(piix4_smba + i2ccfg_offset, 1);
 284
 285         if (i2ccfg & 1)
 286                 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus.\n");
 287         else
 288                 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus.\n");
 289
 290         dev_info(&PIIX4_dev->dev,
 291                  "SMBus Host Controller at 0x%x, revision %d\n",
 292                  piix4_smba, i2ccfg >> 4);
 293
 294         return piix4_smba;
 295 }
 296
 297 static int piix4_transaction(unsigned short piix4_smba)
 298 {
 299         int temp;
 300         int result = 0;
 301         int timeout = 0;
 302
 303         dev_dbg(&piix4_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
 304                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
 305                 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
 306                 inb_p(SMBHSTDAT1));
 307
 308         /* Make sure the SMBus host is ready to start transmitting */
 309         if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
 310                 dev_dbg(&piix4_adapter.dev, "SMBus busy (%02x). "
 311                         "Resetting...\n", temp);
 312                 outb_p(temp, SMBHSTSTS);
 313                 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
 314                         dev_err(&piix4_adapter.dev, "Failed! (%02x)\n", temp);
 315                         return -EBUSY;
 316                 } else {
 317                         dev_dbg(&piix4_adapter.dev, "Successful!\n");
 318                 }
 319         }
 320
 321         /* start the transaction by setting bit 6 */
 322         outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
 323
 324         /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
 325         if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */
 326                 msleep(2);
 327         else
 328                 msleep(1);
 329
 330         while ((++timeout < MAX_TIMEOUT) &&
 331                ((temp = inb_p(SMBHSTSTS)) & 0x01))
 332                 msleep(1);
 333
 334         /* If the SMBus is still busy, we give up */
 335         if (timeout == MAX_TIMEOUT) {
 336                 dev_err(&piix4_adapter.dev, "SMBus Timeout!\n");
 337                 result = -ETIMEDOUT;
 338         }
 339
 340         if (temp & 0x10) {
 341                 result = -EIO;
 342                 dev_err(&piix4_adapter.dev, "Error: Failed bus transaction\n");
 343         }
 344
 345         if (temp & 0x08) {
 346                 result = -EIO;
 347                 dev_dbg(&piix4_adapter.dev, "Bus collision! SMBus may be "
 348                         "locked until next hard reset. (sorry!)\n");
 349                 /* Clock stops and slave is stuck in mid-transmission */
 350         }
 351
 352         if (temp & 0x04) {
 353                 result = -ENXIO;
 354                 dev_dbg(&piix4_adapter.dev, "Error: no response!\n");
 355         }
 356
 357         if (inb_p(SMBHSTSTS) != 0x00)
 358                 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
 359
 360         if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
 361                 dev_err(&piix4_adapter.dev, "Failed reset at end of "
 362                         "transaction (%02x)\n", temp);
 363         }
 364         dev_dbg(&piix4_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, "
 365                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
 366                 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
 367                 inb_p(SMBHSTDAT1));
 368         return result;
 369 }
 370
 371 /* Return negative errno on error. */
 372 static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
 373                  unsigned short flags, char read_write,
 374                  u8 command, int size, union i2c_smbus_data * data)
 375 {
 376         struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
 377         unsigned short piix4_smba = adapdata->smba;
 378         int i, len;
 379         int status;
 380
 381         switch (size) {
 382         case I2C_SMBUS_QUICK:
 383                 outb_p((addr << 1) | read_write,
 384                        SMBHSTADD);
 385                 size = PIIX4_QUICK;
 386                 break;
 387         case I2C_SMBUS_BYTE:
 388                 outb_p((addr << 1) | read_write,
 389                        SMBHSTADD);
 390                 if (read_write == I2C_SMBUS_WRITE)
 391                         outb_p(command, SMBHSTCMD);
 392                 size = PIIX4_BYTE;
 393                 break;
 394         case I2C_SMBUS_BYTE_DATA:
 395                 outb_p((addr << 1) | read_write,
 396                        SMBHSTADD);
 397                 outb_p(command, SMBHSTCMD);
 398                 if (read_write == I2C_SMBUS_WRITE)
 399                         outb_p(data->byte, SMBHSTDAT0);
 400                 size = PIIX4_BYTE_DATA;
 401                 break;
 402         case I2C_SMBUS_WORD_DATA:
 403                 outb_p((addr << 1) | read_write,
 404                        SMBHSTADD);
 405                 outb_p(command, SMBHSTCMD);
 406                 if (read_write == I2C_SMBUS_WRITE) {
 407                         outb_p(data->word & 0xff, SMBHSTDAT0);
 408                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
 409                 }
 410                 size = PIIX4_WORD_DATA;
 411                 break;
 412         case I2C_SMBUS_BLOCK_DATA:
 413                 outb_p((addr << 1) | read_write,
 414                        SMBHSTADD);
 415                 outb_p(command, SMBHSTCMD);
 416                 if (read_write == I2C_SMBUS_WRITE) {
 417                         len = data->block[0];
 418                         if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
 419                                 return -EINVAL;
 420                         outb_p(len, SMBHSTDAT0);
 421                         i = inb_p(SMBHSTCNT);   /* Reset SMBBLKDAT */
 422                         for (i = 1; i <= len; i++)
 423                                 outb_p(data->block[i], SMBBLKDAT);
 424                 }
 425                 size = PIIX4_BLOCK_DATA;
 426                 break;
 427         default:
 428                 dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
 429                 return -EOPNOTSUPP;
 430         }
 431
 432         outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
 433
 434         status = piix4_transaction(piix4_smba);
 435         if (status)
 436                 return status;
 437
 438         if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
 439                 return 0;
 440
 441
 442         switch (size) {
 443         case PIIX4_BYTE:
 444         case PIIX4_BYTE_DATA:
 445                 data->byte = inb_p(SMBHSTDAT0);
 446                 break;
 447         case PIIX4_WORD_DATA:
 448                 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
 449                 break;
 450         case PIIX4_BLOCK_DATA:
 451                 data->block[0] = inb_p(SMBHSTDAT0);
 452                 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
 453                         return -EPROTO;
 454                 i = inb_p(SMBHSTCNT);   /* Reset SMBBLKDAT */
 455                 for (i = 1; i <= data->block[0]; i++)
 456                         data->block[i] = inb_p(SMBBLKDAT);
 457                 break;
 458         }
 459         return 0;
 460 }
 461
 462 static u32 piix4_func(struct i2c_adapter *adapter)
 463 {
 464         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 465             I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 466             I2C_FUNC_SMBUS_BLOCK_DATA;
 467 }
 468
 469 static const struct i2c_algorithm smbus_algorithm = {
 470         .smbus_xfer     = piix4_access,
 471         .functionality  = piix4_func,
 472 };
 473
 474 static struct i2c_adapter piix4_adapter = {
 475         .owner          = THIS_MODULE,
 476         .class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,
 477         .algo           = &smbus_algorithm,
 478 };
 479
 480 static struct i2c_piix4_adapdata piix4_adapter_data;
 481
 482 static DEFINE_PCI_DEVICE_TABLE(piix4_ids) = {
 483         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
 484         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
 485         { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
 486         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
 487         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
 488         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
 489         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
 490         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
 491         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 492                      PCI_DEVICE_ID_SERVERWORKS_OSB4) },
 493         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 494                      PCI_DEVICE_ID_SERVERWORKS_CSB5) },
 495         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 496                      PCI_DEVICE_ID_SERVERWORKS_CSB6) },
 497         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 498                      PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
 499         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 500                      PCI_DEVICE_ID_SERVERWORKS_HT1100LD) },
 501         { 0, }
 502 };
 503
 504 MODULE_DEVICE_TABLE (pci, piix4_ids);
 505
 506 static int __devinit piix4_probe(struct pci_dev *dev,
 507                                 const struct pci_device_id *id)
 508 {
 509         int retval;
 510
 511         if ((dev->vendor == PCI_VENDOR_ID_ATI &&
 512              dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
 513              dev->revision >= 0x40) ||
 514             dev->vendor == PCI_VENDOR_ID_AMD)
 515                 /* base address location etc changed in SB800 */
 516                 retval = piix4_setup_sb800(dev, id);
 517         else
 518                 retval = piix4_setup(dev, id);
 519
 520         if (retval < 0)
 521                 return retval;
 522
 523         piix4_adapter_data.smba = retval;
 524
 525         /* set up the sysfs linkage to our parent device */
 526         piix4_adapter.dev.parent = &dev->dev;
 527
 528         snprintf(piix4_adapter.name, sizeof(piix4_adapter.name),
 529                 "SMBus PIIX4 adapter at %04x", piix4_adapter_data.smba);
 530
 531         i2c_set_adapdata(&piix4_adapter, &piix4_adapter_data);
 532
 533         if ((retval = i2c_add_adapter(&piix4_adapter))) {
 534                 dev_err(&dev->dev, "Couldn't register adapter!\n");
 535                 release_region(piix4_adapter_data.smba, SMBIOSIZE);
 536                 piix4_adapter_data.smba = 0;
 537         }
 538
 539         return retval;
 540 }
 541
 542 static void __devexit piix4_adap_remove(struct i2c_adapter *adap)
 543 {
 544         struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
 545
 546         if (adapdata->smba) {
 547                 i2c_del_adapter(adap);
 548                 release_region(adapdata->smba, SMBIOSIZE);
 549                 adapdata->smba = 0;
 550         }
 551 }
 552
 553 static void __devexit piix4_remove(struct pci_dev *dev)
 554 {
 555         piix4_adap_remove(&piix4_adapter);
 556 }
 557
 558 static struct pci_driver piix4_driver = {
 559         .name           = "piix4_smbus",
 560         .id_table       = piix4_ids,
 561         .probe          = piix4_probe,
 562         .remove         = __devexit_p(piix4_remove),
 563 };
 564
 565 module_pci_driver(piix4_driver);
 566
 567 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and "
 568                 "Philip Edelbrock <phil@netroedge.com>");
 569 MODULE_DESCRIPTION("PIIX4 SMBus driver");
 570 MODULE_LICENSE("GPL");