drivers/i2c/busses/i2c-piix4.c

   1 /*
   2     Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
   3     Philip Edelbrock <phil@netroedge.com>
   4
   5     This program is free software; you can redistribute it and/or modify
   6     it under the terms of the GNU General Public License as published by
   7     the Free Software Foundation; either version 2 of the License, or
   8     (at your option) any later version.
   9
  10     This program is distributed in the hope that it will be useful,
  11     but WITHOUT ANY WARRANTY; without even the implied warranty of
  12     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13     GNU General Public License for more details.
  14
  15     You should have received a copy of the GNU General Public License
  16     along with this program; if not, write to the Free Software
  17     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18 */
  19
  20 /*
  21    Supports:
  22         Intel PIIX4, 440MX
  23         Serverworks OSB4, CSB5, CSB6, HT-1000
  24         ATI IXP200, IXP300, IXP400, SB600, SB700, SB800
  25         SMSC Victory66
  26
  27    Note: we assume there can only be one device, with one SMBus interface.
  28 */
  29
  30 #include <linux/module.h>
  31 #include <linux/moduleparam.h>
  32 #include <linux/pci.h>
  33 #include <linux/kernel.h>
  34 #include <linux/delay.h>
  35 #include <linux/stddef.h>
  36 #include <linux/ioport.h>
  37 #include <linux/i2c.h>
  38 #include <linux/init.h>
  39 #include <linux/dmi.h>
  40 #include <linux/acpi.h>
  41 #include <asm/io.h>
  42
  43
  44 /* PIIX4 SMBus address offsets */
  45 #define SMBHSTSTS       (0 + piix4_smba)
  46 #define SMBHSLVSTS      (1 + piix4_smba)
  47 #define SMBHSTCNT       (2 + piix4_smba)
  48 #define SMBHSTCMD       (3 + piix4_smba)
  49 #define SMBHSTADD       (4 + piix4_smba)
  50 #define SMBHSTDAT0      (5 + piix4_smba)
  51 #define SMBHSTDAT1      (6 + piix4_smba)
  52 #define SMBBLKDAT       (7 + piix4_smba)
  53 #define SMBSLVCNT       (8 + piix4_smba)
  54 #define SMBSHDWCMD      (9 + piix4_smba)
  55 #define SMBSLVEVT       (0xA + piix4_smba)
  56 #define SMBSLVDAT       (0xC + piix4_smba)
  57
  58 /* count for request_region */
  59 #define SMBIOSIZE       8
  60
  61 /* PCI Address Constants */
  62 #define SMBBA           0x090
  63 #define SMBHSTCFG       0x0D2
  64 #define SMBSLVC         0x0D3
  65 #define SMBSHDW1        0x0D4
  66 #define SMBSHDW2        0x0D5
  67 #define SMBREV          0x0D6
  68
  69 /* Other settings */
  70 #define MAX_TIMEOUT     500
  71 #define  ENABLE_INT9    0
  72
  73 /* PIIX4 constants */
  74 #define PIIX4_QUICK             0x00
  75 #define PIIX4_BYTE              0x04
  76 #define PIIX4_BYTE_DATA         0x08
  77 #define PIIX4_WORD_DATA         0x0C
  78 #define PIIX4_BLOCK_DATA        0x14
  79
  80 /* insmod parameters */
  81
  82 /* If force is set to anything different from 0, we forcibly enable the
  83    PIIX4. DANGEROUS! */
  84 static int force;
  85 module_param (force, int, 0);
  86 MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
  87
  88 /* If force_addr is set to anything different from 0, we forcibly enable
  89    the PIIX4 at the given address. VERY DANGEROUS! */
  90 static int force_addr;
  91 module_param (force_addr, int, 0);
  92 MODULE_PARM_DESC(force_addr,
  93                  "Forcibly enable the PIIX4 at the given address. "
  94                  "EXTREMELY DANGEROUS!");
  95
  96 static unsigned short piix4_smba;
  97 static int srvrworks_csb5_delay;
  98 static struct pci_driver piix4_driver;
  99 static struct i2c_adapter piix4_adapter;
 100
 101 static struct dmi_system_id __devinitdata piix4_dmi_blacklist[] = {
 102         {
 103                 .ident = "Sapphire AM2RD790",
 104                 .matches = {
 105                         DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
 106                         DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
 107                 },
 108         },
 109         {
 110                 .ident = "DFI Lanparty UT 790FX",
 111                 .matches = {
 112                         DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
 113                         DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
 114                 },
 115         },
 116         { }
 117 };
 118
 119 /* The IBM entry is in a separate table because we only check it
 120    on Intel-based systems */
 121 static struct dmi_system_id __devinitdata piix4_dmi_ibm[] = {
 122         {
 123                 .ident = "IBM",
 124                 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
 125         },
 126         { },
 127 };
 128
 129 static int __devinit piix4_setup(struct pci_dev *PIIX4_dev,
 130                                 const struct pci_device_id *id)
 131 {
 132         unsigned char temp;
 133
 134         if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
 135             (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
 136                 srvrworks_csb5_delay = 1;
 137
 138         /* On some motherboards, it was reported that accessing the SMBus
 139            caused severe hardware problems */
 140         if (dmi_check_system(piix4_dmi_blacklist)) {
 141                 dev_err(&PIIX4_dev->dev,
 142                         "Accessing the SMBus on this system is unsafe!\n");
 143                 return -EPERM;
 144         }
 145
 146         /* Don't access SMBus on IBM systems which get corrupted eeproms */
 147         if (dmi_check_system(piix4_dmi_ibm) &&
 148                         PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
 149                 dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
 150                         "may corrupt your serial eeprom! Refusing to load "
 151                         "module!\n");
 152                 return -EPERM;
 153         }
 154
 155         /* Determine the address of the SMBus areas */
 156         if (force_addr) {
 157                 piix4_smba = force_addr & 0xfff0;
 158                 force = 0;
 159         } else {
 160                 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
 161                 piix4_smba &= 0xfff0;
 162                 if(piix4_smba == 0) {
 163                         dev_err(&PIIX4_dev->dev, "SMBus base address "
 164                                 "uninitialized - upgrade BIOS or use "
 165                                 "force_addr=0xaddr\n");
 166                         return -ENODEV;
 167                 }
 168         }
 169
 170         if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
 171                 return -EBUSY;
 172
 173         if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
 174                 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
 175                         piix4_smba);
 176                 return -EBUSY;
 177         }
 178
 179         pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
 180
 181         /* If force_addr is set, we program the new address here. Just to make
 182            sure, we disable the PIIX4 first. */
 183         if (force_addr) {
 184                 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
 185                 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
 186                 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
 187                 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
 188                         "new address %04x!\n", piix4_smba);
 189         } else if ((temp & 1) == 0) {
 190                 if (force) {
 191                         /* This should never need to be done, but has been
 192                          * noted that many Dell machines have the SMBus
 193                          * interface on the PIIX4 disabled!? NOTE: This assumes
 194                          * I/O space and other allocations WERE done by the
 195                          * Bios!  Don't complain if your hardware does weird
 196                          * things after enabling this. :') Check for Bios
 197                          * updates before resorting to this.
 198                          */
 199                         pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
 200                                               temp | 1);
 201                         dev_printk(KERN_NOTICE, &PIIX4_dev->dev,
 202                                 "WARNING: SMBus interface has been "
 203                                 "FORCEFULLY ENABLED!\n");
 204                 } else {
 205                         dev_err(&PIIX4_dev->dev,
 206                                 "Host SMBus controller not enabled!\n");
 207                         release_region(piix4_smba, SMBIOSIZE);
 208                         piix4_smba = 0;
 209                         return -ENODEV;
 210                 }
 211         }
 212
 213         if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
 214                 dev_dbg(&PIIX4_dev->dev, "Using Interrupt 9 for SMBus.\n");
 215         else if ((temp & 0x0E) == 0)
 216                 dev_dbg(&PIIX4_dev->dev, "Using Interrupt SMI# for SMBus.\n");
 217         else
 218                 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
 219                         "(or code out of date)!\n");
 220
 221         pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
 222         dev_info(&PIIX4_dev->dev,
 223                  "SMBus Host Controller at 0x%x, revision %d\n",
 224                  piix4_smba, temp);
 225
 226         return 0;
 227 }
 228
 229 static int piix4_transaction(void)
 230 {
 231         int temp;
 232         int result = 0;
 233         int timeout = 0;
 234
 235         dev_dbg(&piix4_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
 236                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
 237                 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
 238                 inb_p(SMBHSTDAT1));
 239
 240         /* Make sure the SMBus host is ready to start transmitting */
 241         if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
 242                 dev_dbg(&piix4_adapter.dev, "SMBus busy (%02x). "
 243                         "Resetting...\n", temp);
 244                 outb_p(temp, SMBHSTSTS);
 245                 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
 246                         dev_err(&piix4_adapter.dev, "Failed! (%02x)\n", temp);
 247                         return -EBUSY;
 248                 } else {
 249                         dev_dbg(&piix4_adapter.dev, "Successful!\n");
 250                 }
 251         }
 252
 253         /* start the transaction by setting bit 6 */
 254         outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
 255
 256         /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
 257         if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */
 258                 msleep(2);
 259         else
 260                 msleep(1);
 261
 262         while ((timeout++ < MAX_TIMEOUT) &&
 263                ((temp = inb_p(SMBHSTSTS)) & 0x01))
 264                 msleep(1);
 265
 266         /* If the SMBus is still busy, we give up */
 267         if (timeout >= MAX_TIMEOUT) {
 268                 dev_err(&piix4_adapter.dev, "SMBus Timeout!\n");
 269                 result = -ETIMEDOUT;
 270         }
 271
 272         if (temp & 0x10) {
 273                 result = -EIO;
 274                 dev_err(&piix4_adapter.dev, "Error: Failed bus transaction\n");
 275         }
 276
 277         if (temp & 0x08) {
 278                 result = -EIO;
 279                 dev_dbg(&piix4_adapter.dev, "Bus collision! SMBus may be "
 280                         "locked until next hard reset. (sorry!)\n");
 281                 /* Clock stops and slave is stuck in mid-transmission */
 282         }
 283
 284         if (temp & 0x04) {
 285                 result = -ENXIO;
 286                 dev_dbg(&piix4_adapter.dev, "Error: no response!\n");
 287         }
 288
 289         if (inb_p(SMBHSTSTS) != 0x00)
 290                 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
 291
 292         if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
 293                 dev_err(&piix4_adapter.dev, "Failed reset at end of "
 294                         "transaction (%02x)\n", temp);
 295         }
 296         dev_dbg(&piix4_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, "
 297                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
 298                 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
 299                 inb_p(SMBHSTDAT1));
 300         return result;
 301 }
 302
 303 /* Return negative errno on error. */
 304 static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
 305                  unsigned short flags, char read_write,
 306                  u8 command, int size, union i2c_smbus_data * data)
 307 {
 308         int i, len;
 309         int status;
 310
 311         switch (size) {
 312         case I2C_SMBUS_QUICK:
 313                 outb_p((addr << 1) | read_write,
 314                        SMBHSTADD);
 315                 size = PIIX4_QUICK;
 316                 break;
 317         case I2C_SMBUS_BYTE:
 318                 outb_p((addr << 1) | read_write,
 319                        SMBHSTADD);
 320                 if (read_write == I2C_SMBUS_WRITE)
 321                         outb_p(command, SMBHSTCMD);
 322                 size = PIIX4_BYTE;
 323                 break;
 324         case I2C_SMBUS_BYTE_DATA:
 325                 outb_p((addr << 1) | read_write,
 326                        SMBHSTADD);
 327                 outb_p(command, SMBHSTCMD);
 328                 if (read_write == I2C_SMBUS_WRITE)
 329                         outb_p(data->byte, SMBHSTDAT0);
 330                 size = PIIX4_BYTE_DATA;
 331                 break;
 332         case I2C_SMBUS_WORD_DATA:
 333                 outb_p((addr << 1) | read_write,
 334                        SMBHSTADD);
 335                 outb_p(command, SMBHSTCMD);
 336                 if (read_write == I2C_SMBUS_WRITE) {
 337                         outb_p(data->word & 0xff, SMBHSTDAT0);
 338                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
 339                 }
 340                 size = PIIX4_WORD_DATA;
 341                 break;
 342         case I2C_SMBUS_BLOCK_DATA:
 343                 outb_p((addr << 1) | read_write,
 344                        SMBHSTADD);
 345                 outb_p(command, SMBHSTCMD);
 346                 if (read_write == I2C_SMBUS_WRITE) {
 347                         len = data->block[0];
 348                         if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
 349                                 return -EINVAL;
 350                         outb_p(len, SMBHSTDAT0);
 351                         i = inb_p(SMBHSTCNT);   /* Reset SMBBLKDAT */
 352                         for (i = 1; i <= len; i++)
 353                                 outb_p(data->block[i], SMBBLKDAT);
 354                 }
 355                 size = PIIX4_BLOCK_DATA;
 356                 break;
 357         default:
 358                 dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
 359                 return -EOPNOTSUPP;
 360         }
 361
 362         outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
 363
 364         status = piix4_transaction();
 365         if (status)
 366                 return status;
 367
 368         if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
 369                 return 0;
 370
 371
 372         switch (size) {
 373         case PIIX4_BYTE:
 374         case PIIX4_BYTE_DATA:
 375                 data->byte = inb_p(SMBHSTDAT0);
 376                 break;
 377         case PIIX4_WORD_DATA:
 378                 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
 379                 break;
 380         case PIIX4_BLOCK_DATA:
 381                 data->block[0] = inb_p(SMBHSTDAT0);
 382                 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
 383                         return -EPROTO;
 384                 i = inb_p(SMBHSTCNT);   /* Reset SMBBLKDAT */
 385                 for (i = 1; i <= data->block[0]; i++)
 386                         data->block[i] = inb_p(SMBBLKDAT);
 387                 break;
 388         }
 389         return 0;
 390 }
 391
 392 static u32 piix4_func(struct i2c_adapter *adapter)
 393 {
 394         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 395             I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 396             I2C_FUNC_SMBUS_BLOCK_DATA;
 397 }
 398
 399 static const struct i2c_algorithm smbus_algorithm = {
 400         .smbus_xfer     = piix4_access,
 401         .functionality  = piix4_func,
 402 };
 403
 404 static struct i2c_adapter piix4_adapter = {
 405         .owner          = THIS_MODULE,
 406         .id             = I2C_HW_SMBUS_PIIX4,
 407         .class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,
 408         .algo           = &smbus_algorithm,
 409 };
 410
 411 static struct pci_device_id piix4_ids[] = {
 412         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
 413         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
 414         { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
 415         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
 416         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
 417         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
 418         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
 419         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 420                      PCI_DEVICE_ID_SERVERWORKS_OSB4) },
 421         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 422                      PCI_DEVICE_ID_SERVERWORKS_CSB5) },
 423         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 424                      PCI_DEVICE_ID_SERVERWORKS_CSB6) },
 425         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 426                      PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
 427         { 0, }
 428 };
 429
 430 MODULE_DEVICE_TABLE (pci, piix4_ids);
 431
 432 static int __devinit piix4_probe(struct pci_dev *dev,
 433                                 const struct pci_device_id *id)
 434 {
 435         int retval;
 436
 437         retval = piix4_setup(dev, id);
 438         if (retval)
 439                 return retval;
 440
 441         /* set up the sysfs linkage to our parent device */
 442         piix4_adapter.dev.parent = &dev->dev;
 443
 444         snprintf(piix4_adapter.name, sizeof(piix4_adapter.name),
 445                 "SMBus PIIX4 adapter at %04x", piix4_smba);
 446
 447         if ((retval = i2c_add_adapter(&piix4_adapter))) {
 448                 dev_err(&dev->dev, "Couldn't register adapter!\n");
 449                 release_region(piix4_smba, SMBIOSIZE);
 450                 piix4_smba = 0;
 451         }
 452
 453         return retval;
 454 }
 455
 456 static void __devexit piix4_remove(struct pci_dev *dev)
 457 {
 458         if (piix4_smba) {
 459                 i2c_del_adapter(&piix4_adapter);
 460                 release_region(piix4_smba, SMBIOSIZE);
 461                 piix4_smba = 0;
 462         }
 463 }
 464
 465 static struct pci_driver piix4_driver = {
 466         .name           = "piix4_smbus",
 467         .id_table       = piix4_ids,
 468         .probe          = piix4_probe,
 469         .remove         = __devexit_p(piix4_remove),
 470 };
 471
 472 static int __init i2c_piix4_init(void)
 473 {
 474         return pci_register_driver(&piix4_driver);
 475 }
 476
 477 static void __exit i2c_piix4_exit(void)
 478 {
 479         pci_unregister_driver(&piix4_driver);
 480 }
 481
 482 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and "
 483                 "Philip Edelbrock <phil@netroedge.com>");
 484 MODULE_DESCRIPTION("PIIX4 SMBus driver");
 485 MODULE_LICENSE("GPL");
 486
 487 module_init(i2c_piix4_init);
 488 module_exit(i2c_piix4_exit);