drivers/i2c/busses/i2c-pnx.c

   1 /*
   2  * Provides I2C support for Philips PNX010x/PNX4008 boards.
   3  *
   4  * Authors: Dennis Kovalev <dkovalev@ru.mvista.com>
   5  *          Vitaly Wool <vwool@ru.mvista.com>
   6  *
   7  * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under
   8  * the terms of the GNU General Public License version 2. This program
   9  * is licensed "as is" without any warranty of any kind, whether express
  10  * or implied.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/ioport.h>
  16 #include <linux/delay.h>
  17 #include <linux/i2c.h>
  18 #include <linux/timer.h>
  19 #include <linux/completion.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/i2c-pnx.h>
  22 #include <linux/io.h>
  23 #include <linux/err.h>
  24 #include <linux/clk.h>
  25 #include <linux/slab.h>
  26 #include <linux/of_i2c.h>
  27
  28 #define I2C_PNX_TIMEOUT_DEFAULT         10 /* msec */
  29 #define I2C_PNX_SPEED_KHZ_DEFAULT       100
  30 #define I2C_PNX_REGION_SIZE             0x100
  31
  32 enum {
  33         mstatus_tdi = 0x00000001,
  34         mstatus_afi = 0x00000002,
  35         mstatus_nai = 0x00000004,
  36         mstatus_drmi = 0x00000008,
  37         mstatus_active = 0x00000020,
  38         mstatus_scl = 0x00000040,
  39         mstatus_sda = 0x00000080,
  40         mstatus_rff = 0x00000100,
  41         mstatus_rfe = 0x00000200,
  42         mstatus_tff = 0x00000400,
  43         mstatus_tfe = 0x00000800,
  44 };
  45
  46 enum {
  47         mcntrl_tdie = 0x00000001,
  48         mcntrl_afie = 0x00000002,
  49         mcntrl_naie = 0x00000004,
  50         mcntrl_drmie = 0x00000008,
  51         mcntrl_daie = 0x00000020,
  52         mcntrl_rffie = 0x00000040,
  53         mcntrl_tffie = 0x00000080,
  54         mcntrl_reset = 0x00000100,
  55         mcntrl_cdbmode = 0x00000400,
  56 };
  57
  58 enum {
  59         rw_bit = 1 << 0,
  60         start_bit = 1 << 8,
  61         stop_bit = 1 << 9,
  62 };
  63
  64 #define I2C_REG_RX(a)   ((a)->ioaddr)           /* Rx FIFO reg (RO) */
  65 #define I2C_REG_TX(a)   ((a)->ioaddr)           /* Tx FIFO reg (WO) */
  66 #define I2C_REG_STS(a)  ((a)->ioaddr + 0x04)    /* Status reg (RO) */
  67 #define I2C_REG_CTL(a)  ((a)->ioaddr + 0x08)    /* Ctl reg */
  68 #define I2C_REG_CKL(a)  ((a)->ioaddr + 0x0c)    /* Clock divider low */
  69 #define I2C_REG_CKH(a)  ((a)->ioaddr + 0x10)    /* Clock divider high */
  70 #define I2C_REG_ADR(a)  ((a)->ioaddr + 0x14)    /* I2C address */
  71 #define I2C_REG_RFL(a)  ((a)->ioaddr + 0x18)    /* Rx FIFO level (RO) */
  72 #define I2C_REG_TFL(a)  ((a)->ioaddr + 0x1c)    /* Tx FIFO level (RO) */
  73 #define I2C_REG_RXB(a)  ((a)->ioaddr + 0x20)    /* Num of bytes Rx-ed (RO) */
  74 #define I2C_REG_TXB(a)  ((a)->ioaddr + 0x24)    /* Num of bytes Tx-ed (RO) */
  75 #define I2C_REG_TXS(a)  ((a)->ioaddr + 0x28)    /* Tx slave FIFO (RO) */
  76 #define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c)    /* Tx slave FIFO level (RO) */
  77
  78 static inline int wait_timeout(struct i2c_pnx_algo_data *data)
  79 {
  80         long timeout = data->timeout;
  81         while (timeout > 0 &&
  82                         (ioread32(I2C_REG_STS(data)) & mstatus_active)) {
  83                 mdelay(1);
  84                 timeout--;
  85         }
  86         return (timeout <= 0);
  87 }
  88
  89 static inline int wait_reset(struct i2c_pnx_algo_data *data)
  90 {
  91         long timeout = data->timeout;
  92         while (timeout > 0 &&
  93                         (ioread32(I2C_REG_CTL(data)) & mcntrl_reset)) {
  94                 mdelay(1);
  95                 timeout--;
  96         }
  97         return (timeout <= 0);
  98 }
  99
 100 static inline void i2c_pnx_arm_timer(struct i2c_pnx_algo_data *alg_data)
 101 {
 102         struct timer_list *timer = &alg_data->mif.timer;
 103         unsigned long expires = msecs_to_jiffies(alg_data->timeout);
 104
 105         if (expires <= 1)
 106                 expires = 2;
 107
 108         del_timer_sync(timer);
 109
 110         dev_dbg(&alg_data->adapter.dev, "Timer armed at %lu plus %lu jiffies.\n",
 111                 jiffies, expires);
 112
 113         timer->expires = jiffies + expires;
 114         timer->data = (unsigned long)alg_data;
 115
 116         add_timer(timer);
 117 }
 118
 119 /**
 120  * i2c_pnx_start - start a device
 121  * @slave_addr:         slave address
 122  * @adap:               pointer to adapter structure
 123  *
 124  * Generate a START signal in the desired mode.
 125  */
 126 static int i2c_pnx_start(unsigned char slave_addr,
 127         struct i2c_pnx_algo_data *alg_data)
 128 {
 129         dev_dbg(&alg_data->adapter.dev, "%s(): addr 0x%x mode %d\n", __func__,
 130                 slave_addr, alg_data->mif.mode);
 131
 132         /* Check for 7 bit slave addresses only */
 133         if (slave_addr & ~0x7f) {
 134                 dev_err(&alg_data->adapter.dev,
 135                         "%s: Invalid slave address %x. Only 7-bit addresses are supported\n",
 136                         alg_data->adapter.name, slave_addr);
 137                 return -EINVAL;
 138         }
 139
 140         /* First, make sure bus is idle */
 141         if (wait_timeout(alg_data)) {
 142                 /* Somebody else is monopolizing the bus */
 143                 dev_err(&alg_data->adapter.dev,
 144                         "%s: Bus busy. Slave addr = %02x, cntrl = %x, stat = %x\n",
 145                         alg_data->adapter.name, slave_addr,
 146                         ioread32(I2C_REG_CTL(alg_data)),
 147                         ioread32(I2C_REG_STS(alg_data)));
 148                 return -EBUSY;
 149         } else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) {
 150                 /* Sorry, we lost the bus */
 151                 dev_err(&alg_data->adapter.dev,
 152                         "%s: Arbitration failure. Slave addr = %02x\n",
 153                         alg_data->adapter.name, slave_addr);
 154                 return -EIO;
 155         }
 156
 157         /*
 158          * OK, I2C is enabled and we have the bus.
 159          * Clear the current TDI and AFI status flags.
 160          */
 161         iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi,
 162                   I2C_REG_STS(alg_data));
 163
 164         dev_dbg(&alg_data->adapter.dev, "%s(): sending %#x\n", __func__,
 165                 (slave_addr << 1) | start_bit | alg_data->mif.mode);
 166
 167         /* Write the slave address, START bit and R/W bit */
 168         iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode,
 169                   I2C_REG_TX(alg_data));
 170
 171         dev_dbg(&alg_data->adapter.dev, "%s(): exit\n", __func__);
 172
 173         return 0;
 174 }
 175
 176 /**
 177  * i2c_pnx_stop - stop a device
 178  * @adap:               pointer to I2C adapter structure
 179  *
 180  * Generate a STOP signal to terminate the master transaction.
 181  */
 182 static void i2c_pnx_stop(struct i2c_pnx_algo_data *alg_data)
 183 {
 184         /* Only 1 msec max timeout due to interrupt context */
 185         long timeout = 1000;
 186
 187         dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
 188                 __func__, ioread32(I2C_REG_STS(alg_data)));
 189
 190         /* Write a STOP bit to TX FIFO */
 191         iowrite32(0xff | stop_bit, I2C_REG_TX(alg_data));
 192
 193         /* Wait until the STOP is seen. */
 194         while (timeout > 0 &&
 195                (ioread32(I2C_REG_STS(alg_data)) & mstatus_active)) {
 196                 /* may be called from interrupt context */
 197                 udelay(1);
 198                 timeout--;
 199         }
 200
 201         dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
 202                 __func__, ioread32(I2C_REG_STS(alg_data)));
 203 }
 204
 205 /**
 206  * i2c_pnx_master_xmit - transmit data to slave
 207  * @adap:               pointer to I2C adapter structure
 208  *
 209  * Sends one byte of data to the slave
 210  */
 211 static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data *alg_data)
 212 {
 213         u32 val;
 214
 215         dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
 216                 __func__, ioread32(I2C_REG_STS(alg_data)));
 217
 218         if (alg_data->mif.len > 0) {
 219                 /* We still have something to talk about... */
 220                 val = *alg_data->mif.buf++;
 221
 222                 if (alg_data->mif.len == 1)
 223                         val |= stop_bit;
 224
 225                 alg_data->mif.len--;
 226                 iowrite32(val, I2C_REG_TX(alg_data));
 227
 228                 dev_dbg(&alg_data->adapter.dev, "%s(): xmit %#x [%d]\n",
 229                         __func__, val, alg_data->mif.len + 1);
 230
 231                 if (alg_data->mif.len == 0) {
 232                         if (alg_data->last) {
 233                                 /* Wait until the STOP is seen. */
 234                                 if (wait_timeout(alg_data))
 235                                         dev_err(&alg_data->adapter.dev,
 236                                                 "The bus is still active after timeout\n");
 237                         }
 238                         /* Disable master interrupts */
 239                         iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
 240                                 ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
 241                                   I2C_REG_CTL(alg_data));
 242
 243                         del_timer_sync(&alg_data->mif.timer);
 244
 245                         dev_dbg(&alg_data->adapter.dev,
 246                                 "%s(): Waking up xfer routine.\n",
 247                                 __func__);
 248
 249                         complete(&alg_data->mif.complete);
 250                 }
 251         } else if (alg_data->mif.len == 0) {
 252                 /* zero-sized transfer */
 253                 i2c_pnx_stop(alg_data);
 254
 255                 /* Disable master interrupts. */
 256                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
 257                         ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
 258                           I2C_REG_CTL(alg_data));
 259
 260                 /* Stop timer. */
 261                 del_timer_sync(&alg_data->mif.timer);
 262                 dev_dbg(&alg_data->adapter.dev,
 263                         "%s(): Waking up xfer routine after zero-xfer.\n",
 264                         __func__);
 265
 266                 complete(&alg_data->mif.complete);
 267         }
 268
 269         dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
 270                 __func__, ioread32(I2C_REG_STS(alg_data)));
 271
 272         return 0;
 273 }
 274
 275 /**
 276  * i2c_pnx_master_rcv - receive data from slave
 277  * @adap:               pointer to I2C adapter structure
 278  *
 279  * Reads one byte data from the slave
 280  */
 281 static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data *alg_data)
 282 {
 283         unsigned int val = 0;
 284         u32 ctl = 0;
 285
 286         dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
 287                 __func__, ioread32(I2C_REG_STS(alg_data)));
 288
 289         /* Check, whether there is already data,
 290          * or we didn't 'ask' for it yet.
 291          */
 292         if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) {
 293                 dev_dbg(&alg_data->adapter.dev,
 294                         "%s(): Write dummy data to fill Rx-fifo...\n",
 295                         __func__);
 296
 297                 if (alg_data->mif.len == 1) {
 298                         /* Last byte, do not acknowledge next rcv. */
 299                         val |= stop_bit;
 300
 301                         /*
 302                          * Enable interrupt RFDAIE (data in Rx fifo),
 303                          * and disable DRMIE (need data for Tx)
 304                          */
 305                         ctl = ioread32(I2C_REG_CTL(alg_data));
 306                         ctl |= mcntrl_rffie | mcntrl_daie;
 307                         ctl &= ~mcntrl_drmie;
 308                         iowrite32(ctl, I2C_REG_CTL(alg_data));
 309                 }
 310
 311                 /*
 312                  * Now we'll 'ask' for data:
 313                  * For each byte we want to receive, we must
 314                  * write a (dummy) byte to the Tx-FIFO.
 315                  */
 316                 iowrite32(val, I2C_REG_TX(alg_data));
 317
 318                 return 0;
 319         }
 320
 321         /* Handle data. */
 322         if (alg_data->mif.len > 0) {
 323                 val = ioread32(I2C_REG_RX(alg_data));
 324                 *alg_data->mif.buf++ = (u8) (val & 0xff);
 325                 dev_dbg(&alg_data->adapter.dev, "%s(): rcv 0x%x [%d]\n",
 326                         __func__, val, alg_data->mif.len);
 327
 328                 alg_data->mif.len--;
 329                 if (alg_data->mif.len == 0) {
 330                         if (alg_data->last)
 331                                 /* Wait until the STOP is seen. */
 332                                 if (wait_timeout(alg_data))
 333                                         dev_err(&alg_data->adapter.dev,
 334                                                 "The bus is still active after timeout\n");
 335
 336                         /* Disable master interrupts */
 337                         ctl = ioread32(I2C_REG_CTL(alg_data));
 338                         ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
 339                                  mcntrl_drmie | mcntrl_daie);
 340                         iowrite32(ctl, I2C_REG_CTL(alg_data));
 341
 342                         /* Kill timer. */
 343                         del_timer_sync(&alg_data->mif.timer);
 344                         complete(&alg_data->mif.complete);
 345                 }
 346         }
 347
 348         dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
 349                 __func__, ioread32(I2C_REG_STS(alg_data)));
 350
 351         return 0;
 352 }
 353
 354 static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id)
 355 {
 356         struct i2c_pnx_algo_data *alg_data = dev_id;
 357         u32 stat, ctl;
 358
 359         dev_dbg(&alg_data->adapter.dev,
 360                 "%s(): mstat = %x mctrl = %x, mode = %d\n",
 361                 __func__,
 362                 ioread32(I2C_REG_STS(alg_data)),
 363                 ioread32(I2C_REG_CTL(alg_data)),
 364                 alg_data->mif.mode);
 365         stat = ioread32(I2C_REG_STS(alg_data));
 366
 367         /* let's see what kind of event this is */
 368         if (stat & mstatus_afi) {
 369                 /* We lost arbitration in the midst of a transfer */
 370                 alg_data->mif.ret = -EIO;
 371
 372                 /* Disable master interrupts. */
 373                 ctl = ioread32(I2C_REG_CTL(alg_data));
 374                 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
 375                          mcntrl_drmie);
 376                 iowrite32(ctl, I2C_REG_CTL(alg_data));
 377
 378                 /* Stop timer, to prevent timeout. */
 379                 del_timer_sync(&alg_data->mif.timer);
 380                 complete(&alg_data->mif.complete);
 381         } else if (stat & mstatus_nai) {
 382                 /* Slave did not acknowledge, generate a STOP */
 383                 dev_dbg(&alg_data->adapter.dev,
 384                         "%s(): Slave did not acknowledge, generating a STOP.\n",
 385                         __func__);
 386                 i2c_pnx_stop(alg_data);
 387
 388                 /* Disable master interrupts. */
 389                 ctl = ioread32(I2C_REG_CTL(alg_data));
 390                 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
 391                          mcntrl_drmie);
 392                 iowrite32(ctl, I2C_REG_CTL(alg_data));
 393
 394                 /* Our return value. */
 395                 alg_data->mif.ret = -EIO;
 396
 397                 /* Stop timer, to prevent timeout. */
 398                 del_timer_sync(&alg_data->mif.timer);
 399                 complete(&alg_data->mif.complete);
 400         } else {
 401                 /*
 402                  * Two options:
 403                  * - Master Tx needs data.
 404                  * - There is data in the Rx-fifo
 405                  * The latter is only the case if we have requested for data,
 406                  * via a dummy write. (See 'i2c_pnx_master_rcv'.)
 407                  * We therefore check, as a sanity check, whether that interrupt
 408                  * has been enabled.
 409                  */
 410                 if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) {
 411                         if (alg_data->mif.mode == I2C_SMBUS_WRITE) {
 412                                 i2c_pnx_master_xmit(alg_data);
 413                         } else if (alg_data->mif.mode == I2C_SMBUS_READ) {
 414                                 i2c_pnx_master_rcv(alg_data);
 415                         }
 416                 }
 417         }
 418
 419         /* Clear TDI and AFI bits */
 420         stat = ioread32(I2C_REG_STS(alg_data));
 421         iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data));
 422
 423         dev_dbg(&alg_data->adapter.dev,
 424                 "%s(): exiting, stat = %x ctrl = %x.\n",
 425                  __func__, ioread32(I2C_REG_STS(alg_data)),
 426                  ioread32(I2C_REG_CTL(alg_data)));
 427
 428         return IRQ_HANDLED;
 429 }
 430
 431 static void i2c_pnx_timeout(unsigned long data)
 432 {
 433         struct i2c_pnx_algo_data *alg_data = (struct i2c_pnx_algo_data *)data;
 434         u32 ctl;
 435
 436         dev_err(&alg_data->adapter.dev,
 437                 "Master timed out. stat = %04x, cntrl = %04x. Resetting master...\n",
 438                 ioread32(I2C_REG_STS(alg_data)),
 439                 ioread32(I2C_REG_CTL(alg_data)));
 440
 441         /* Reset master and disable interrupts */
 442         ctl = ioread32(I2C_REG_CTL(alg_data));
 443         ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | mcntrl_drmie);
 444         iowrite32(ctl, I2C_REG_CTL(alg_data));
 445
 446         ctl |= mcntrl_reset;
 447         iowrite32(ctl, I2C_REG_CTL(alg_data));
 448         wait_reset(alg_data);
 449         alg_data->mif.ret = -EIO;
 450         complete(&alg_data->mif.complete);
 451 }
 452
 453 static inline void bus_reset_if_active(struct i2c_pnx_algo_data *alg_data)
 454 {
 455         u32 stat;
 456
 457         if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) {
 458                 dev_err(&alg_data->adapter.dev,
 459                         "%s: Bus is still active after xfer. Reset it...\n",
 460                         alg_data->adapter.name);
 461                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
 462                           I2C_REG_CTL(alg_data));
 463                 wait_reset(alg_data);
 464         } else if (!(stat & mstatus_rfe) || !(stat & mstatus_tfe)) {
 465                 /* If there is data in the fifo's after transfer,
 466                  * flush fifo's by reset.
 467                  */
 468                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
 469                           I2C_REG_CTL(alg_data));
 470                 wait_reset(alg_data);
 471         } else if (stat & mstatus_nai) {
 472                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
 473                           I2C_REG_CTL(alg_data));
 474                 wait_reset(alg_data);
 475         }
 476 }
 477
 478 /**
 479  * i2c_pnx_xfer - generic transfer entry point
 480  * @adap:               pointer to I2C adapter structure
 481  * @msgs:               array of messages
 482  * @num:                number of messages
 483  *
 484  * Initiates the transfer
 485  */
 486 static int
 487 i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 488 {
 489         struct i2c_msg *pmsg;
 490         int rc = 0, completed = 0, i;
 491         struct i2c_pnx_algo_data *alg_data = adap->algo_data;
 492         u32 stat = ioread32(I2C_REG_STS(alg_data));
 493
 494         dev_dbg(&alg_data->adapter.dev,
 495                 "%s(): entering: %d messages, stat = %04x.\n",
 496                 __func__, num, ioread32(I2C_REG_STS(alg_data)));
 497
 498         bus_reset_if_active(alg_data);
 499
 500         /* Process transactions in a loop. */
 501         for (i = 0; rc >= 0 && i < num; i++) {
 502                 u8 addr;
 503
 504                 pmsg = &msgs[i];
 505                 addr = pmsg->addr;
 506
 507                 if (pmsg->flags & I2C_M_TEN) {
 508                         dev_err(&alg_data->adapter.dev,
 509                                 "%s: 10 bits addr not supported!\n",
 510                                 alg_data->adapter.name);
 511                         rc = -EINVAL;
 512                         break;
 513                 }
 514
 515                 alg_data->mif.buf = pmsg->buf;
 516                 alg_data->mif.len = pmsg->len;
 517                 alg_data->mif.mode = (pmsg->flags & I2C_M_RD) ?
 518                         I2C_SMBUS_READ : I2C_SMBUS_WRITE;
 519                 alg_data->mif.ret = 0;
 520                 alg_data->last = (i == num - 1);
 521
 522                 dev_dbg(&alg_data->adapter.dev, "%s(): mode %d, %d bytes\n",
 523                         __func__, alg_data->mif.mode, alg_data->mif.len);
 524
 525                 i2c_pnx_arm_timer(alg_data);
 526
 527                 /* initialize the completion var */
 528                 init_completion(&alg_data->mif.complete);
 529
 530                 /* Enable master interrupt */
 531                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_afie |
 532                                 mcntrl_naie | mcntrl_drmie,
 533                           I2C_REG_CTL(alg_data));
 534
 535                 /* Put start-code and slave-address on the bus. */
 536                 rc = i2c_pnx_start(addr, alg_data);
 537                 if (rc < 0)
 538                         break;
 539
 540                 /* Wait for completion */
 541                 wait_for_completion(&alg_data->mif.complete);
 542
 543                 if (!(rc = alg_data->mif.ret))
 544                         completed++;
 545                 dev_dbg(&alg_data->adapter.dev,
 546                         "%s(): Complete, return code = %d.\n",
 547                         __func__, rc);
 548
 549                 /* Clear TDI and AFI bits in case they are set. */
 550                 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) {
 551                         dev_dbg(&alg_data->adapter.dev,
 552                                 "%s: TDI still set... clearing now.\n",
 553                                 alg_data->adapter.name);
 554                         iowrite32(stat, I2C_REG_STS(alg_data));
 555                 }
 556                 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) {
 557                         dev_dbg(&alg_data->adapter.dev,
 558                                 "%s: AFI still set... clearing now.\n",
 559                                 alg_data->adapter.name);
 560                         iowrite32(stat, I2C_REG_STS(alg_data));
 561                 }
 562         }
 563
 564         bus_reset_if_active(alg_data);
 565
 566         /* Cleanup to be sure... */
 567         alg_data->mif.buf = NULL;
 568         alg_data->mif.len = 0;
 569
 570         dev_dbg(&alg_data->adapter.dev, "%s(): exiting, stat = %x\n",
 571                 __func__, ioread32(I2C_REG_STS(alg_data)));
 572
 573         if (completed != num)
 574                 return ((rc < 0) ? rc : -EREMOTEIO);
 575
 576         return num;
 577 }
 578
 579 static u32 i2c_pnx_func(struct i2c_adapter *adapter)
 580 {
 581         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 582 }
 583
 584 static struct i2c_algorithm pnx_algorithm = {
 585         .master_xfer = i2c_pnx_xfer,
 586         .functionality = i2c_pnx_func,
 587 };
 588
 589 #ifdef CONFIG_PM
 590 static int i2c_pnx_controller_suspend(struct platform_device *pdev,
 591                                       pm_message_t state)
 592 {
 593         struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
 594
 595         clk_disable(alg_data->clk);
 596
 597         return 0;
 598 }
 599
 600 static int i2c_pnx_controller_resume(struct platform_device *pdev)
 601 {
 602         struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
 603
 604         return clk_enable(alg_data->clk);
 605 }
 606 #else
 607 #define i2c_pnx_controller_suspend      NULL
 608 #define i2c_pnx_controller_resume       NULL
 609 #endif
 610
 611 static int __devinit i2c_pnx_probe(struct platform_device *pdev)
 612 {
 613         unsigned long tmp;
 614         int ret = 0;
 615         struct i2c_pnx_algo_data *alg_data;
 616         unsigned long freq;
 617         struct resource *res;
 618         u32 speed = I2C_PNX_SPEED_KHZ_DEFAULT * 1000;
 619
 620         alg_data = kzalloc(sizeof(*alg_data), GFP_KERNEL);
 621         if (!alg_data) {
 622                 ret = -ENOMEM;
 623                 goto err_kzalloc;
 624         }
 625
 626         platform_set_drvdata(pdev, alg_data);
 627
 628         alg_data->adapter.dev.parent = &pdev->dev;
 629         alg_data->adapter.algo = &pnx_algorithm;
 630         alg_data->adapter.algo_data = alg_data;
 631         alg_data->adapter.nr = pdev->id;
 632
 633         alg_data->timeout = I2C_PNX_TIMEOUT_DEFAULT;
 634 #ifdef CONFIG_OF
 635         alg_data->adapter.dev.of_node = of_node_get(pdev->dev.of_node);
 636         if (pdev->dev.of_node) {
 637                 of_property_read_u32(pdev->dev.of_node, "clock-frequency",
 638                                      &speed);
 639                 /*
 640                  * At this point, it is planned to add an OF timeout property.
 641                  * As soon as there is a consensus about how to call and handle
 642                  * this, sth. like the following can be put here:
 643                  *
 644                  * of_property_read_u32(pdev->dev.of_node, "timeout",
 645                  *                      &alg_data->timeout);
 646                  */
 647         }
 648 #endif
 649         alg_data->clk = clk_get(&pdev->dev, NULL);
 650         if (IS_ERR(alg_data->clk)) {
 651                 ret = PTR_ERR(alg_data->clk);
 652                 goto out_drvdata;
 653         }
 654
 655         init_timer(&alg_data->mif.timer);
 656         alg_data->mif.timer.function = i2c_pnx_timeout;
 657         alg_data->mif.timer.data = (unsigned long)alg_data;
 658
 659         snprintf(alg_data->adapter.name, sizeof(alg_data->adapter.name),
 660                  "%s", pdev->name);
 661
 662         /* Register I/O resource */
 663         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 664         if (!res) {
 665                 dev_err(&pdev->dev, "Unable to get mem resource.\n");
 666                 ret = -EBUSY;
 667                 goto out_clkget;
 668         }
 669         if (!request_mem_region(res->start, I2C_PNX_REGION_SIZE,
 670                                 pdev->name)) {
 671                 dev_err(&pdev->dev,
 672                        "I/O region 0x%08x for I2C already in use.\n",
 673                        res->start);
 674                 ret = -ENOMEM;
 675                 goto out_clkget;
 676         }
 677
 678         alg_data->base = res->start;
 679         alg_data->ioaddr = ioremap(res->start, I2C_PNX_REGION_SIZE);
 680         if (!alg_data->ioaddr) {
 681                 dev_err(&pdev->dev, "Couldn't ioremap I2C I/O region\n");
 682                 ret = -ENOMEM;
 683                 goto out_release;
 684         }
 685
 686         ret = clk_enable(alg_data->clk);
 687         if (ret)
 688                 goto out_unmap;
 689
 690         freq = clk_get_rate(alg_data->clk);
 691
 692         /*
 693          * Clock Divisor High This value is the number of system clocks
 694          * the serial clock (SCL) will be high.
 695          * For example, if the system clock period is 50 ns and the maximum
 696          * desired serial period is 10000 ns (100 kHz), then CLKHI would be
 697          * set to 0.5*(f_sys/f_i2c)-2=0.5*(20e6/100e3)-2=98. The actual value
 698          * programmed into CLKHI will vary from this slightly due to
 699          * variations in the output pad's rise and fall times as well as
 700          * the deglitching filter length.
 701          */
 702
 703         tmp = (freq / speed) / 2 - 2;
 704         if (tmp > 0x3FF)
 705                 tmp = 0x3FF;
 706         iowrite32(tmp, I2C_REG_CKH(alg_data));
 707         iowrite32(tmp, I2C_REG_CKL(alg_data));
 708
 709         iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data));
 710         if (wait_reset(alg_data)) {
 711                 ret = -ENODEV;
 712                 goto out_clock;
 713         }
 714         init_completion(&alg_data->mif.complete);
 715
 716         alg_data->irq = platform_get_irq(pdev, 0);
 717         if (alg_data->irq < 0) {
 718                 dev_err(&pdev->dev, "Failed to get IRQ from platform resource\n");
 719                 goto out_irq;
 720         }
 721         ret = request_irq(alg_data->irq, i2c_pnx_interrupt,
 722                         0, pdev->name, alg_data);
 723         if (ret)
 724                 goto out_clock;
 725
 726         /* Register this adapter with the I2C subsystem */
 727         ret = i2c_add_numbered_adapter(&alg_data->adapter);
 728         if (ret < 0) {
 729                 dev_err(&pdev->dev, "I2C: Failed to add bus\n");
 730                 goto out_irq;
 731         }
 732
 733         of_i2c_register_devices(&alg_data->adapter);
 734
 735         dev_dbg(&pdev->dev, "%s: Master at %#8x, irq %d.\n",
 736                 alg_data->adapter.name, res->start, alg_data->irq);
 737
 738         return 0;
 739
 740 out_irq:
 741         free_irq(alg_data->irq, alg_data);
 742 out_clock:
 743         clk_disable(alg_data->clk);
 744 out_unmap:
 745         iounmap(alg_data->ioaddr);
 746 out_release:
 747         release_mem_region(res->start, I2C_PNX_REGION_SIZE);
 748 out_clkget:
 749         clk_put(alg_data->clk);
 750 out_drvdata:
 751         kfree(alg_data);
 752 err_kzalloc:
 753         platform_set_drvdata(pdev, NULL);
 754         return ret;
 755 }
 756
 757 static int __devexit i2c_pnx_remove(struct platform_device *pdev)
 758 {
 759         struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
 760
 761         free_irq(alg_data->irq, alg_data);
 762         i2c_del_adapter(&alg_data->adapter);
 763         clk_disable(alg_data->clk);
 764         iounmap(alg_data->ioaddr);
 765         release_mem_region(alg_data->base, I2C_PNX_REGION_SIZE);
 766         clk_put(alg_data->clk);
 767         kfree(alg_data);
 768         platform_set_drvdata(pdev, NULL);
 769
 770         return 0;
 771 }
 772
 773 #ifdef CONFIG_OF
 774 static const struct of_device_id i2c_pnx_of_match[] = {
 775         { .compatible = "nxp,pnx-i2c" },
 776         { },
 777 };
 778 MODULE_DEVICE_TABLE(of, i2c_pnx_of_match);
 779 #endif
 780
 781 static struct platform_driver i2c_pnx_driver = {
 782         .driver = {
 783                 .name = "pnx-i2c",
 784                 .owner = THIS_MODULE,
 785                 .of_match_table = of_match_ptr(i2c_pnx_of_match),
 786         },
 787         .probe = i2c_pnx_probe,
 788         .remove = __devexit_p(i2c_pnx_remove),
 789         .suspend = i2c_pnx_controller_suspend,
 790         .resume = i2c_pnx_controller_resume,
 791 };
 792
 793 static int __init i2c_adap_pnx_init(void)
 794 {
 795         return platform_driver_register(&i2c_pnx_driver);
 796 }
 797
 798 static void __exit i2c_adap_pnx_exit(void)
 799 {
 800         platform_driver_unregister(&i2c_pnx_driver);
 801 }
 802
 803 MODULE_AUTHOR("Vitaly Wool, Dennis Kovalev <source@mvista.com>");
 804 MODULE_DESCRIPTION("I2C driver for Philips IP3204-based I2C busses");
 805 MODULE_LICENSE("GPL");
 806 MODULE_ALIAS("platform:pnx-i2c");
 807
 808 /* We need to make sure I2C is initialized before USB */
 809 subsys_initcall(i2c_adap_pnx_init);
 810 module_exit(i2c_adap_pnx_exit);