4 * I2C adapter for the PXA I2C bus access.
6 * Copyright (C) 2002 Intrinsyc Software Inc.
7 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * Apr 2002: Initial version [CS]
15 * Jun 2002: Properly seperated algo/adap [FB]
16 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
17 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
18 * Sep 2004: Major rework to ensure efficient bus handling [RMK]
19 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
20 * Feb 2005: Rework slave mode handling [RMK]
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/i2c-id.h>
26 #include <linux/init.h>
27 #include <linux/time.h>
28 #include <linux/sched.h>
29 #include <linux/delay.h>
30 #include <linux/errno.h>
31 #include <linux/interrupt.h>
32 #include <linux/i2c-pxa.h>
33 #include <linux/platform_device.h>
34 #include <linux/err.h>
35 #include <linux/clk.h>
37 #include <mach/hardware.h>
43 * I2C registers and bit definitions
51 #define ICR_START (1 << 0) /* start bit */
52 #define ICR_STOP (1 << 1) /* stop bit */
53 #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
54 #define ICR_TB (1 << 3) /* transfer byte bit */
55 #define ICR_MA (1 << 4) /* master abort */
56 #define ICR_SCLE (1 << 5) /* master clock enable */
57 #define ICR_IUE (1 << 6) /* unit enable */
58 #define ICR_GCD (1 << 7) /* general call disable */
59 #define ICR_ITEIE (1 << 8) /* enable tx interrupts */
60 #define ICR_IRFIE (1 << 9) /* enable rx interrupts */
61 #define ICR_BEIE (1 << 10) /* enable bus error ints */
62 #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
63 #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
64 #define ICR_SADIE (1 << 13) /* slave address detected int enable */
65 #define ICR_UR (1 << 14) /* unit reset */
66 #define ICR_FM (1 << 15) /* fast mode */
68 #define ISR_RWM (1 << 0) /* read/write mode */
69 #define ISR_ACKNAK (1 << 1) /* ack/nak status */
70 #define ISR_UB (1 << 2) /* unit busy */
71 #define ISR_IBB (1 << 3) /* bus busy */
72 #define ISR_SSD (1 << 4) /* slave stop detected */
73 #define ISR_ALD (1 << 5) /* arbitration loss detected */
74 #define ISR_ITE (1 << 6) /* tx buffer empty */
75 #define ISR_IRF (1 << 7) /* rx buffer full */
76 #define ISR_GCAD (1 << 8) /* general call address detected */
77 #define ISR_SAD (1 << 9) /* slave address detected */
78 #define ISR_BED (1 << 10) /* bus error no ACK/NAK */
82 wait_queue_head_t wait
;
87 unsigned int slave_addr
;
89 struct i2c_adapter adap
;
91 #ifdef CONFIG_I2C_PXA_SLAVE
92 struct i2c_slave_client
*slave
;
95 unsigned int irqlogidx
;
99 void __iomem
*reg_base
;
100 unsigned int reg_shift
;
102 unsigned long iobase
;
103 unsigned long iosize
;
106 unsigned int use_pio
:1;
107 unsigned int fast_mode
:1;
110 #define _IBMR(i2c) ((i2c)->reg_base + (0x0 << (i2c)->reg_shift))
111 #define _IDBR(i2c) ((i2c)->reg_base + (0x4 << (i2c)->reg_shift))
112 #define _ICR(i2c) ((i2c)->reg_base + (0x8 << (i2c)->reg_shift))
113 #define _ISR(i2c) ((i2c)->reg_base + (0xc << (i2c)->reg_shift))
114 #define _ISAR(i2c) ((i2c)->reg_base + (0x10 << (i2c)->reg_shift))
117 * I2C Slave mode address
119 #define I2C_PXA_SLAVE_ADDR 0x1
128 #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u }
131 decode_bits(const char *prefix
, const struct bits
*bits
, int num
, u32 val
)
133 printk("%s %08x: ", prefix
, val
);
135 const char *str
= val
& bits
->mask
? bits
->set
: bits
->unset
;
142 static const struct bits isr_bits
[] = {
143 PXA_BIT(ISR_RWM
, "RX", "TX"),
144 PXA_BIT(ISR_ACKNAK
, "NAK", "ACK"),
145 PXA_BIT(ISR_UB
, "Bsy", "Rdy"),
146 PXA_BIT(ISR_IBB
, "BusBsy", "BusRdy"),
147 PXA_BIT(ISR_SSD
, "SlaveStop", NULL
),
148 PXA_BIT(ISR_ALD
, "ALD", NULL
),
149 PXA_BIT(ISR_ITE
, "TxEmpty", NULL
),
150 PXA_BIT(ISR_IRF
, "RxFull", NULL
),
151 PXA_BIT(ISR_GCAD
, "GenCall", NULL
),
152 PXA_BIT(ISR_SAD
, "SlaveAddr", NULL
),
153 PXA_BIT(ISR_BED
, "BusErr", NULL
),
156 static void decode_ISR(unsigned int val
)
158 decode_bits(KERN_DEBUG
"ISR", isr_bits
, ARRAY_SIZE(isr_bits
), val
);
162 static const struct bits icr_bits
[] = {
163 PXA_BIT(ICR_START
, "START", NULL
),
164 PXA_BIT(ICR_STOP
, "STOP", NULL
),
165 PXA_BIT(ICR_ACKNAK
, "ACKNAK", NULL
),
166 PXA_BIT(ICR_TB
, "TB", NULL
),
167 PXA_BIT(ICR_MA
, "MA", NULL
),
168 PXA_BIT(ICR_SCLE
, "SCLE", "scle"),
169 PXA_BIT(ICR_IUE
, "IUE", "iue"),
170 PXA_BIT(ICR_GCD
, "GCD", NULL
),
171 PXA_BIT(ICR_ITEIE
, "ITEIE", NULL
),
172 PXA_BIT(ICR_IRFIE
, "IRFIE", NULL
),
173 PXA_BIT(ICR_BEIE
, "BEIE", NULL
),
174 PXA_BIT(ICR_SSDIE
, "SSDIE", NULL
),
175 PXA_BIT(ICR_ALDIE
, "ALDIE", NULL
),
176 PXA_BIT(ICR_SADIE
, "SADIE", NULL
),
177 PXA_BIT(ICR_UR
, "UR", "ur"),
180 #ifdef CONFIG_I2C_PXA_SLAVE
181 static void decode_ICR(unsigned int val
)
183 decode_bits(KERN_DEBUG
"ICR", icr_bits
, ARRAY_SIZE(icr_bits
), val
);
188 static unsigned int i2c_debug
= DEBUG
;
190 static void i2c_pxa_show_state(struct pxa_i2c
*i2c
, int lno
, const char *fname
)
192 dev_dbg(&i2c
->adap
.dev
, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname
, lno
,
193 readl(_ISR(i2c
)), readl(_ICR(i2c
)), readl(_IBMR(i2c
)));
196 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
200 #define show_state(i2c) do { } while (0)
201 #define decode_ISR(val) do { } while (0)
202 #define decode_ICR(val) do { } while (0)
205 #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0)
207 static void i2c_pxa_master_complete(struct pxa_i2c
*i2c
, int ret
);
208 static irqreturn_t
i2c_pxa_handler(int this_irq
, void *dev_id
);
210 static void i2c_pxa_scream_blue_murder(struct pxa_i2c
*i2c
, const char *why
)
213 printk("i2c: error: %s\n", why
);
214 printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
215 i2c
->msg_num
, i2c
->msg_idx
, i2c
->msg_ptr
);
216 printk("i2c: ICR: %08x ISR: %08x\n"
217 "i2c: log: ", readl(_ICR(i2c
)), readl(_ISR(i2c
)));
218 for (i
= 0; i
< i2c
->irqlogidx
; i
++)
219 printk("[%08x:%08x] ", i2c
->isrlog
[i
], i2c
->icrlog
[i
]);
223 static inline int i2c_pxa_is_slavemode(struct pxa_i2c
*i2c
)
225 return !(readl(_ICR(i2c
)) & ICR_SCLE
);
228 static void i2c_pxa_abort(struct pxa_i2c
*i2c
)
232 if (i2c_pxa_is_slavemode(i2c
)) {
233 dev_dbg(&i2c
->adap
.dev
, "%s: called in slave mode\n", __func__
);
237 while ((i
> 0) && (readl(_IBMR(i2c
)) & 0x1) == 0) {
238 unsigned long icr
= readl(_ICR(i2c
));
241 icr
|= ICR_ACKNAK
| ICR_STOP
| ICR_TB
;
243 writel(icr
, _ICR(i2c
));
251 writel(readl(_ICR(i2c
)) & ~(ICR_MA
| ICR_START
| ICR_STOP
),
255 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c
*i2c
)
257 int timeout
= DEF_TIMEOUT
;
259 while (timeout
-- && readl(_ISR(i2c
)) & (ISR_IBB
| ISR_UB
)) {
260 if ((readl(_ISR(i2c
)) & ISR_SAD
) != 0)
270 return timeout
<= 0 ? I2C_RETRY
: 0;
273 static int i2c_pxa_wait_master(struct pxa_i2c
*i2c
)
275 unsigned long timeout
= jiffies
+ HZ
*4;
277 while (time_before(jiffies
, timeout
)) {
279 dev_dbg(&i2c
->adap
.dev
, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
280 __func__
, (long)jiffies
, readl(_ISR(i2c
)), readl(_ICR(i2c
)), readl(_IBMR(i2c
)));
282 if (readl(_ISR(i2c
)) & ISR_SAD
) {
284 dev_dbg(&i2c
->adap
.dev
, "%s: Slave detected\n", __func__
);
288 /* wait for unit and bus being not busy, and we also do a
289 * quick check of the i2c lines themselves to ensure they've
292 if ((readl(_ISR(i2c
)) & (ISR_UB
| ISR_IBB
)) == 0 && readl(_IBMR(i2c
)) == 3) {
294 dev_dbg(&i2c
->adap
.dev
, "%s: done\n", __func__
);
302 dev_dbg(&i2c
->adap
.dev
, "%s: did not free\n", __func__
);
307 static int i2c_pxa_set_master(struct pxa_i2c
*i2c
)
310 dev_dbg(&i2c
->adap
.dev
, "setting to bus master\n");
312 if ((readl(_ISR(i2c
)) & (ISR_UB
| ISR_IBB
)) != 0) {
313 dev_dbg(&i2c
->adap
.dev
, "%s: unit is busy\n", __func__
);
314 if (!i2c_pxa_wait_master(i2c
)) {
315 dev_dbg(&i2c
->adap
.dev
, "%s: error: unit busy\n", __func__
);
320 writel(readl(_ICR(i2c
)) | ICR_SCLE
, _ICR(i2c
));
324 #ifdef CONFIG_I2C_PXA_SLAVE
325 static int i2c_pxa_wait_slave(struct pxa_i2c
*i2c
)
327 unsigned long timeout
= jiffies
+ HZ
*1;
333 while (time_before(jiffies
, timeout
)) {
335 dev_dbg(&i2c
->adap
.dev
, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
336 __func__
, (long)jiffies
, readl(_ISR(i2c
)), readl(_ICR(i2c
)), readl(_IBMR(i2c
)));
338 if ((readl(_ISR(i2c
)) & (ISR_UB
|ISR_IBB
)) == 0 ||
339 (readl(_ISR(i2c
)) & ISR_SAD
) != 0 ||
340 (readl(_ICR(i2c
)) & ICR_SCLE
) == 0) {
342 dev_dbg(&i2c
->adap
.dev
, "%s: done\n", __func__
);
350 dev_dbg(&i2c
->adap
.dev
, "%s: did not free\n", __func__
);
355 * clear the hold on the bus, and take of anything else
356 * that has been configured
358 static void i2c_pxa_set_slave(struct pxa_i2c
*i2c
, int errcode
)
363 udelay(100); /* simple delay */
365 /* we need to wait for the stop condition to end */
367 /* if we where in stop, then clear... */
368 if (readl(_ICR(i2c
)) & ICR_STOP
) {
370 writel(readl(_ICR(i2c
)) & ~ICR_STOP
, _ICR(i2c
));
373 if (!i2c_pxa_wait_slave(i2c
)) {
374 dev_err(&i2c
->adap
.dev
, "%s: wait timedout\n",
380 writel(readl(_ICR(i2c
)) & ~(ICR_STOP
|ICR_ACKNAK
|ICR_MA
), _ICR(i2c
));
381 writel(readl(_ICR(i2c
)) & ~ICR_SCLE
, _ICR(i2c
));
384 dev_dbg(&i2c
->adap
.dev
, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c
)), readl(_ISR(i2c
)));
385 decode_ICR(readl(_ICR(i2c
)));
389 #define i2c_pxa_set_slave(i2c, err) do { } while (0)
392 static void i2c_pxa_reset(struct pxa_i2c
*i2c
)
394 pr_debug("Resetting I2C Controller Unit\n");
396 /* abort any transfer currently under way */
399 /* reset according to 9.8 */
400 writel(ICR_UR
, _ICR(i2c
));
401 writel(I2C_ISR_INIT
, _ISR(i2c
));
402 writel(readl(_ICR(i2c
)) & ~ICR_UR
, _ICR(i2c
));
404 writel(i2c
->slave_addr
, _ISAR(i2c
));
406 /* set control register values */
407 writel(I2C_ICR_INIT
| (i2c
->fast_mode
? ICR_FM
: 0), _ICR(i2c
));
409 #ifdef CONFIG_I2C_PXA_SLAVE
410 dev_info(&i2c
->adap
.dev
, "Enabling slave mode\n");
411 writel(readl(_ICR(i2c
)) | ICR_SADIE
| ICR_ALDIE
| ICR_SSDIE
, _ICR(i2c
));
414 i2c_pxa_set_slave(i2c
, 0);
417 writel(readl(_ICR(i2c
)) | ICR_IUE
, _ICR(i2c
));
422 #ifdef CONFIG_I2C_PXA_SLAVE
427 static void i2c_pxa_slave_txempty(struct pxa_i2c
*i2c
, u32 isr
)
430 /* what should we do here? */
434 if (i2c
->slave
!= NULL
)
435 ret
= i2c
->slave
->read(i2c
->slave
->data
);
437 writel(ret
, _IDBR(i2c
));
438 writel(readl(_ICR(i2c
)) | ICR_TB
, _ICR(i2c
)); /* allow next byte */
442 static void i2c_pxa_slave_rxfull(struct pxa_i2c
*i2c
, u32 isr
)
444 unsigned int byte
= readl(_IDBR(i2c
));
446 if (i2c
->slave
!= NULL
)
447 i2c
->slave
->write(i2c
->slave
->data
, byte
);
449 writel(readl(_ICR(i2c
)) | ICR_TB
, _ICR(i2c
));
452 static void i2c_pxa_slave_start(struct pxa_i2c
*i2c
, u32 isr
)
457 dev_dbg(&i2c
->adap
.dev
, "SAD, mode is slave-%cx\n",
458 (isr
& ISR_RWM
) ? 'r' : 't');
460 if (i2c
->slave
!= NULL
)
461 i2c
->slave
->event(i2c
->slave
->data
,
462 (isr
& ISR_RWM
) ? I2C_SLAVE_EVENT_START_READ
: I2C_SLAVE_EVENT_START_WRITE
);
465 * slave could interrupt in the middle of us generating a
466 * start condition... if this happens, we'd better back off
467 * and stop holding the poor thing up
469 writel(readl(_ICR(i2c
)) & ~(ICR_START
|ICR_STOP
), _ICR(i2c
));
470 writel(readl(_ICR(i2c
)) | ICR_TB
, _ICR(i2c
));
475 if ((readl(_IBMR(i2c
)) & 2) == 2)
481 dev_err(&i2c
->adap
.dev
, "timeout waiting for SCL high\n");
486 writel(readl(_ICR(i2c
)) & ~ICR_SCLE
, _ICR(i2c
));
489 static void i2c_pxa_slave_stop(struct pxa_i2c
*i2c
)
492 dev_dbg(&i2c
->adap
.dev
, "ISR: SSD (Slave Stop)\n");
494 if (i2c
->slave
!= NULL
)
495 i2c
->slave
->event(i2c
->slave
->data
, I2C_SLAVE_EVENT_STOP
);
498 dev_dbg(&i2c
->adap
.dev
, "ISR: SSD (Slave Stop) acked\n");
501 * If we have a master-mode message waiting,
502 * kick it off now that the slave has completed.
505 i2c_pxa_master_complete(i2c
, I2C_RETRY
);
508 static void i2c_pxa_slave_txempty(struct pxa_i2c
*i2c
, u32 isr
)
511 /* what should we do here? */
513 writel(0, _IDBR(i2c
));
514 writel(readl(_ICR(i2c
)) | ICR_TB
, _ICR(i2c
));
518 static void i2c_pxa_slave_rxfull(struct pxa_i2c
*i2c
, u32 isr
)
520 writel(readl(_ICR(i2c
)) | ICR_TB
| ICR_ACKNAK
, _ICR(i2c
));
523 static void i2c_pxa_slave_start(struct pxa_i2c
*i2c
, u32 isr
)
528 * slave could interrupt in the middle of us generating a
529 * start condition... if this happens, we'd better back off
530 * and stop holding the poor thing up
532 writel(readl(_ICR(i2c
)) & ~(ICR_START
|ICR_STOP
), _ICR(i2c
));
533 writel(readl(_ICR(i2c
)) | ICR_TB
| ICR_ACKNAK
, _ICR(i2c
));
538 if ((readl(_IBMR(i2c
)) & 2) == 2)
544 dev_err(&i2c
->adap
.dev
, "timeout waiting for SCL high\n");
549 writel(readl(_ICR(i2c
)) & ~ICR_SCLE
, _ICR(i2c
));
552 static void i2c_pxa_slave_stop(struct pxa_i2c
*i2c
)
555 i2c_pxa_master_complete(i2c
, I2C_RETRY
);
560 * PXA I2C Master mode
563 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg
*msg
)
565 unsigned int addr
= (msg
->addr
& 0x7f) << 1;
567 if (msg
->flags
& I2C_M_RD
)
573 static inline void i2c_pxa_start_message(struct pxa_i2c
*i2c
)
578 * Step 1: target slave address into IDBR
580 writel(i2c_pxa_addr_byte(i2c
->msg
), _IDBR(i2c
));
583 * Step 2: initiate the write.
585 icr
= readl(_ICR(i2c
)) & ~(ICR_STOP
| ICR_ALDIE
);
586 writel(icr
| ICR_START
| ICR_TB
, _ICR(i2c
));
589 static inline void i2c_pxa_stop_message(struct pxa_i2c
*i2c
)
594 * Clear the STOP and ACK flags
596 icr
= readl(_ICR(i2c
));
597 icr
&= ~(ICR_STOP
| ICR_ACKNAK
);
598 writel(icr
, _ICR(i2c
));
601 static int i2c_pxa_pio_set_master(struct pxa_i2c
*i2c
)
603 /* make timeout the same as for interrupt based functions */
604 long timeout
= 2 * DEF_TIMEOUT
;
607 * Wait for the bus to become free.
609 while (timeout
-- && readl(_ISR(i2c
)) & (ISR_IBB
| ISR_UB
)) {
616 dev_err(&i2c
->adap
.dev
,
617 "i2c_pxa: timeout waiting for bus free\n");
624 writel(readl(_ICR(i2c
)) | ICR_SCLE
, _ICR(i2c
));
629 static int i2c_pxa_do_pio_xfer(struct pxa_i2c
*i2c
,
630 struct i2c_msg
*msg
, int num
)
632 unsigned long timeout
= 500000; /* 5 seconds */
635 ret
= i2c_pxa_pio_set_master(i2c
);
645 i2c_pxa_start_message(i2c
);
647 while (timeout
-- && i2c
->msg_num
> 0) {
648 i2c_pxa_handler(0, i2c
);
652 i2c_pxa_stop_message(i2c
);
655 * We place the return code in i2c->msg_idx.
661 i2c_pxa_scream_blue_murder(i2c
, "timeout");
667 * We are protected by the adapter bus mutex.
669 static int i2c_pxa_do_xfer(struct pxa_i2c
*i2c
, struct i2c_msg
*msg
, int num
)
675 * Wait for the bus to become free.
677 ret
= i2c_pxa_wait_bus_not_busy(i2c
);
679 dev_err(&i2c
->adap
.dev
, "i2c_pxa: timeout waiting for bus free\n");
686 ret
= i2c_pxa_set_master(i2c
);
688 dev_err(&i2c
->adap
.dev
, "i2c_pxa_set_master: error %d\n", ret
);
692 spin_lock_irq(&i2c
->lock
);
700 i2c_pxa_start_message(i2c
);
702 spin_unlock_irq(&i2c
->lock
);
705 * The rest of the processing occurs in the interrupt handler.
707 timeout
= wait_event_timeout(i2c
->wait
, i2c
->msg_num
== 0, HZ
* 5);
708 i2c_pxa_stop_message(i2c
);
711 * We place the return code in i2c->msg_idx.
716 i2c_pxa_scream_blue_murder(i2c
, "timeout");
722 static int i2c_pxa_pio_xfer(struct i2c_adapter
*adap
,
723 struct i2c_msg msgs
[], int num
)
725 struct pxa_i2c
*i2c
= adap
->algo_data
;
728 /* If the I2C controller is disabled we need to reset it
729 (probably due to a suspend/resume destroying state). We do
730 this here as we can then avoid worrying about resuming the
731 controller before its users. */
732 if (!(readl(_ICR(i2c
)) & ICR_IUE
))
735 for (i
= adap
->retries
; i
>= 0; i
--) {
736 ret
= i2c_pxa_do_pio_xfer(i2c
, msgs
, num
);
737 if (ret
!= I2C_RETRY
)
741 dev_dbg(&adap
->dev
, "Retrying transmission\n");
744 i2c_pxa_scream_blue_murder(i2c
, "exhausted retries");
747 i2c_pxa_set_slave(i2c
, ret
);
752 * i2c_pxa_master_complete - complete the message and wake up.
754 static void i2c_pxa_master_complete(struct pxa_i2c
*i2c
, int ret
)
766 static void i2c_pxa_irq_txempty(struct pxa_i2c
*i2c
, u32 isr
)
768 u32 icr
= readl(_ICR(i2c
)) & ~(ICR_START
|ICR_STOP
|ICR_ACKNAK
|ICR_TB
);
772 * If ISR_ALD is set, we lost arbitration.
776 * Do we need to do anything here? The PXA docs
777 * are vague about what happens.
779 i2c_pxa_scream_blue_murder(i2c
, "ALD set");
782 * We ignore this error. We seem to see spurious ALDs
783 * for seemingly no reason. If we handle them as I think
784 * they should, we end up causing an I2C error, which
785 * is painful for some systems.
794 * I2C bus error - either the device NAK'd us, or
795 * something more serious happened. If we were NAK'd
796 * on the initial address phase, we can retry.
798 if (isr
& ISR_ACKNAK
) {
799 if (i2c
->msg_ptr
== 0 && i2c
->msg_idx
== 0)
804 i2c_pxa_master_complete(i2c
, ret
);
805 } else if (isr
& ISR_RWM
) {
807 * Read mode. We have just sent the address byte, and
808 * now we must initiate the transfer.
810 if (i2c
->msg_ptr
== i2c
->msg
->len
- 1 &&
811 i2c
->msg_idx
== i2c
->msg_num
- 1)
812 icr
|= ICR_STOP
| ICR_ACKNAK
;
814 icr
|= ICR_ALDIE
| ICR_TB
;
815 } else if (i2c
->msg_ptr
< i2c
->msg
->len
) {
817 * Write mode. Write the next data byte.
819 writel(i2c
->msg
->buf
[i2c
->msg_ptr
++], _IDBR(i2c
));
821 icr
|= ICR_ALDIE
| ICR_TB
;
824 * If this is the last byte of the last message, send
827 if (i2c
->msg_ptr
== i2c
->msg
->len
&&
828 i2c
->msg_idx
== i2c
->msg_num
- 1)
830 } else if (i2c
->msg_idx
< i2c
->msg_num
- 1) {
832 * Next segment of the message.
839 * If we aren't doing a repeated start and address,
840 * go back and try to send the next byte. Note that
841 * we do not support switching the R/W direction here.
843 if (i2c
->msg
->flags
& I2C_M_NOSTART
)
847 * Write the next address.
849 writel(i2c_pxa_addr_byte(i2c
->msg
), _IDBR(i2c
));
852 * And trigger a repeated start, and send the byte.
855 icr
|= ICR_START
| ICR_TB
;
857 if (i2c
->msg
->len
== 0) {
859 * Device probes have a message length of zero
860 * and need the bus to be reset before it can
865 i2c_pxa_master_complete(i2c
, 0);
868 i2c
->icrlog
[i2c
->irqlogidx
-1] = icr
;
870 writel(icr
, _ICR(i2c
));
874 static void i2c_pxa_irq_rxfull(struct pxa_i2c
*i2c
, u32 isr
)
876 u32 icr
= readl(_ICR(i2c
)) & ~(ICR_START
|ICR_STOP
|ICR_ACKNAK
|ICR_TB
);
881 i2c
->msg
->buf
[i2c
->msg_ptr
++] = readl(_IDBR(i2c
));
883 if (i2c
->msg_ptr
< i2c
->msg
->len
) {
885 * If this is the last byte of the last
886 * message, send a STOP.
888 if (i2c
->msg_ptr
== i2c
->msg
->len
- 1)
889 icr
|= ICR_STOP
| ICR_ACKNAK
;
891 icr
|= ICR_ALDIE
| ICR_TB
;
893 i2c_pxa_master_complete(i2c
, 0);
896 i2c
->icrlog
[i2c
->irqlogidx
-1] = icr
;
898 writel(icr
, _ICR(i2c
));
901 static irqreturn_t
i2c_pxa_handler(int this_irq
, void *dev_id
)
903 struct pxa_i2c
*i2c
= dev_id
;
904 u32 isr
= readl(_ISR(i2c
));
906 if (i2c_debug
> 2 && 0) {
907 dev_dbg(&i2c
->adap
.dev
, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
908 __func__
, isr
, readl(_ICR(i2c
)), readl(_IBMR(i2c
)));
912 if (i2c
->irqlogidx
< ARRAY_SIZE(i2c
->isrlog
))
913 i2c
->isrlog
[i2c
->irqlogidx
++] = isr
;
918 * Always clear all pending IRQs.
920 writel(isr
& (ISR_SSD
|ISR_ALD
|ISR_ITE
|ISR_IRF
|ISR_SAD
|ISR_BED
), _ISR(i2c
));
923 i2c_pxa_slave_start(i2c
, isr
);
925 i2c_pxa_slave_stop(i2c
);
927 if (i2c_pxa_is_slavemode(i2c
)) {
929 i2c_pxa_slave_txempty(i2c
, isr
);
931 i2c_pxa_slave_rxfull(i2c
, isr
);
932 } else if (i2c
->msg
) {
934 i2c_pxa_irq_txempty(i2c
, isr
);
936 i2c_pxa_irq_rxfull(i2c
, isr
);
938 i2c_pxa_scream_blue_murder(i2c
, "spurious irq");
945 static int i2c_pxa_xfer(struct i2c_adapter
*adap
, struct i2c_msg msgs
[], int num
)
947 struct pxa_i2c
*i2c
= adap
->algo_data
;
950 for (i
= adap
->retries
; i
>= 0; i
--) {
951 ret
= i2c_pxa_do_xfer(i2c
, msgs
, num
);
952 if (ret
!= I2C_RETRY
)
956 dev_dbg(&adap
->dev
, "Retrying transmission\n");
959 i2c_pxa_scream_blue_murder(i2c
, "exhausted retries");
962 i2c_pxa_set_slave(i2c
, ret
);
966 static u32
i2c_pxa_functionality(struct i2c_adapter
*adap
)
968 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
971 static const struct i2c_algorithm i2c_pxa_algorithm
= {
972 .master_xfer
= i2c_pxa_xfer
,
973 .functionality
= i2c_pxa_functionality
,
976 static const struct i2c_algorithm i2c_pxa_pio_algorithm
= {
977 .master_xfer
= i2c_pxa_pio_xfer
,
978 .functionality
= i2c_pxa_functionality
,
981 #define res_len(r) ((r)->end - (r)->start + 1)
982 static int i2c_pxa_probe(struct platform_device
*dev
)
985 struct resource
*res
;
986 struct i2c_pxa_platform_data
*plat
= dev
->dev
.platform_data
;
990 res
= platform_get_resource(dev
, IORESOURCE_MEM
, 0);
991 irq
= platform_get_irq(dev
, 0);
992 if (res
== NULL
|| irq
< 0)
995 if (!request_mem_region(res
->start
, res_len(res
), res
->name
))
998 i2c
= kzalloc(sizeof(struct pxa_i2c
), GFP_KERNEL
);
1004 i2c
->adap
.owner
= THIS_MODULE
;
1005 i2c
->adap
.retries
= 5;
1007 spin_lock_init(&i2c
->lock
);
1008 init_waitqueue_head(&i2c
->wait
);
1011 * If "dev->id" is negative we consider it as zero.
1012 * The reason to do so is to avoid sysfs names that only make
1013 * sense when there are multiple adapters.
1015 i2c
->adap
.nr
= dev
->id
!= -1 ? dev
->id
: 0;
1016 snprintf(i2c
->adap
.name
, sizeof(i2c
->adap
.name
), "pxa_i2c-i2c.%u",
1019 i2c
->clk
= clk_get(&dev
->dev
, NULL
);
1020 if (IS_ERR(i2c
->clk
)) {
1021 ret
= PTR_ERR(i2c
->clk
);
1025 i2c
->reg_base
= ioremap(res
->start
, res_len(res
));
1026 if (!i2c
->reg_base
) {
1030 i2c
->reg_shift
= (cpu_is_pxa3xx() && (dev
->id
== 1)) ? 0 : 1;
1032 i2c
->iobase
= res
->start
;
1033 i2c
->iosize
= res_len(res
);
1037 i2c
->slave_addr
= I2C_PXA_SLAVE_ADDR
;
1039 #ifdef CONFIG_I2C_PXA_SLAVE
1041 i2c
->slave_addr
= plat
->slave_addr
;
1042 i2c
->slave
= plat
->slave
;
1046 clk_enable(i2c
->clk
);
1049 i2c
->adap
.class = plat
->class;
1050 i2c
->use_pio
= plat
->use_pio
;
1051 i2c
->fast_mode
= plat
->fast_mode
;
1055 i2c
->adap
.algo
= &i2c_pxa_pio_algorithm
;
1057 i2c
->adap
.algo
= &i2c_pxa_algorithm
;
1058 ret
= request_irq(irq
, i2c_pxa_handler
, IRQF_DISABLED
,
1059 i2c
->adap
.name
, i2c
);
1066 i2c
->adap
.algo_data
= i2c
;
1067 i2c
->adap
.dev
.parent
= &dev
->dev
;
1069 ret
= i2c_add_numbered_adapter(&i2c
->adap
);
1071 printk(KERN_INFO
"I2C: Failed to add bus\n");
1075 platform_set_drvdata(dev
, i2c
);
1077 #ifdef CONFIG_I2C_PXA_SLAVE
1078 printk(KERN_INFO
"I2C: %s: PXA I2C adapter, slave address %d\n",
1079 i2c
->adap
.dev
.bus_id
, i2c
->slave_addr
);
1081 printk(KERN_INFO
"I2C: %s: PXA I2C adapter\n",
1082 i2c
->adap
.dev
.bus_id
);
1090 clk_disable(i2c
->clk
);
1091 iounmap(i2c
->reg_base
);
1097 release_mem_region(res
->start
, res_len(res
));
1101 static int __exit
i2c_pxa_remove(struct platform_device
*dev
)
1103 struct pxa_i2c
*i2c
= platform_get_drvdata(dev
);
1105 platform_set_drvdata(dev
, NULL
);
1107 i2c_del_adapter(&i2c
->adap
);
1109 free_irq(i2c
->irq
, i2c
);
1111 clk_disable(i2c
->clk
);
1114 iounmap(i2c
->reg_base
);
1115 release_mem_region(i2c
->iobase
, i2c
->iosize
);
1122 static int i2c_pxa_suspend_late(struct platform_device
*dev
, pm_message_t state
)
1124 struct pxa_i2c
*i2c
= platform_get_drvdata(dev
);
1125 clk_disable(i2c
->clk
);
1129 static int i2c_pxa_resume_early(struct platform_device
*dev
)
1131 struct pxa_i2c
*i2c
= platform_get_drvdata(dev
);
1133 clk_enable(i2c
->clk
);
1139 #define i2c_pxa_suspend_late NULL
1140 #define i2c_pxa_resume_early NULL
1143 static struct platform_driver i2c_pxa_driver
= {
1144 .probe
= i2c_pxa_probe
,
1145 .remove
= __exit_p(i2c_pxa_remove
),
1146 .suspend_late
= i2c_pxa_suspend_late
,
1147 .resume_early
= i2c_pxa_resume_early
,
1149 .name
= "pxa2xx-i2c",
1150 .owner
= THIS_MODULE
,
1154 static int __init
i2c_adap_pxa_init(void)
1156 return platform_driver_register(&i2c_pxa_driver
);
1159 static void __exit
i2c_adap_pxa_exit(void)
1161 platform_driver_unregister(&i2c_pxa_driver
);
1164 MODULE_LICENSE("GPL");
1165 MODULE_ALIAS("platform:pxa2xx-i2c");
1167 subsys_initcall(i2c_adap_pxa_init
);
1168 module_exit(i2c_adap_pxa_exit
);