4 * I2C adapter for the PXA I2C bus access.
6 * Copyright (C) 2002 Intrinsyc Software Inc.
7 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * Apr 2002: Initial version [CS]
15 * Jun 2002: Properly seperated algo/adap [FB]
16 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
17 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
18 * Sep 2004: Major rework to ensure efficient bus handling [RMK]
19 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
20 * Feb 2005: Rework slave mode handling [RMK]
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/i2c-id.h>
26 #include <linux/init.h>
27 #include <linux/time.h>
28 #include <linux/sched.h>
29 #include <linux/delay.h>
30 #include <linux/errno.h>
31 #include <linux/interrupt.h>
32 #include <linux/i2c-pxa.h>
33 #include <linux/platform_device.h>
34 #include <linux/err.h>
35 #include <linux/clk.h>
37 #include <mach/hardware.h>
43 * I2C registers and bit definitions
51 #define ICR_START (1 << 0) /* start bit */
52 #define ICR_STOP (1 << 1) /* stop bit */
53 #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
54 #define ICR_TB (1 << 3) /* transfer byte bit */
55 #define ICR_MA (1 << 4) /* master abort */
56 #define ICR_SCLE (1 << 5) /* master clock enable */
57 #define ICR_IUE (1 << 6) /* unit enable */
58 #define ICR_GCD (1 << 7) /* general call disable */
59 #define ICR_ITEIE (1 << 8) /* enable tx interrupts */
60 #define ICR_IRFIE (1 << 9) /* enable rx interrupts */
61 #define ICR_BEIE (1 << 10) /* enable bus error ints */
62 #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
63 #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
64 #define ICR_SADIE (1 << 13) /* slave address detected int enable */
65 #define ICR_UR (1 << 14) /* unit reset */
66 #define ICR_FM (1 << 15) /* fast mode */
68 #define ISR_RWM (1 << 0) /* read/write mode */
69 #define ISR_ACKNAK (1 << 1) /* ack/nak status */
70 #define ISR_UB (1 << 2) /* unit busy */
71 #define ISR_IBB (1 << 3) /* bus busy */
72 #define ISR_SSD (1 << 4) /* slave stop detected */
73 #define ISR_ALD (1 << 5) /* arbitration loss detected */
74 #define ISR_ITE (1 << 6) /* tx buffer empty */
75 #define ISR_IRF (1 << 7) /* rx buffer full */
76 #define ISR_GCAD (1 << 8) /* general call address detected */
77 #define ISR_SAD (1 << 9) /* slave address detected */
78 #define ISR_BED (1 << 10) /* bus error no ACK/NAK */
82 wait_queue_head_t wait
;
87 unsigned int slave_addr
;
89 struct i2c_adapter adap
;
91 #ifdef CONFIG_I2C_PXA_SLAVE
92 struct i2c_slave_client
*slave
;
95 unsigned int irqlogidx
;
99 void __iomem
*reg_base
;
100 unsigned int reg_shift
;
102 unsigned long iobase
;
103 unsigned long iosize
;
106 unsigned int use_pio
:1;
107 unsigned int fast_mode
:1;
110 #define _IBMR(i2c) ((i2c)->reg_base + (0x0 << (i2c)->reg_shift))
111 #define _IDBR(i2c) ((i2c)->reg_base + (0x4 << (i2c)->reg_shift))
112 #define _ICR(i2c) ((i2c)->reg_base + (0x8 << (i2c)->reg_shift))
113 #define _ISR(i2c) ((i2c)->reg_base + (0xc << (i2c)->reg_shift))
114 #define _ISAR(i2c) ((i2c)->reg_base + (0x10 << (i2c)->reg_shift))
117 * I2C Slave mode address
119 #define I2C_PXA_SLAVE_ADDR 0x1
128 #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u }
131 decode_bits(const char *prefix
, const struct bits
*bits
, int num
, u32 val
)
133 printk("%s %08x: ", prefix
, val
);
135 const char *str
= val
& bits
->mask
? bits
->set
: bits
->unset
;
142 static const struct bits isr_bits
[] = {
143 PXA_BIT(ISR_RWM
, "RX", "TX"),
144 PXA_BIT(ISR_ACKNAK
, "NAK", "ACK"),
145 PXA_BIT(ISR_UB
, "Bsy", "Rdy"),
146 PXA_BIT(ISR_IBB
, "BusBsy", "BusRdy"),
147 PXA_BIT(ISR_SSD
, "SlaveStop", NULL
),
148 PXA_BIT(ISR_ALD
, "ALD", NULL
),
149 PXA_BIT(ISR_ITE
, "TxEmpty", NULL
),
150 PXA_BIT(ISR_IRF
, "RxFull", NULL
),
151 PXA_BIT(ISR_GCAD
, "GenCall", NULL
),
152 PXA_BIT(ISR_SAD
, "SlaveAddr", NULL
),
153 PXA_BIT(ISR_BED
, "BusErr", NULL
),
156 static void decode_ISR(unsigned int val
)
158 decode_bits(KERN_DEBUG
"ISR", isr_bits
, ARRAY_SIZE(isr_bits
), val
);
162 static const struct bits icr_bits
[] = {
163 PXA_BIT(ICR_START
, "START", NULL
),
164 PXA_BIT(ICR_STOP
, "STOP", NULL
),
165 PXA_BIT(ICR_ACKNAK
, "ACKNAK", NULL
),
166 PXA_BIT(ICR_TB
, "TB", NULL
),
167 PXA_BIT(ICR_MA
, "MA", NULL
),
168 PXA_BIT(ICR_SCLE
, "SCLE", "scle"),
169 PXA_BIT(ICR_IUE
, "IUE", "iue"),
170 PXA_BIT(ICR_GCD
, "GCD", NULL
),
171 PXA_BIT(ICR_ITEIE
, "ITEIE", NULL
),
172 PXA_BIT(ICR_IRFIE
, "IRFIE", NULL
),
173 PXA_BIT(ICR_BEIE
, "BEIE", NULL
),
174 PXA_BIT(ICR_SSDIE
, "SSDIE", NULL
),
175 PXA_BIT(ICR_ALDIE
, "ALDIE", NULL
),
176 PXA_BIT(ICR_SADIE
, "SADIE", NULL
),
177 PXA_BIT(ICR_UR
, "UR", "ur"),
180 #ifdef CONFIG_I2C_PXA_SLAVE
181 static void decode_ICR(unsigned int val
)
183 decode_bits(KERN_DEBUG
"ICR", icr_bits
, ARRAY_SIZE(icr_bits
), val
);
188 static unsigned int i2c_debug
= DEBUG
;
190 static void i2c_pxa_show_state(struct pxa_i2c
*i2c
, int lno
, const char *fname
)
192 dev_dbg(&i2c
->adap
.dev
, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname
, lno
,
193 readl(_ISR(i2c
)), readl(_ICR(i2c
)), readl(_IBMR(i2c
)));
196 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
200 #define show_state(i2c) do { } while (0)
201 #define decode_ISR(val) do { } while (0)
202 #define decode_ICR(val) do { } while (0)
205 #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0)
207 static void i2c_pxa_master_complete(struct pxa_i2c
*i2c
, int ret
);
208 static irqreturn_t
i2c_pxa_handler(int this_irq
, void *dev_id
);
210 static void i2c_pxa_scream_blue_murder(struct pxa_i2c
*i2c
, const char *why
)
213 printk(KERN_ERR
"i2c: error: %s\n", why
);
214 printk(KERN_ERR
"i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
215 i2c
->msg_num
, i2c
->msg_idx
, i2c
->msg_ptr
);
216 printk(KERN_ERR
"i2c: ICR: %08x ISR: %08x\n",
217 readl(_ICR(i2c
)), readl(_ISR(i2c
)));
218 printk(KERN_DEBUG
"i2c: log: ");
219 for (i
= 0; i
< i2c
->irqlogidx
; i
++)
220 printk("[%08x:%08x] ", i2c
->isrlog
[i
], i2c
->icrlog
[i
]);
224 static inline int i2c_pxa_is_slavemode(struct pxa_i2c
*i2c
)
226 return !(readl(_ICR(i2c
)) & ICR_SCLE
);
229 static void i2c_pxa_abort(struct pxa_i2c
*i2c
)
233 if (i2c_pxa_is_slavemode(i2c
)) {
234 dev_dbg(&i2c
->adap
.dev
, "%s: called in slave mode\n", __func__
);
238 while ((i
> 0) && (readl(_IBMR(i2c
)) & 0x1) == 0) {
239 unsigned long icr
= readl(_ICR(i2c
));
242 icr
|= ICR_ACKNAK
| ICR_STOP
| ICR_TB
;
244 writel(icr
, _ICR(i2c
));
252 writel(readl(_ICR(i2c
)) & ~(ICR_MA
| ICR_START
| ICR_STOP
),
256 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c
*i2c
)
258 int timeout
= DEF_TIMEOUT
;
260 while (timeout
-- && readl(_ISR(i2c
)) & (ISR_IBB
| ISR_UB
)) {
261 if ((readl(_ISR(i2c
)) & ISR_SAD
) != 0)
271 return timeout
< 0 ? I2C_RETRY
: 0;
274 static int i2c_pxa_wait_master(struct pxa_i2c
*i2c
)
276 unsigned long timeout
= jiffies
+ HZ
*4;
278 while (time_before(jiffies
, timeout
)) {
280 dev_dbg(&i2c
->adap
.dev
, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
281 __func__
, (long)jiffies
, readl(_ISR(i2c
)), readl(_ICR(i2c
)), readl(_IBMR(i2c
)));
283 if (readl(_ISR(i2c
)) & ISR_SAD
) {
285 dev_dbg(&i2c
->adap
.dev
, "%s: Slave detected\n", __func__
);
289 /* wait for unit and bus being not busy, and we also do a
290 * quick check of the i2c lines themselves to ensure they've
293 if ((readl(_ISR(i2c
)) & (ISR_UB
| ISR_IBB
)) == 0 && readl(_IBMR(i2c
)) == 3) {
295 dev_dbg(&i2c
->adap
.dev
, "%s: done\n", __func__
);
303 dev_dbg(&i2c
->adap
.dev
, "%s: did not free\n", __func__
);
308 static int i2c_pxa_set_master(struct pxa_i2c
*i2c
)
311 dev_dbg(&i2c
->adap
.dev
, "setting to bus master\n");
313 if ((readl(_ISR(i2c
)) & (ISR_UB
| ISR_IBB
)) != 0) {
314 dev_dbg(&i2c
->adap
.dev
, "%s: unit is busy\n", __func__
);
315 if (!i2c_pxa_wait_master(i2c
)) {
316 dev_dbg(&i2c
->adap
.dev
, "%s: error: unit busy\n", __func__
);
321 writel(readl(_ICR(i2c
)) | ICR_SCLE
, _ICR(i2c
));
325 #ifdef CONFIG_I2C_PXA_SLAVE
326 static int i2c_pxa_wait_slave(struct pxa_i2c
*i2c
)
328 unsigned long timeout
= jiffies
+ HZ
*1;
334 while (time_before(jiffies
, timeout
)) {
336 dev_dbg(&i2c
->adap
.dev
, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
337 __func__
, (long)jiffies
, readl(_ISR(i2c
)), readl(_ICR(i2c
)), readl(_IBMR(i2c
)));
339 if ((readl(_ISR(i2c
)) & (ISR_UB
|ISR_IBB
)) == 0 ||
340 (readl(_ISR(i2c
)) & ISR_SAD
) != 0 ||
341 (readl(_ICR(i2c
)) & ICR_SCLE
) == 0) {
343 dev_dbg(&i2c
->adap
.dev
, "%s: done\n", __func__
);
351 dev_dbg(&i2c
->adap
.dev
, "%s: did not free\n", __func__
);
356 * clear the hold on the bus, and take of anything else
357 * that has been configured
359 static void i2c_pxa_set_slave(struct pxa_i2c
*i2c
, int errcode
)
364 udelay(100); /* simple delay */
366 /* we need to wait for the stop condition to end */
368 /* if we where in stop, then clear... */
369 if (readl(_ICR(i2c
)) & ICR_STOP
) {
371 writel(readl(_ICR(i2c
)) & ~ICR_STOP
, _ICR(i2c
));
374 if (!i2c_pxa_wait_slave(i2c
)) {
375 dev_err(&i2c
->adap
.dev
, "%s: wait timedout\n",
381 writel(readl(_ICR(i2c
)) & ~(ICR_STOP
|ICR_ACKNAK
|ICR_MA
), _ICR(i2c
));
382 writel(readl(_ICR(i2c
)) & ~ICR_SCLE
, _ICR(i2c
));
385 dev_dbg(&i2c
->adap
.dev
, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c
)), readl(_ISR(i2c
)));
386 decode_ICR(readl(_ICR(i2c
)));
390 #define i2c_pxa_set_slave(i2c, err) do { } while (0)
393 static void i2c_pxa_reset(struct pxa_i2c
*i2c
)
395 pr_debug("Resetting I2C Controller Unit\n");
397 /* abort any transfer currently under way */
400 /* reset according to 9.8 */
401 writel(ICR_UR
, _ICR(i2c
));
402 writel(I2C_ISR_INIT
, _ISR(i2c
));
403 writel(readl(_ICR(i2c
)) & ~ICR_UR
, _ICR(i2c
));
405 writel(i2c
->slave_addr
, _ISAR(i2c
));
407 /* set control register values */
408 writel(I2C_ICR_INIT
| (i2c
->fast_mode
? ICR_FM
: 0), _ICR(i2c
));
410 #ifdef CONFIG_I2C_PXA_SLAVE
411 dev_info(&i2c
->adap
.dev
, "Enabling slave mode\n");
412 writel(readl(_ICR(i2c
)) | ICR_SADIE
| ICR_ALDIE
| ICR_SSDIE
, _ICR(i2c
));
415 i2c_pxa_set_slave(i2c
, 0);
418 writel(readl(_ICR(i2c
)) | ICR_IUE
, _ICR(i2c
));
423 #ifdef CONFIG_I2C_PXA_SLAVE
428 static void i2c_pxa_slave_txempty(struct pxa_i2c
*i2c
, u32 isr
)
431 /* what should we do here? */
435 if (i2c
->slave
!= NULL
)
436 ret
= i2c
->slave
->read(i2c
->slave
->data
);
438 writel(ret
, _IDBR(i2c
));
439 writel(readl(_ICR(i2c
)) | ICR_TB
, _ICR(i2c
)); /* allow next byte */
443 static void i2c_pxa_slave_rxfull(struct pxa_i2c
*i2c
, u32 isr
)
445 unsigned int byte
= readl(_IDBR(i2c
));
447 if (i2c
->slave
!= NULL
)
448 i2c
->slave
->write(i2c
->slave
->data
, byte
);
450 writel(readl(_ICR(i2c
)) | ICR_TB
, _ICR(i2c
));
453 static void i2c_pxa_slave_start(struct pxa_i2c
*i2c
, u32 isr
)
458 dev_dbg(&i2c
->adap
.dev
, "SAD, mode is slave-%cx\n",
459 (isr
& ISR_RWM
) ? 'r' : 't');
461 if (i2c
->slave
!= NULL
)
462 i2c
->slave
->event(i2c
->slave
->data
,
463 (isr
& ISR_RWM
) ? I2C_SLAVE_EVENT_START_READ
: I2C_SLAVE_EVENT_START_WRITE
);
466 * slave could interrupt in the middle of us generating a
467 * start condition... if this happens, we'd better back off
468 * and stop holding the poor thing up
470 writel(readl(_ICR(i2c
)) & ~(ICR_START
|ICR_STOP
), _ICR(i2c
));
471 writel(readl(_ICR(i2c
)) | ICR_TB
, _ICR(i2c
));
476 if ((readl(_IBMR(i2c
)) & 2) == 2)
482 dev_err(&i2c
->adap
.dev
, "timeout waiting for SCL high\n");
487 writel(readl(_ICR(i2c
)) & ~ICR_SCLE
, _ICR(i2c
));
490 static void i2c_pxa_slave_stop(struct pxa_i2c
*i2c
)
493 dev_dbg(&i2c
->adap
.dev
, "ISR: SSD (Slave Stop)\n");
495 if (i2c
->slave
!= NULL
)
496 i2c
->slave
->event(i2c
->slave
->data
, I2C_SLAVE_EVENT_STOP
);
499 dev_dbg(&i2c
->adap
.dev
, "ISR: SSD (Slave Stop) acked\n");
502 * If we have a master-mode message waiting,
503 * kick it off now that the slave has completed.
506 i2c_pxa_master_complete(i2c
, I2C_RETRY
);
509 static void i2c_pxa_slave_txempty(struct pxa_i2c
*i2c
, u32 isr
)
512 /* what should we do here? */
514 writel(0, _IDBR(i2c
));
515 writel(readl(_ICR(i2c
)) | ICR_TB
, _ICR(i2c
));
519 static void i2c_pxa_slave_rxfull(struct pxa_i2c
*i2c
, u32 isr
)
521 writel(readl(_ICR(i2c
)) | ICR_TB
| ICR_ACKNAK
, _ICR(i2c
));
524 static void i2c_pxa_slave_start(struct pxa_i2c
*i2c
, u32 isr
)
529 * slave could interrupt in the middle of us generating a
530 * start condition... if this happens, we'd better back off
531 * and stop holding the poor thing up
533 writel(readl(_ICR(i2c
)) & ~(ICR_START
|ICR_STOP
), _ICR(i2c
));
534 writel(readl(_ICR(i2c
)) | ICR_TB
| ICR_ACKNAK
, _ICR(i2c
));
539 if ((readl(_IBMR(i2c
)) & 2) == 2)
545 dev_err(&i2c
->adap
.dev
, "timeout waiting for SCL high\n");
550 writel(readl(_ICR(i2c
)) & ~ICR_SCLE
, _ICR(i2c
));
553 static void i2c_pxa_slave_stop(struct pxa_i2c
*i2c
)
556 i2c_pxa_master_complete(i2c
, I2C_RETRY
);
561 * PXA I2C Master mode
564 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg
*msg
)
566 unsigned int addr
= (msg
->addr
& 0x7f) << 1;
568 if (msg
->flags
& I2C_M_RD
)
574 static inline void i2c_pxa_start_message(struct pxa_i2c
*i2c
)
579 * Step 1: target slave address into IDBR
581 writel(i2c_pxa_addr_byte(i2c
->msg
), _IDBR(i2c
));
584 * Step 2: initiate the write.
586 icr
= readl(_ICR(i2c
)) & ~(ICR_STOP
| ICR_ALDIE
);
587 writel(icr
| ICR_START
| ICR_TB
, _ICR(i2c
));
590 static inline void i2c_pxa_stop_message(struct pxa_i2c
*i2c
)
595 * Clear the STOP and ACK flags
597 icr
= readl(_ICR(i2c
));
598 icr
&= ~(ICR_STOP
| ICR_ACKNAK
);
599 writel(icr
, _ICR(i2c
));
602 static int i2c_pxa_pio_set_master(struct pxa_i2c
*i2c
)
604 /* make timeout the same as for interrupt based functions */
605 long timeout
= 2 * DEF_TIMEOUT
;
608 * Wait for the bus to become free.
610 while (timeout
-- && readl(_ISR(i2c
)) & (ISR_IBB
| ISR_UB
)) {
617 dev_err(&i2c
->adap
.dev
,
618 "i2c_pxa: timeout waiting for bus free\n");
625 writel(readl(_ICR(i2c
)) | ICR_SCLE
, _ICR(i2c
));
630 static int i2c_pxa_do_pio_xfer(struct pxa_i2c
*i2c
,
631 struct i2c_msg
*msg
, int num
)
633 unsigned long timeout
= 500000; /* 5 seconds */
636 ret
= i2c_pxa_pio_set_master(i2c
);
646 i2c_pxa_start_message(i2c
);
648 while (i2c
->msg_num
> 0 && --timeout
) {
649 i2c_pxa_handler(0, i2c
);
653 i2c_pxa_stop_message(i2c
);
656 * We place the return code in i2c->msg_idx.
662 i2c_pxa_scream_blue_murder(i2c
, "timeout");
668 * We are protected by the adapter bus mutex.
670 static int i2c_pxa_do_xfer(struct pxa_i2c
*i2c
, struct i2c_msg
*msg
, int num
)
676 * Wait for the bus to become free.
678 ret
= i2c_pxa_wait_bus_not_busy(i2c
);
680 dev_err(&i2c
->adap
.dev
, "i2c_pxa: timeout waiting for bus free\n");
687 ret
= i2c_pxa_set_master(i2c
);
689 dev_err(&i2c
->adap
.dev
, "i2c_pxa_set_master: error %d\n", ret
);
693 spin_lock_irq(&i2c
->lock
);
701 i2c_pxa_start_message(i2c
);
703 spin_unlock_irq(&i2c
->lock
);
706 * The rest of the processing occurs in the interrupt handler.
708 timeout
= wait_event_timeout(i2c
->wait
, i2c
->msg_num
== 0, HZ
* 5);
709 i2c_pxa_stop_message(i2c
);
712 * We place the return code in i2c->msg_idx.
717 i2c_pxa_scream_blue_murder(i2c
, "timeout");
723 static int i2c_pxa_pio_xfer(struct i2c_adapter
*adap
,
724 struct i2c_msg msgs
[], int num
)
726 struct pxa_i2c
*i2c
= adap
->algo_data
;
729 /* If the I2C controller is disabled we need to reset it
730 (probably due to a suspend/resume destroying state). We do
731 this here as we can then avoid worrying about resuming the
732 controller before its users. */
733 if (!(readl(_ICR(i2c
)) & ICR_IUE
))
736 for (i
= adap
->retries
; i
>= 0; i
--) {
737 ret
= i2c_pxa_do_pio_xfer(i2c
, msgs
, num
);
738 if (ret
!= I2C_RETRY
)
742 dev_dbg(&adap
->dev
, "Retrying transmission\n");
745 i2c_pxa_scream_blue_murder(i2c
, "exhausted retries");
748 i2c_pxa_set_slave(i2c
, ret
);
753 * i2c_pxa_master_complete - complete the message and wake up.
755 static void i2c_pxa_master_complete(struct pxa_i2c
*i2c
, int ret
)
767 static void i2c_pxa_irq_txempty(struct pxa_i2c
*i2c
, u32 isr
)
769 u32 icr
= readl(_ICR(i2c
)) & ~(ICR_START
|ICR_STOP
|ICR_ACKNAK
|ICR_TB
);
773 * If ISR_ALD is set, we lost arbitration.
777 * Do we need to do anything here? The PXA docs
778 * are vague about what happens.
780 i2c_pxa_scream_blue_murder(i2c
, "ALD set");
783 * We ignore this error. We seem to see spurious ALDs
784 * for seemingly no reason. If we handle them as I think
785 * they should, we end up causing an I2C error, which
786 * is painful for some systems.
795 * I2C bus error - either the device NAK'd us, or
796 * something more serious happened. If we were NAK'd
797 * on the initial address phase, we can retry.
799 if (isr
& ISR_ACKNAK
) {
800 if (i2c
->msg_ptr
== 0 && i2c
->msg_idx
== 0)
805 i2c_pxa_master_complete(i2c
, ret
);
806 } else if (isr
& ISR_RWM
) {
808 * Read mode. We have just sent the address byte, and
809 * now we must initiate the transfer.
811 if (i2c
->msg_ptr
== i2c
->msg
->len
- 1 &&
812 i2c
->msg_idx
== i2c
->msg_num
- 1)
813 icr
|= ICR_STOP
| ICR_ACKNAK
;
815 icr
|= ICR_ALDIE
| ICR_TB
;
816 } else if (i2c
->msg_ptr
< i2c
->msg
->len
) {
818 * Write mode. Write the next data byte.
820 writel(i2c
->msg
->buf
[i2c
->msg_ptr
++], _IDBR(i2c
));
822 icr
|= ICR_ALDIE
| ICR_TB
;
825 * If this is the last byte of the last message, send
828 if (i2c
->msg_ptr
== i2c
->msg
->len
&&
829 i2c
->msg_idx
== i2c
->msg_num
- 1)
831 } else if (i2c
->msg_idx
< i2c
->msg_num
- 1) {
833 * Next segment of the message.
840 * If we aren't doing a repeated start and address,
841 * go back and try to send the next byte. Note that
842 * we do not support switching the R/W direction here.
844 if (i2c
->msg
->flags
& I2C_M_NOSTART
)
848 * Write the next address.
850 writel(i2c_pxa_addr_byte(i2c
->msg
), _IDBR(i2c
));
853 * And trigger a repeated start, and send the byte.
856 icr
|= ICR_START
| ICR_TB
;
858 if (i2c
->msg
->len
== 0) {
860 * Device probes have a message length of zero
861 * and need the bus to be reset before it can
866 i2c_pxa_master_complete(i2c
, 0);
869 i2c
->icrlog
[i2c
->irqlogidx
-1] = icr
;
871 writel(icr
, _ICR(i2c
));
875 static void i2c_pxa_irq_rxfull(struct pxa_i2c
*i2c
, u32 isr
)
877 u32 icr
= readl(_ICR(i2c
)) & ~(ICR_START
|ICR_STOP
|ICR_ACKNAK
|ICR_TB
);
882 i2c
->msg
->buf
[i2c
->msg_ptr
++] = readl(_IDBR(i2c
));
884 if (i2c
->msg_ptr
< i2c
->msg
->len
) {
886 * If this is the last byte of the last
887 * message, send a STOP.
889 if (i2c
->msg_ptr
== i2c
->msg
->len
- 1)
890 icr
|= ICR_STOP
| ICR_ACKNAK
;
892 icr
|= ICR_ALDIE
| ICR_TB
;
894 i2c_pxa_master_complete(i2c
, 0);
897 i2c
->icrlog
[i2c
->irqlogidx
-1] = icr
;
899 writel(icr
, _ICR(i2c
));
902 static irqreturn_t
i2c_pxa_handler(int this_irq
, void *dev_id
)
904 struct pxa_i2c
*i2c
= dev_id
;
905 u32 isr
= readl(_ISR(i2c
));
907 if (i2c_debug
> 2 && 0) {
908 dev_dbg(&i2c
->adap
.dev
, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
909 __func__
, isr
, readl(_ICR(i2c
)), readl(_IBMR(i2c
)));
913 if (i2c
->irqlogidx
< ARRAY_SIZE(i2c
->isrlog
))
914 i2c
->isrlog
[i2c
->irqlogidx
++] = isr
;
919 * Always clear all pending IRQs.
921 writel(isr
& (ISR_SSD
|ISR_ALD
|ISR_ITE
|ISR_IRF
|ISR_SAD
|ISR_BED
), _ISR(i2c
));
924 i2c_pxa_slave_start(i2c
, isr
);
926 i2c_pxa_slave_stop(i2c
);
928 if (i2c_pxa_is_slavemode(i2c
)) {
930 i2c_pxa_slave_txempty(i2c
, isr
);
932 i2c_pxa_slave_rxfull(i2c
, isr
);
933 } else if (i2c
->msg
) {
935 i2c_pxa_irq_txempty(i2c
, isr
);
937 i2c_pxa_irq_rxfull(i2c
, isr
);
939 i2c_pxa_scream_blue_murder(i2c
, "spurious irq");
946 static int i2c_pxa_xfer(struct i2c_adapter
*adap
, struct i2c_msg msgs
[], int num
)
948 struct pxa_i2c
*i2c
= adap
->algo_data
;
951 for (i
= adap
->retries
; i
>= 0; i
--) {
952 ret
= i2c_pxa_do_xfer(i2c
, msgs
, num
);
953 if (ret
!= I2C_RETRY
)
957 dev_dbg(&adap
->dev
, "Retrying transmission\n");
960 i2c_pxa_scream_blue_murder(i2c
, "exhausted retries");
963 i2c_pxa_set_slave(i2c
, ret
);
967 static u32
i2c_pxa_functionality(struct i2c_adapter
*adap
)
969 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
972 static const struct i2c_algorithm i2c_pxa_algorithm
= {
973 .master_xfer
= i2c_pxa_xfer
,
974 .functionality
= i2c_pxa_functionality
,
977 static const struct i2c_algorithm i2c_pxa_pio_algorithm
= {
978 .master_xfer
= i2c_pxa_pio_xfer
,
979 .functionality
= i2c_pxa_functionality
,
982 #define res_len(r) ((r)->end - (r)->start + 1)
983 static int i2c_pxa_probe(struct platform_device
*dev
)
986 struct resource
*res
;
987 struct i2c_pxa_platform_data
*plat
= dev
->dev
.platform_data
;
991 res
= platform_get_resource(dev
, IORESOURCE_MEM
, 0);
992 irq
= platform_get_irq(dev
, 0);
993 if (res
== NULL
|| irq
< 0)
996 if (!request_mem_region(res
->start
, res_len(res
), res
->name
))
999 i2c
= kzalloc(sizeof(struct pxa_i2c
), GFP_KERNEL
);
1005 i2c
->adap
.owner
= THIS_MODULE
;
1006 i2c
->adap
.retries
= 5;
1008 spin_lock_init(&i2c
->lock
);
1009 init_waitqueue_head(&i2c
->wait
);
1012 * If "dev->id" is negative we consider it as zero.
1013 * The reason to do so is to avoid sysfs names that only make
1014 * sense when there are multiple adapters.
1016 i2c
->adap
.nr
= dev
->id
!= -1 ? dev
->id
: 0;
1017 snprintf(i2c
->adap
.name
, sizeof(i2c
->adap
.name
), "pxa_i2c-i2c.%u",
1020 i2c
->clk
= clk_get(&dev
->dev
, NULL
);
1021 if (IS_ERR(i2c
->clk
)) {
1022 ret
= PTR_ERR(i2c
->clk
);
1026 i2c
->reg_base
= ioremap(res
->start
, res_len(res
));
1027 if (!i2c
->reg_base
) {
1031 i2c
->reg_shift
= (cpu_is_pxa3xx() && (dev
->id
== 1)) ? 0 : 1;
1033 i2c
->iobase
= res
->start
;
1034 i2c
->iosize
= res_len(res
);
1038 i2c
->slave_addr
= I2C_PXA_SLAVE_ADDR
;
1040 #ifdef CONFIG_I2C_PXA_SLAVE
1042 i2c
->slave_addr
= plat
->slave_addr
;
1043 i2c
->slave
= plat
->slave
;
1047 clk_enable(i2c
->clk
);
1050 i2c
->adap
.class = plat
->class;
1051 i2c
->use_pio
= plat
->use_pio
;
1052 i2c
->fast_mode
= plat
->fast_mode
;
1056 i2c
->adap
.algo
= &i2c_pxa_pio_algorithm
;
1058 i2c
->adap
.algo
= &i2c_pxa_algorithm
;
1059 ret
= request_irq(irq
, i2c_pxa_handler
, IRQF_DISABLED
,
1060 i2c
->adap
.name
, i2c
);
1067 i2c
->adap
.algo_data
= i2c
;
1068 i2c
->adap
.dev
.parent
= &dev
->dev
;
1070 ret
= i2c_add_numbered_adapter(&i2c
->adap
);
1072 printk(KERN_INFO
"I2C: Failed to add bus\n");
1076 platform_set_drvdata(dev
, i2c
);
1078 #ifdef CONFIG_I2C_PXA_SLAVE
1079 printk(KERN_INFO
"I2C: %s: PXA I2C adapter, slave address %d\n",
1080 dev_name(&i2c
->adap
.dev
), i2c
->slave_addr
);
1082 printk(KERN_INFO
"I2C: %s: PXA I2C adapter\n",
1083 dev_name(&i2c
->adap
.dev
));
1091 clk_disable(i2c
->clk
);
1092 iounmap(i2c
->reg_base
);
1098 release_mem_region(res
->start
, res_len(res
));
1102 static int __exit
i2c_pxa_remove(struct platform_device
*dev
)
1104 struct pxa_i2c
*i2c
= platform_get_drvdata(dev
);
1106 platform_set_drvdata(dev
, NULL
);
1108 i2c_del_adapter(&i2c
->adap
);
1110 free_irq(i2c
->irq
, i2c
);
1112 clk_disable(i2c
->clk
);
1115 iounmap(i2c
->reg_base
);
1116 release_mem_region(i2c
->iobase
, i2c
->iosize
);
1123 static int i2c_pxa_suspend_late(struct platform_device
*dev
, pm_message_t state
)
1125 struct pxa_i2c
*i2c
= platform_get_drvdata(dev
);
1126 clk_disable(i2c
->clk
);
1130 static int i2c_pxa_resume_early(struct platform_device
*dev
)
1132 struct pxa_i2c
*i2c
= platform_get_drvdata(dev
);
1134 clk_enable(i2c
->clk
);
1140 #define i2c_pxa_suspend_late NULL
1141 #define i2c_pxa_resume_early NULL
1144 static struct platform_driver i2c_pxa_driver
= {
1145 .probe
= i2c_pxa_probe
,
1146 .remove
= __exit_p(i2c_pxa_remove
),
1147 .suspend_late
= i2c_pxa_suspend_late
,
1148 .resume_early
= i2c_pxa_resume_early
,
1150 .name
= "pxa2xx-i2c",
1151 .owner
= THIS_MODULE
,
1155 static int __init
i2c_adap_pxa_init(void)
1157 return platform_driver_register(&i2c_pxa_driver
);
1160 static void __exit
i2c_adap_pxa_exit(void)
1162 platform_driver_unregister(&i2c_pxa_driver
);
1165 MODULE_LICENSE("GPL");
1166 MODULE_ALIAS("platform:pxa2xx-i2c");
1168 subsys_initcall(i2c_adap_pxa_init
);
1169 module_exit(i2c_adap_pxa_exit
);