drivers/i2c/busses/i2c-rcar.c

   1 /*
   2  * Driver for the Renesas RCar I2C unit
   3  *
   4  * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
   5  * Copyright (C) 2011-2015 Renesas Electronics Corporation
   6  *
   7  * Copyright (C) 2012-14 Renesas Solutions Corp.
   8  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   9  *
  10  * This file is based on the drivers/i2c/busses/i2c-sh7760.c
  11  * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; version 2 of the License.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  */
  22 #include <linux/clk.h>
  23 #include <linux/delay.h>
  24 #include <linux/err.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/i2c.h>
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/of_device.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/slab.h>
  34
  35 /* register offsets */
  36 #define ICSCR   0x00    /* slave ctrl */
  37 #define ICMCR   0x04    /* master ctrl */
  38 #define ICSSR   0x08    /* slave status */
  39 #define ICMSR   0x0C    /* master status */
  40 #define ICSIER  0x10    /* slave irq enable */
  41 #define ICMIER  0x14    /* master irq enable */
  42 #define ICCCR   0x18    /* clock dividers */
  43 #define ICSAR   0x1C    /* slave address */
  44 #define ICMAR   0x20    /* master address */
  45 #define ICRXTX  0x24    /* data port */
  46
  47 /* ICSCR */
  48 #define SDBS    (1 << 3)        /* slave data buffer select */
  49 #define SIE     (1 << 2)        /* slave interface enable */
  50 #define GCAE    (1 << 1)        /* general call address enable */
  51 #define FNA     (1 << 0)        /* forced non acknowledgment */
  52
  53 /* ICMCR */
  54 #define MDBS    (1 << 7)        /* non-fifo mode switch */
  55 #define FSCL    (1 << 6)        /* override SCL pin */
  56 #define FSDA    (1 << 5)        /* override SDA pin */
  57 #define OBPC    (1 << 4)        /* override pins */
  58 #define MIE     (1 << 3)        /* master if enable */
  59 #define TSBE    (1 << 2)
  60 #define FSB     (1 << 1)        /* force stop bit */
  61 #define ESG     (1 << 0)        /* en startbit gen */
  62
  63 /* ICSSR (also for ICSIER) */
  64 #define GCAR    (1 << 6)        /* general call received */
  65 #define STM     (1 << 5)        /* slave transmit mode */
  66 #define SSR     (1 << 4)        /* stop received */
  67 #define SDE     (1 << 3)        /* slave data empty */
  68 #define SDT     (1 << 2)        /* slave data transmitted */
  69 #define SDR     (1 << 1)        /* slave data received */
  70 #define SAR     (1 << 0)        /* slave addr received */
  71
  72 /* ICMSR (also for ICMIE) */
  73 #define MNR     (1 << 6)        /* nack received */
  74 #define MAL     (1 << 5)        /* arbitration lost */
  75 #define MST     (1 << 4)        /* sent a stop */
  76 #define MDE     (1 << 3)
  77 #define MDT     (1 << 2)
  78 #define MDR     (1 << 1)
  79 #define MAT     (1 << 0)        /* slave addr xfer done */
  80
  81
  82 #define RCAR_BUS_PHASE_START    (MDBS | MIE | ESG)
  83 #define RCAR_BUS_PHASE_DATA     (MDBS | MIE)
  84 #define RCAR_BUS_MASK_DATA      (~(ESG | FSB) & 0xFF)
  85 #define RCAR_BUS_PHASE_STOP     (MDBS | MIE | FSB)
  86
  87 #define RCAR_IRQ_SEND   (MNR | MAL | MST | MAT | MDE)
  88 #define RCAR_IRQ_RECV   (MNR | MAL | MST | MAT | MDR)
  89 #define RCAR_IRQ_STOP   (MST)
  90
  91 #define RCAR_IRQ_ACK_SEND       (~(MAT | MDE) & 0xFF)
  92 #define RCAR_IRQ_ACK_RECV       (~(MAT | MDR) & 0xFF)
  93
  94 #define ID_LAST_MSG     (1 << 0)
  95 #define ID_FIRST_MSG    (1 << 1)
  96 #define ID_DONE         (1 << 2)
  97 #define ID_ARBLOST      (1 << 3)
  98 #define ID_NACK         (1 << 4)
  99 /* persistent flags */
 100 #define ID_P_PM_BLOCKED (1 << 31)
 101 #define ID_P_MASK       ID_P_PM_BLOCKED
 102
 103 enum rcar_i2c_type {
 104         I2C_RCAR_GEN1,
 105         I2C_RCAR_GEN2,
 106         I2C_RCAR_GEN3,
 107 };
 108
 109 struct rcar_i2c_priv {
 110         void __iomem *io;
 111         struct i2c_adapter adap;
 112         struct i2c_msg *msg;
 113         int msgs_left;
 114         struct clk *clk;
 115
 116         wait_queue_head_t wait;
 117
 118         int pos;
 119         u32 icccr;
 120         u32 flags;
 121         enum rcar_i2c_type devtype;
 122         struct i2c_client *slave;
 123 };
 124
 125 #define rcar_i2c_priv_to_dev(p)         ((p)->adap.dev.parent)
 126 #define rcar_i2c_is_recv(p)             ((p)->msg->flags & I2C_M_RD)
 127
 128 #define LOOP_TIMEOUT    1024
 129
 130
 131 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
 132 {
 133         writel(val, priv->io + reg);
 134 }
 135
 136 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
 137 {
 138         return readl(priv->io + reg);
 139 }
 140
 141 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
 142 {
 143         /* reset master mode */
 144         rcar_i2c_write(priv, ICMIER, 0);
 145         rcar_i2c_write(priv, ICMCR, MDBS);
 146         rcar_i2c_write(priv, ICMSR, 0);
 147         /* start clock */
 148         rcar_i2c_write(priv, ICCCR, priv->icccr);
 149 }
 150
 151 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
 152 {
 153         int i;
 154
 155         for (i = 0; i < LOOP_TIMEOUT; i++) {
 156                 /* make sure that bus is not busy */
 157                 if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
 158                         return 0;
 159                 udelay(1);
 160         }
 161
 162         return -EBUSY;
 163 }
 164
 165 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, struct i2c_timings *t)
 166 {
 167         u32 scgd, cdf, round, ick, sum, scl, cdf_width;
 168         unsigned long rate;
 169         struct device *dev = rcar_i2c_priv_to_dev(priv);
 170
 171         /* Fall back to previously used values if not supplied */
 172         t->bus_freq_hz = t->bus_freq_hz ?: 100000;
 173         t->scl_fall_ns = t->scl_fall_ns ?: 35;
 174         t->scl_rise_ns = t->scl_rise_ns ?: 200;
 175         t->scl_int_delay_ns = t->scl_int_delay_ns ?: 50;
 176
 177         switch (priv->devtype) {
 178         case I2C_RCAR_GEN1:
 179                 cdf_width = 2;
 180                 break;
 181         case I2C_RCAR_GEN2:
 182         case I2C_RCAR_GEN3:
 183                 cdf_width = 3;
 184                 break;
 185         default:
 186                 dev_err(dev, "device type error\n");
 187                 return -EIO;
 188         }
 189
 190         /*
 191          * calculate SCL clock
 192          * see
 193          *      ICCCR
 194          *
 195          * ick  = clkp / (1 + CDF)
 196          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
 197          *
 198          * ick  : I2C internal clock < 20 MHz
 199          * ticf : I2C SCL falling time
 200          * tr   : I2C SCL rising  time
 201          * intd : LSI internal delay
 202          * clkp : peripheral_clk
 203          * F[]  : integer up-valuation
 204          */
 205         rate = clk_get_rate(priv->clk);
 206         cdf = rate / 20000000;
 207         if (cdf >= 1U << cdf_width) {
 208                 dev_err(dev, "Input clock %lu too high\n", rate);
 209                 return -EIO;
 210         }
 211         ick = rate / (cdf + 1);
 212
 213         /*
 214          * it is impossible to calculate large scale
 215          * number on u32. separate it
 216          *
 217          * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
 218          *  = F[sum * ick / 1000000000]
 219          *  = F[(ick / 1000000) * sum / 1000]
 220          */
 221         sum = t->scl_fall_ns + t->scl_rise_ns + t->scl_int_delay_ns;
 222         round = (ick + 500000) / 1000000 * sum;
 223         round = (round + 500) / 1000;
 224
 225         /*
 226          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
 227          *
 228          * Calculation result (= SCL) should be less than
 229          * bus_speed for hardware safety
 230          *
 231          * We could use something along the lines of
 232          *      div = ick / (bus_speed + 1) + 1;
 233          *      scgd = (div - 20 - round + 7) / 8;
 234          *      scl = ick / (20 + (scgd * 8) + round);
 235          * (not fully verified) but that would get pretty involved
 236          */
 237         for (scgd = 0; scgd < 0x40; scgd++) {
 238                 scl = ick / (20 + (scgd * 8) + round);
 239                 if (scl <= t->bus_freq_hz)
 240                         goto scgd_find;
 241         }
 242         dev_err(dev, "it is impossible to calculate best SCL\n");
 243         return -EIO;
 244
 245 scgd_find:
 246         dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
 247                 scl, t->bus_freq_hz, clk_get_rate(priv->clk), round, cdf, scgd);
 248
 249         /* keep icccr value */
 250         priv->icccr = scgd << cdf_width | cdf;
 251
 252         return 0;
 253 }
 254
 255 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
 256 {
 257         int read = !!rcar_i2c_is_recv(priv);
 258
 259         priv->pos = 0;
 260         if (priv->msgs_left == 1)
 261                 priv->flags |= ID_LAST_MSG;
 262
 263         rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read);
 264         /*
 265          * We don't have a testcase but the HW engineers say that the write order
 266          * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since
 267          * it didn't cause a drawback for me, let's rather be safe than sorry.
 268          */
 269         if (priv->flags & ID_FIRST_MSG) {
 270                 rcar_i2c_write(priv, ICMSR, 0);
 271                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
 272         } else {
 273                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
 274                 rcar_i2c_write(priv, ICMSR, 0);
 275         }
 276         rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
 277 }
 278
 279 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
 280 {
 281         priv->msg++;
 282         priv->msgs_left--;
 283         priv->flags &= ID_P_MASK;
 284         rcar_i2c_prepare_msg(priv);
 285 }
 286
 287 /*
 288  *              interrupt functions
 289  */
 290 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
 291 {
 292         struct i2c_msg *msg = priv->msg;
 293
 294         /* FIXME: sometimes, unknown interrupt happened. Do nothing */
 295         if (!(msr & MDE))
 296                 return;
 297
 298         if (priv->pos < msg->len) {
 299                 /*
 300                  * Prepare next data to ICRXTX register.
 301                  * This data will go to _SHIFT_ register.
 302                  *
 303                  *    *
 304                  * [ICRXTX] -> [SHIFT] -> [I2C bus]
 305                  */
 306                 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
 307                 priv->pos++;
 308
 309         } else {
 310                 /*
 311                  * The last data was pushed to ICRXTX on _PREV_ empty irq.
 312                  * It is on _SHIFT_ register, and will sent to I2C bus.
 313                  *
 314                  *                *
 315                  * [ICRXTX] -> [SHIFT] -> [I2C bus]
 316                  */
 317
 318                 if (priv->flags & ID_LAST_MSG) {
 319                         /*
 320                          * If current msg is the _LAST_ msg,
 321                          * prepare stop condition here.
 322                          * ID_DONE will be set on STOP irq.
 323                          */
 324                         rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
 325                 } else {
 326                         rcar_i2c_next_msg(priv);
 327                         return;
 328                 }
 329         }
 330
 331         rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
 332 }
 333
 334 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
 335 {
 336         struct i2c_msg *msg = priv->msg;
 337
 338         /* FIXME: sometimes, unknown interrupt happened. Do nothing */
 339         if (!(msr & MDR))
 340                 return;
 341
 342         if (msr & MAT) {
 343                 /* Address transfer phase finished, but no data at this point. */
 344         } else if (priv->pos < msg->len) {
 345                 /* get received data */
 346                 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
 347                 priv->pos++;
 348         }
 349
 350         /*
 351          * If next received data is the _LAST_, go to STOP phase. Might be
 352          * overwritten by REP START when setting up a new msg. Not elegant
 353          * but the only stable sequence for REP START I have found so far.
 354          */
 355         if (priv->pos + 1 >= msg->len)
 356                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
 357
 358         if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG))
 359                 rcar_i2c_next_msg(priv);
 360         else
 361                 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
 362 }
 363
 364 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
 365 {
 366         u32 ssr_raw, ssr_filtered;
 367         u8 value;
 368
 369         ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff;
 370         ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER);
 371
 372         if (!ssr_filtered)
 373                 return false;
 374
 375         /* address detected */
 376         if (ssr_filtered & SAR) {
 377                 /* read or write request */
 378                 if (ssr_raw & STM) {
 379                         i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value);
 380                         rcar_i2c_write(priv, ICRXTX, value);
 381                         rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
 382                 } else {
 383                         i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
 384                         rcar_i2c_read(priv, ICRXTX);    /* dummy read */
 385                         rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
 386                 }
 387
 388                 rcar_i2c_write(priv, ICSSR, ~SAR & 0xff);
 389         }
 390
 391         /* master sent stop */
 392         if (ssr_filtered & SSR) {
 393                 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
 394                 rcar_i2c_write(priv, ICSIER, SAR | SSR);
 395                 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
 396         }
 397
 398         /* master wants to write to us */
 399         if (ssr_filtered & SDR) {
 400                 int ret;
 401
 402                 value = rcar_i2c_read(priv, ICRXTX);
 403                 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
 404                 /* Send NACK in case of error */
 405                 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0));
 406                 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
 407         }
 408
 409         /* master wants to read from us */
 410         if (ssr_filtered & SDE) {
 411                 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value);
 412                 rcar_i2c_write(priv, ICRXTX, value);
 413                 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
 414         }
 415
 416         return true;
 417 }
 418
 419 static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
 420 {
 421         struct rcar_i2c_priv *priv = ptr;
 422         u32 msr, val;
 423
 424         /* Clear START or STOP as soon as we can */
 425         val = rcar_i2c_read(priv, ICMCR);
 426         rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA);
 427
 428         msr = rcar_i2c_read(priv, ICMSR);
 429
 430         /* Only handle interrupts that are currently enabled */
 431         msr &= rcar_i2c_read(priv, ICMIER);
 432         if (!msr) {
 433                 if (rcar_i2c_slave_irq(priv))
 434                         return IRQ_HANDLED;
 435
 436                 return IRQ_NONE;
 437         }
 438
 439         /* Arbitration lost */
 440         if (msr & MAL) {
 441                 priv->flags |= ID_DONE | ID_ARBLOST;
 442                 goto out;
 443         }
 444
 445         /* Nack */
 446         if (msr & MNR) {
 447                 /* HW automatically sends STOP after received NACK */
 448                 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
 449                 priv->flags |= ID_NACK;
 450                 goto out;
 451         }
 452
 453         /* Stop */
 454         if (msr & MST) {
 455                 priv->msgs_left--; /* The last message also made it */
 456                 priv->flags |= ID_DONE;
 457                 goto out;
 458         }
 459
 460         if (rcar_i2c_is_recv(priv))
 461                 rcar_i2c_irq_recv(priv, msr);
 462         else
 463                 rcar_i2c_irq_send(priv, msr);
 464
 465 out:
 466         if (priv->flags & ID_DONE) {
 467                 rcar_i2c_write(priv, ICMIER, 0);
 468                 rcar_i2c_write(priv, ICMSR, 0);
 469                 wake_up(&priv->wait);
 470         }
 471
 472         return IRQ_HANDLED;
 473 }
 474
 475 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
 476                                 struct i2c_msg *msgs,
 477                                 int num)
 478 {
 479         struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
 480         struct device *dev = rcar_i2c_priv_to_dev(priv);
 481         int i, ret;
 482         long time_left;
 483
 484         pm_runtime_get_sync(dev);
 485
 486         ret = rcar_i2c_bus_barrier(priv);
 487         if (ret < 0)
 488                 goto out;
 489
 490         for (i = 0; i < num; i++) {
 491                 /* This HW can't send STOP after address phase */
 492                 if (msgs[i].len == 0) {
 493                         ret = -EOPNOTSUPP;
 494                         goto out;
 495                 }
 496         }
 497
 498         /* init first message */
 499         priv->msg = msgs;
 500         priv->msgs_left = num;
 501         priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG;
 502         rcar_i2c_prepare_msg(priv);
 503
 504         time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE,
 505                                      num * adap->timeout);
 506         if (!time_left) {
 507                 rcar_i2c_init(priv);
 508                 ret = -ETIMEDOUT;
 509         } else if (priv->flags & ID_NACK) {
 510                 ret = -ENXIO;
 511         } else if (priv->flags & ID_ARBLOST) {
 512                 ret = -EAGAIN;
 513         } else {
 514                 ret = num - priv->msgs_left; /* The number of transfer */
 515         }
 516 out:
 517         pm_runtime_put(dev);
 518
 519         if (ret < 0 && ret != -ENXIO)
 520                 dev_err(dev, "error %d : %x\n", ret, priv->flags);
 521
 522         return ret;
 523 }
 524
 525 static int rcar_reg_slave(struct i2c_client *slave)
 526 {
 527         struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
 528
 529         if (priv->slave)
 530                 return -EBUSY;
 531
 532         if (slave->flags & I2C_CLIENT_TEN)
 533                 return -EAFNOSUPPORT;
 534
 535         pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv));
 536
 537         priv->slave = slave;
 538         rcar_i2c_write(priv, ICSAR, slave->addr);
 539         rcar_i2c_write(priv, ICSSR, 0);
 540         rcar_i2c_write(priv, ICSIER, SAR | SSR);
 541         rcar_i2c_write(priv, ICSCR, SIE | SDBS);
 542
 543         return 0;
 544 }
 545
 546 static int rcar_unreg_slave(struct i2c_client *slave)
 547 {
 548         struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
 549
 550         WARN_ON(!priv->slave);
 551
 552         rcar_i2c_write(priv, ICSIER, 0);
 553         rcar_i2c_write(priv, ICSCR, 0);
 554
 555         priv->slave = NULL;
 556
 557         pm_runtime_put(rcar_i2c_priv_to_dev(priv));
 558
 559         return 0;
 560 }
 561
 562 static u32 rcar_i2c_func(struct i2c_adapter *adap)
 563 {
 564         /* This HW can't do SMBUS_QUICK and NOSTART */
 565         return I2C_FUNC_I2C | I2C_FUNC_SLAVE |
 566                 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 567 }
 568
 569 static const struct i2c_algorithm rcar_i2c_algo = {
 570         .master_xfer    = rcar_i2c_master_xfer,
 571         .functionality  = rcar_i2c_func,
 572         .reg_slave      = rcar_reg_slave,
 573         .unreg_slave    = rcar_unreg_slave,
 574 };
 575
 576 static const struct of_device_id rcar_i2c_dt_ids[] = {
 577         { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
 578         { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
 579         { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
 580         { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
 581         { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
 582         { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
 583         { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
 584         { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
 585         { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 },
 586         {},
 587 };
 588 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
 589
 590 static int rcar_i2c_probe(struct platform_device *pdev)
 591 {
 592         struct rcar_i2c_priv *priv;
 593         struct i2c_adapter *adap;
 594         struct resource *res;
 595         struct device *dev = &pdev->dev;
 596         struct i2c_timings i2c_t;
 597         int irq, ret;
 598
 599         priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
 600         if (!priv)
 601                 return -ENOMEM;
 602
 603         priv->clk = devm_clk_get(dev, NULL);
 604         if (IS_ERR(priv->clk)) {
 605                 dev_err(dev, "cannot get clock\n");
 606                 return PTR_ERR(priv->clk);
 607         }
 608
 609         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 610         priv->io = devm_ioremap_resource(dev, res);
 611         if (IS_ERR(priv->io))
 612                 return PTR_ERR(priv->io);
 613
 614         priv->devtype = (enum rcar_i2c_type)of_match_device(rcar_i2c_dt_ids, dev)->data;
 615         init_waitqueue_head(&priv->wait);
 616
 617         adap = &priv->adap;
 618         adap->nr = pdev->id;
 619         adap->algo = &rcar_i2c_algo;
 620         adap->class = I2C_CLASS_DEPRECATED;
 621         adap->retries = 3;
 622         adap->dev.parent = dev;
 623         adap->dev.of_node = dev->of_node;
 624         i2c_set_adapdata(adap, priv);
 625         strlcpy(adap->name, pdev->name, sizeof(adap->name));
 626
 627         i2c_parse_fw_timings(dev, &i2c_t, false);
 628
 629         pm_runtime_enable(dev);
 630         pm_runtime_get_sync(dev);
 631         ret = rcar_i2c_clock_calculate(priv, &i2c_t);
 632         if (ret < 0)
 633                 goto out_pm_put;
 634
 635         rcar_i2c_init(priv);
 636
 637         /* Don't suspend when multi-master to keep arbitration working */
 638         if (of_property_read_bool(dev->of_node, "multi-master"))
 639                 priv->flags |= ID_P_PM_BLOCKED;
 640         else
 641                 pm_runtime_put(dev);
 642
 643
 644         irq = platform_get_irq(pdev, 0);
 645         ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0, dev_name(dev), priv);
 646         if (ret < 0) {
 647                 dev_err(dev, "cannot get irq %d\n", irq);
 648                 goto out_pm_disable;
 649         }
 650
 651         platform_set_drvdata(pdev, priv);
 652
 653         ret = i2c_add_numbered_adapter(adap);
 654         if (ret < 0) {
 655                 dev_err(dev, "reg adap failed: %d\n", ret);
 656                 goto out_pm_disable;
 657         }
 658
 659         dev_info(dev, "probed\n");
 660
 661         return 0;
 662
 663  out_pm_put:
 664         pm_runtime_put(dev);
 665  out_pm_disable:
 666         pm_runtime_disable(dev);
 667         return ret;
 668 }
 669
 670 static int rcar_i2c_remove(struct platform_device *pdev)
 671 {
 672         struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
 673         struct device *dev = &pdev->dev;
 674
 675         i2c_del_adapter(&priv->adap);
 676         if (priv->flags & ID_P_PM_BLOCKED)
 677                 pm_runtime_put(dev);
 678         pm_runtime_disable(dev);
 679
 680         return 0;
 681 }
 682
 683 static struct platform_driver rcar_i2c_driver = {
 684         .driver = {
 685                 .name   = "i2c-rcar",
 686                 .of_match_table = rcar_i2c_dt_ids,
 687         },
 688         .probe          = rcar_i2c_probe,
 689         .remove         = rcar_i2c_remove,
 690 };
 691
 692 module_platform_driver(rcar_i2c_driver);
 693
 694 MODULE_LICENSE("GPL v2");
 695 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
 696 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");